1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/px30-cru.h> 7#include <dt-bindings/display/media-bus-format.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/power/px30-power.h> 13#include <dt-bindings/soc/rockchip,boot-mode.h> 14#include <dt-bindings/soc/rockchip-system-status.h> 15#include <dt-bindings/suspend/rockchip-px30.h> 16#include <dt-bindings/thermal/thermal.h> 17#include "px30-dram-default-timing.dtsi" 18#include "px30s-dram-default-timing.dtsi" 19 20/ { 21 compatible = "rockchip,px30"; 22 23 interrupt-parent = <&gic>; 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 aliases { 28 ethernet0 = &gmac; 29 i2c0 = &i2c0; 30 i2c1 = &i2c1; 31 i2c2 = &i2c2; 32 i2c3 = &i2c3; 33 mmc0 = &sdmmc; 34 mmc1 = &sdio; 35 mmc2 = &emmc; 36 serial0 = &uart0; 37 serial1 = &uart1; 38 serial2 = &uart2; 39 serial3 = &uart3; 40 serial4 = &uart4; 41 serial5 = &uart5; 42 spi0 = &spi0; 43 spi1 = &spi1; 44 spi2 = &sfc; 45 }; 46 47 cpus { 48 #address-cells = <2>; 49 #size-cells = <0>; 50 51 cpu0: cpu@0 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a35"; 54 reg = <0x0 0x0>; 55 enable-method = "psci"; 56 clocks = <&cru ARMCLK>; 57 #cooling-cells = <2>; 58 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 59 dynamic-power-coefficient = <90>; 60 operating-points-v2 = <&cpu0_opp_table>; 61 }; 62 63 cpu1: cpu@1 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a35"; 66 reg = <0x0 0x1>; 67 enable-method = "psci"; 68 clocks = <&cru ARMCLK>; 69 #cooling-cells = <2>; 70 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 71 dynamic-power-coefficient = <90>; 72 operating-points-v2 = <&cpu0_opp_table>; 73 }; 74 75 cpu2: cpu@2 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a35"; 78 reg = <0x0 0x2>; 79 enable-method = "psci"; 80 clocks = <&cru ARMCLK>; 81 #cooling-cells = <2>; 82 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 83 dynamic-power-coefficient = <90>; 84 operating-points-v2 = <&cpu0_opp_table>; 85 }; 86 87 cpu3: cpu@3 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a35"; 90 reg = <0x0 0x3>; 91 enable-method = "psci"; 92 clocks = <&cru ARMCLK>; 93 #cooling-cells = <2>; 94 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 95 dynamic-power-coefficient = <90>; 96 operating-points-v2 = <&cpu0_opp_table>; 97 }; 98 99 idle-states { 100 entry-method = "psci"; 101 102 CPU_SLEEP: cpu-sleep { 103 compatible = "arm,idle-state"; 104 local-timer-stop; 105 arm,psci-suspend-param = <0x0010000>; 106 entry-latency-us = <120>; 107 exit-latency-us = <250>; 108 min-residency-us = <900>; 109 }; 110 111 CLUSTER_SLEEP: cluster-sleep { 112 compatible = "arm,idle-state"; 113 local-timer-stop; 114 arm,psci-suspend-param = <0x1010000>; 115 entry-latency-us = <400>; 116 exit-latency-us = <500>; 117 min-residency-us = <2000>; 118 }; 119 }; 120 }; 121 122 cpu0_opp_table: cpu0-opp-table { 123 compatible = "operating-points-v2"; 124 opp-shared; 125 126 rockchip,temp-hysteresis = <5000>; 127 rockchip,low-temp = <0>; 128 rockchip,low-temp-min-volt = <1000000>; 129 rockchip,low-temp-adjust-volt = < 130 /* MHz MHz uV */ 131 0 1512 50000 132 >; 133 134 clocks = <&cru PLL_APLL>; 135 rockchip,avs-scale = <4>; 136 rockchip,max-volt = <1350000>; 137 rockchip,evb-irdrop = <25000>; 138 nvmem-cells = <&cpu_leakage>, <&performance>; 139 nvmem-cell-names = "cpu_leakage", "performance"; 140 rockchip,bin-scaling-sel = < 141 0 13 142 1 15 143 >; 144 145 rockchip,pvtm-voltage-sel = < 146 0 50000 0 147 50001 54000 1 148 54001 60000 2 149 60001 99999 3 150 >; 151 rockchip,pvtm-freq = <408000>; 152 rockchip,pvtm-volt = <1000000>; 153 rockchip,pvtm-ch = <0 0>; 154 rockchip,pvtm-sample-time = <1000>; 155 rockchip,pvtm-number = <10>; 156 rockchip,pvtm-error = <1000>; 157 rockchip,pvtm-ref-temp = <40>; 158 rockchip,pvtm-temp-prop = <(-56) (-56)>; 159 rockchip,thermal-zone = "soc-thermal"; 160 161 opp-408000000 { 162 opp-hz = /bits/ 64 <408000000>; 163 opp-microvolt = <950000 950000 1350000>; 164 opp-microvolt-L0 = <950000 950000 1350000>; 165 opp-microvolt-L1 = <950000 950000 1350000>; 166 opp-microvolt-L2 = <950000 950000 1350000>; 167 opp-microvolt-L3 = <950000 950000 1350000>; 168 clock-latency-ns = <40000>; 169 opp-suspend; 170 }; 171 opp-600000000 { 172 opp-hz = /bits/ 64 <600000000>; 173 opp-microvolt = <950000 950000 1350000>; 174 opp-microvolt-L0 = <950000 950000 1350000>; 175 opp-microvolt-L1 = <950000 950000 1350000>; 176 opp-microvolt-L2 = <950000 950000 1350000>; 177 opp-microvolt-L3 = <950000 950000 1350000>; 178 clock-latency-ns = <40000>; 179 }; 180 opp-816000000 { 181 opp-hz = /bits/ 64 <816000000>; 182 opp-microvolt = <1050000 1050000 1350000>; 183 opp-microvolt-L0 = <1050000 1050000 1350000>; 184 opp-microvolt-L1 = <1000000 1000000 1350000>; 185 opp-microvolt-L2 = <1000000 1000000 1350000>; 186 opp-microvolt-L3 = <950000 950000 1350000>; 187 clock-latency-ns = <40000>; 188 }; 189 opp-1008000000 { 190 opp-hz = /bits/ 64 <1008000000>; 191 opp-microvolt = <1175000 1175000 1350000>; 192 opp-microvolt-L0 = <1175000 1175000 1350000>; 193 opp-microvolt-L1 = <1125000 1125000 1350000>; 194 opp-microvolt-L2 = <1125000 1125000 1350000>; 195 opp-microvolt-L3 = <1050000 1050000 1350000>; 196 clock-latency-ns = <40000>; 197 }; 198 opp-1200000000 { 199 opp-hz = /bits/ 64 <1200000000>; 200 opp-microvolt = <1300000 1300000 1350000>; 201 opp-microvolt-L0 = <1300000 1300000 1350000>; 202 opp-microvolt-L1 = <1275000 1275000 1350000>; 203 opp-microvolt-L2 = <1250000 1250000 1350000>; 204 opp-microvolt-L3 = <1200000 1200000 1350000>; 205 clock-latency-ns = <40000>; 206 }; 207 opp-1248000000 { 208 opp-hz = /bits/ 64 <1248000000>; 209 opp-microvolt = <1350000 1350000 1350000>; 210 opp-microvolt-L0 = <1350000 1350000 1350000>; 211 opp-microvolt-L1 = <1300000 1300000 1350000>; 212 opp-microvolt-L2 = <1275000 1275000 1350000>; 213 opp-microvolt-L3 = <1225000 1225000 1350000>; 214 clock-latency-ns = <40000>; 215 }; 216 opp-1296000000 { 217 opp-hz = /bits/ 64 <1296000000>; 218 opp-microvolt = <1350000 1350000 1350000>; 219 opp-microvolt-L0 = <1350000 1350000 1350000>; 220 opp-microvolt-L1 = <1350000 1350000 1350000>; 221 opp-microvolt-L2 = <1300000 1300000 1350000>; 222 opp-microvolt-L3 = <1250000 1250000 1350000>; 223 clock-latency-ns = <40000>; 224 }; 225 opp-1416000000 { 226 opp-hz = /bits/ 64 <1416000000>; 227 opp-microvolt = <1350000 1350000 1350000>; 228 opp-microvolt-L0 = <1350000 1350000 1350000>; 229 opp-microvolt-L1 = <1350000 1350000 1350000>; 230 opp-microvolt-L2 = <1300000 1300000 1350000>; 231 opp-microvolt-L3 = <1250000 1250000 1350000>; 232 clock-latency-ns = <40000>; 233 }; 234 opp-1512000000 { 235 opp-hz = /bits/ 64 <1512000000>; 236 opp-microvolt = <1350000 1350000 1350000>; 237 opp-microvolt-L0 = <1350000 1350000 1350000>; 238 opp-microvolt-L1 = <1350000 1350000 1350000>; 239 opp-microvolt-L2 = <1300000 1300000 1350000>; 240 opp-microvolt-L3 = <1250000 1250000 1350000>; 241 clock-latency-ns = <40000>; 242 }; 243 }; 244 245 px30s_cpu0_opp_table: px30s-cpu0-opp-table { 246 compatible = "operating-points-v2"; 247 opp-shared; 248 249 nvmem-cells = <&cpu_leakage>; 250 nvmem-cell-names = "cpu_leakage"; 251 252 rockchip,pvtm-voltage-sel = < 253 0 69850 0 254 69851 73800 1 255 73801 77750 2 256 77751 81700 3 257 81701 99999 4 258 >; 259 260 rockchip,pvtm-freq = <408000>; 261 rockchip,pvtm-volt = <900000>; 262 rockchip,pvtm-ch = <0 0>; 263 rockchip,pvtm-sample-time = <1000>; 264 rockchip,pvtm-number = <10>; 265 rockchip,pvtm-error = <1000>; 266 rockchip,pvtm-ref-temp = <0>; 267 rockchip,pvtm-temp-prop = <0 0>; 268 rockchip,thermal-zone = "soc-thermal"; 269 270 opp-408000000 { 271 opp-hz = /bits/ 64 <408000000>; 272 opp-microvolt = <850000 850000 1150000>; 273 clock-latency-ns = <40000>; 274 opp-suspend; 275 }; 276 opp-600000000 { 277 opp-hz = /bits/ 64 <600000000>; 278 opp-microvolt = <850000 850000 1150000>; 279 clock-latency-ns = <40000>; 280 }; 281 opp-816000000 { 282 opp-hz = /bits/ 64 <816000000>; 283 opp-microvolt = <850000 850000 1150000>; 284 clock-latency-ns = <40000>; 285 }; 286 opp-1008000000 { 287 opp-hz = /bits/ 64 <1008000000>; 288 opp-microvolt = <950000 950000 1150000>; 289 opp-microvolt-L0 = <950000 950000 1150000>; 290 opp-microvolt-L1 = <925000 925000 1150000>; 291 opp-microvolt-L2 = <900000 900000 1150000>; 292 opp-microvolt-L3 = <875000 875000 1150000>; 293 opp-microvolt-L4 = <850000 850000 1150000>; 294 clock-latency-ns = <40000>; 295 }; 296 opp-1200000000 { 297 opp-hz = /bits/ 64 <1200000000>; 298 opp-microvolt = <1050000 1050000 1150000>; 299 opp-microvolt-L0 = <1050000 1050000 1150000>; 300 opp-microvolt-L1 = <1025000 1025000 1150000>; 301 opp-microvolt-L2 = <1000000 1000000 1150000>; 302 opp-microvolt-L3 = <975000 975000 1150000>; 303 opp-microvolt-L4 = <950000 950000 1150000>; 304 clock-latency-ns = <40000>; 305 }; 306 opp-1248000000 { 307 opp-hz = /bits/ 64 <1248000000>; 308 opp-microvolt = <1075000 1075000 1150000>; 309 opp-microvolt-L0 = <1075000 1075000 1150000>; 310 opp-microvolt-L1 = <1050000 1050000 1150000>; 311 opp-microvolt-L2 = <1025000 1025000 1150000>; 312 opp-microvolt-L3 = <1000000 1000000 1150000>; 313 opp-microvolt-L4 = <975000 975000 1150000>; 314 clock-latency-ns = <40000>; 315 }; 316 opp-1296000000 { 317 opp-hz = /bits/ 64 <1296000000>; 318 opp-microvolt = <1100000 1100000 1150000>; 319 opp-microvolt-L0 = <1100000 1100000 1150000>; 320 opp-microvolt-L1 = <1075000 1075000 1150000>; 321 opp-microvolt-L2 = <1050000 1050000 1150000>; 322 opp-microvolt-L3 = <1025000 1025000 1150000>; 323 opp-microvolt-L4 = <1000000 1000000 1150000>; 324 clock-latency-ns = <40000>; 325 }; 326 opp-1416000000 { 327 opp-hz = /bits/ 64 <1416000000>; 328 opp-microvolt = <1150000 1150000 1150000>; 329 opp-microvolt-L0 = <1150000 1150000 1150000>; 330 opp-microvolt-L1 = <1125000 1125000 1150000>; 331 opp-microvolt-L2 = <1100000 1100000 1150000>; 332 opp-microvolt-L3 = <1075000 1075000 1150000>; 333 opp-microvolt-L4 = <1050000 1050000 1150000>; 334 clock-latency-ns = <40000>; 335 }; 336 opp-1512000000 { 337 opp-hz = /bits/ 64 <1512000000>; 338 opp-microvolt = <1150000 1150000 1150000>; 339 opp-microvolt-L0 = <1150000 1150000 1150000>; 340 opp-microvolt-L1 = <1125000 1125000 1150000>; 341 opp-microvolt-L2 = <1100000 1100000 1150000>; 342 opp-microvolt-L3 = <1075000 1075000 1150000>; 343 opp-microvolt-L4 = <1050000 1050000 1150000>; 344 clock-latency-ns = <40000>; 345 }; 346 }; 347 348 arm-pmu { 349 compatible = "arm,cortex-a35-pmu"; 350 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 354 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 355 }; 356 357 bus_soc: bus-soc { 358 compatible = "rockchip,px30-bus"; 359 rockchip,busfreq-policy = "autocs"; 360 soc-bus0 { 361 bus-id = <0>; 362 timer-us = <20>; 363 enable-msk = <0x40f7>; 364 }; 365 soc-bus1 { 366 bus-id = <1>; 367 timer-us = <200>; 368 enable-msk = <0x40bf>; 369 status = "disabled"; 370 }; 371 soc-bus2 { 372 bus-id = <2>; 373 timer-us = <200>; 374 enable-msk = <0x4007>; 375 status = "disabled"; 376 }; 377 }; 378 379 bus_apll: bus-apll { 380 compatible = "rockchip,px30-bus"; 381 rockchip,busfreq-policy = "clkfreq"; 382 clocks = <&cru PLL_APLL>; 383 clock-names = "bus"; 384 operating-points-v2 = <&bus_apll_opp_table>; 385 status = "disabled"; 386 }; 387 388 bus_apll_opp_table: bus-apll-opp-table { 389 compatible = "operating-points-v2"; 390 opp-shared; 391 392 opp-1512000000 { 393 opp-hz = /bits/ 64 <1512000000>; 394 opp-microvolt = <1000000>; 395 }; 396 opp-1008000000 { 397 opp-hz = /bits/ 64 <1008000000>; 398 opp-microvolt = <950000>; 399 }; 400 }; 401 402 cpuinfo { 403 compatible = "rockchip,cpuinfo"; 404 nvmem-cells = <&cpu_id>; 405 nvmem-cell-names = "id"; 406 }; 407 408 display_subsystem: display-subsystem { 409 compatible = "rockchip,display-subsystem"; 410 ports = <&vopb_out>, <&vopl_out>; 411 status = "disabled"; 412 }; 413 414 firmware { 415 optee: optee { 416 compatible = "linaro,optee-tz"; 417 method = "smc"; 418 }; 419 420 scmi: scmi { 421 compatible = "arm,scmi-smc"; 422 shmem = <&scmi_shmem>; 423 arm,smc-id = <0x82000010>; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 427 scmi_clk: protocol@14 { 428 reg = <0x14>; 429 #clock-cells = <1>; 430 }; 431 }; 432 433 sdei: sdei { 434 compatible = "arm,sdei-1.0"; 435 method = "smc"; 436 }; 437 }; 438 439 gmac_clkin: external-gmac-clock { 440 compatible = "fixed-clock"; 441 clock-frequency = <50000000>; 442 clock-output-names = "gmac_clkin"; 443 #clock-cells = <0>; 444 }; 445 446 psci { 447 compatible = "arm,psci-1.0"; 448 method = "smc"; 449 }; 450 451 rockchip_suspend: rockchip-suspend { 452 compatible = "rockchip,pm-px30"; 453 status = "disabled"; 454 rockchip,sleep-debug-en = <0>; 455 rockchip,sleep-mode-config = < 456 (0 457 | RKPM_SLP_ARMOFF 458 | RKPM_SLP_PMU_HW_PLLS_PD 459 | RKPM_SLP_PMU_PMUALIVE_32K 460 | RKPM_SLP_PMU_DIS_OSC 461 | RKPM_SLP_PMIC_LP 462 ) 463 >; 464 rockchip,wakeup-config = < 465 (0 466 | RKPM_CLUSTER_WKUP_EN 467 | RKPM_GPIO_WKUP_EN 468 | RKPM_USB_WKUP_EN 469 ) 470 >; 471 }; 472 473 timer { 474 compatible = "arm,armv8-timer"; 475 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 476 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 477 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 478 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 479 }; 480 481 thermal_zones: thermal-zones { 482 soc_thermal: soc-thermal { 483 polling-delay-passive = <20>; 484 polling-delay = <1000>; 485 sustainable-power = <750>; 486 thermal-sensors = <&tsadc 0>; 487 488 trips { 489 threshold: trip-point-0 { 490 temperature = <70000>; 491 hysteresis = <2000>; 492 type = "passive"; 493 }; 494 495 target: trip-point-1 { 496 temperature = <85000>; 497 hysteresis = <2000>; 498 type = "passive"; 499 }; 500 501 soc_crit: soc-crit { 502 temperature = <115000>; 503 hysteresis = <2000>; 504 type = "critical"; 505 }; 506 }; 507 508 cooling-maps { 509 map0 { 510 trip = <&target>; 511 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 512 contribution = <4096>; 513 }; 514 515 map1 { 516 trip = <&target>; 517 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 518 contribution = <4096>; 519 }; 520 }; 521 }; 522 523 gpu_thermal: gpu-thermal { 524 polling-delay-passive = <100>; /* milliseconds */ 525 polling-delay = <1000>; /* milliseconds */ 526 thermal-sensors = <&tsadc 1>; 527 }; 528 }; 529 530 xin24m: xin24m { 531 compatible = "fixed-clock"; 532 #clock-cells = <0>; 533 clock-frequency = <24000000>; 534 clock-output-names = "xin24m"; 535 }; 536 537 xin32k: xin32k { 538 compatible = "fixed-clock"; 539 #clock-cells = <0>; 540 clock-frequency = <32768>; 541 clock-output-names = "xin32k"; 542 }; 543 544 scmi_shmem: scmi-shmem@10f000 { 545 compatible = "arm,scmi-shmem"; 546 reg = <0x0 0x0010f000 0x0 0x100>; 547 }; 548 549 pmu: power-management@ff000000 { 550 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 551 reg = <0x0 0xff000000 0x0 0x1000>; 552 553 power: power-controller { 554 compatible = "rockchip,px30-power-controller"; 555 #power-domain-cells = <1>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 559 /* These power domains are grouped by VD_LOGIC */ 560 power-domain@PX30_PD_USB { 561 reg = <PX30_PD_USB>; 562 clocks = <&cru HCLK_HOST>, 563 <&cru HCLK_OTG>, 564 <&cru SCLK_OTG_ADP>; 565 pm_qos = <&qos_usb_host>, <&qos_usb_otg>; 566 }; 567 power-domain@PX30_PD_SDCARD { 568 reg = <PX30_PD_SDCARD>; 569 clocks = <&cru HCLK_SDMMC>, 570 <&cru SCLK_SDMMC>; 571 pm_qos = <&qos_sdmmc>; 572 }; 573 power-domain@PX30_PD_GMAC { 574 reg = <PX30_PD_GMAC>; 575 clocks = <&cru ACLK_GMAC>, 576 <&cru PCLK_GMAC>, 577 <&cru SCLK_MAC_REF>, 578 <&cru SCLK_GMAC_RX_TX>; 579 pm_qos = <&qos_gmac>; 580 }; 581 power-domain@PX30_PD_MMC_NAND { 582 reg = <PX30_PD_MMC_NAND>; 583 clocks = <&cru HCLK_NANDC>, 584 <&cru HCLK_EMMC>, 585 <&cru HCLK_SDIO>, 586 <&cru HCLK_SFC>, 587 <&cru SCLK_EMMC>, 588 <&cru SCLK_NANDC>, 589 <&cru SCLK_SDIO>, 590 <&cru SCLK_SFC>; 591 pm_qos = <&qos_emmc>, <&qos_nand>, 592 <&qos_sdio>, <&qos_sfc>; 593 }; 594 power-domain@PX30_PD_VPU { 595 reg = <PX30_PD_VPU>; 596 clocks = <&cru ACLK_VPU>, 597 <&cru HCLK_VPU>, 598 <&cru SCLK_CORE_VPU>; 599 pm_qos = <&qos_vpu>, <&qos_vpu_r128>; 600 }; 601 power-domain@PX30_PD_VO { 602 reg = <PX30_PD_VO>; 603 clocks = <&cru ACLK_RGA>, 604 <&cru ACLK_VOPB>, 605 <&cru ACLK_VOPL>, 606 <&cru DCLK_VOPB>, 607 <&cru DCLK_VOPL>, 608 <&cru HCLK_RGA>, 609 <&cru HCLK_VOPB>, 610 <&cru HCLK_VOPL>, 611 <&cru PCLK_MIPI_DSI>, 612 <&cru SCLK_RGA_CORE>, 613 <&cru SCLK_VOPB_PWM>; 614 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 615 <&qos_vop_m0>, <&qos_vop_m1>; 616 }; 617 power-domain@PX30_PD_VI { 618 reg = <PX30_PD_VI>; 619 clocks = <&cru ACLK_CIF>, 620 <&cru ACLK_ISP>, 621 <&cru HCLK_CIF>, 622 <&cru HCLK_ISP>, 623 <&cru SCLK_ISP>; 624 pm_qos = <&qos_isp_128>, <&qos_isp_rd>, 625 <&qos_isp_wr>, <&qos_isp_m1>, 626 <&qos_vip>; 627 }; 628 power-domain@PX30_PD_GPU { 629 reg = <PX30_PD_GPU>; 630 clocks = <&cru SCLK_GPU>; 631 pm_qos = <&qos_gpu>; 632 }; 633 }; 634 }; 635 636 pmugrf: syscon@ff010000 { 637 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 638 reg = <0x0 0xff010000 0x0 0x1000>; 639 #address-cells = <1>; 640 #size-cells = <1>; 641 642 pmu_io_domains: io-domains { 643 compatible = "rockchip,px30-pmu-io-voltage-domain"; 644 status = "disabled"; 645 }; 646 647 reboot-mode { 648 compatible = "syscon-reboot-mode"; 649 offset = <0x200>; 650 mode-bootloader = <BOOT_BL_DOWNLOAD>; 651 mode-fastboot = <BOOT_FASTBOOT>; 652 mode-loader = <BOOT_BL_DOWNLOAD>; 653 mode-normal = <BOOT_NORMAL>; 654 mode-recovery = <BOOT_RECOVERY>; 655 }; 656 657 pmu_pvtm: pmu-pvtm { 658 compatible = "rockchip,px30-pmu-pvtm"; 659 #address-cells = <1>; 660 #size-cells = <0>; 661 status = "okay"; 662 663 pvtm@1 { 664 reg = <1>; 665 clocks = <&pmucru SCLK_PVTM_PMU>; 666 clock-names = "clk"; 667 }; 668 }; 669 }; 670 671 uart0: serial@ff030000 { 672 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 673 reg = <0x0 0xff030000 0x0 0x100>; 674 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; 676 clock-names = "baudclk", "apb_pclk"; 677 dmas = <&dmac 0>, <&dmac 1>; 678 /*You can add it to enable dma*/ 679 /*dma-names = "tx", "rx";*/ 680 reg-shift = <2>; 681 reg-io-width = <4>; 682 pinctrl-names = "default"; 683 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 684 status = "disabled"; 685 }; 686 687 i2s0_8ch: i2s@ff060000 { 688 compatible = "rockchip,px30-i2s-tdm"; 689 reg = <0x0 0xff060000 0x0 0x1000>; 690 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 691 clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>; 692 clock-names = "mclk_tx", "mclk_rx", "hclk"; 693 dmas = <&dmac 16>, <&dmac 17>; 694 dma-names = "tx", "rx"; 695 resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>; 696 reset-names = "tx-m", "rx-m"; 697 rockchip,cru = <&cru>; 698 rockchip,grf = <&grf>; 699 pinctrl-names = "default"; 700 pinctrl-0 = <&i2s0_8ch_sclktx 701 &i2s0_8ch_sclkrx 702 &i2s0_8ch_lrcktx 703 &i2s0_8ch_lrckrx 704 &i2s0_8ch_sdi0 705 &i2s0_8ch_sdi1 706 &i2s0_8ch_sdi2 707 &i2s0_8ch_sdi3 708 &i2s0_8ch_sdo0 709 &i2s0_8ch_sdo1 710 &i2s0_8ch_sdo2 711 &i2s0_8ch_sdo3>; 712 status = "disabled"; 713 }; 714 715 i2s1_2ch: i2s@ff070000 { 716 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 717 reg = <0x0 0xff070000 0x0 0x1000>; 718 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 720 clock-names = "i2s_clk", "i2s_hclk"; 721 dmas = <&dmac 18>, <&dmac 19>; 722 dma-names = "tx", "rx"; 723 pinctrl-names = "default"; 724 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck 725 &i2s1_2ch_sdi &i2s1_2ch_sdo>; 726 #sound-dai-cells = <0>; 727 status = "disabled"; 728 }; 729 730 i2s2_2ch: i2s@ff080000 { 731 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 732 reg = <0x0 0xff080000 0x0 0x1000>; 733 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 734 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 735 clock-names = "i2s_clk", "i2s_hclk"; 736 dmas = <&dmac 20>, <&dmac 21>; 737 dma-names = "tx", "rx"; 738 pinctrl-names = "default"; 739 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck 740 &i2s2_2ch_sdi &i2s2_2ch_sdo>; 741 #sound-dai-cells = <0>; 742 status = "disabled"; 743 }; 744 745 crypto: crypto@ff0b0000 { 746 compatible = "rockchip,px30-crypto"; 747 reg = <0x0 0xff0b0000 0x0 0x400>, <0x0 0xff0b0480 0x0 0x3B80>; 748 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&cru ACLK_CRYPTO >, <&cru HCLK_CRYPTO >, 750 <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>; 751 clock-names = "aclk", "hclk", "sclk", "apb_pclk"; 752 resets = <&cru SRST_CRYPTO>; 753 reset-names = "crypto-rst"; 754 status = "disabled"; 755 }; 756 757 rng: rng@ff0b0000 { 758 compatible = "rockchip,cryptov2-rng"; 759 reg = <0x0 0xff0b0400 0x0 0x80>; 760 clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>, 761 <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>; 762 clock-names = "clk_crypto", "clk_crypto_apk", 763 "aclk_crypto", "hclk_crypto"; 764 assigned-clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>, 765 <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>; 766 assigned-clock-rates = <150000000>, <150000000>, 767 <200000000>, <200000000>; 768 resets = <&cru SRST_CRYPTO>; 769 reset-names = "reset"; 770 status = "disabled"; 771 }; 772 773 gic: interrupt-controller@ff131000 { 774 compatible = "arm,gic-400"; 775 #interrupt-cells = <3>; 776 #address-cells = <0>; 777 interrupt-controller; 778 reg = <0x0 0xff131000 0 0x1000>, 779 <0x0 0xff132000 0 0x2000>, 780 <0x0 0xff134000 0 0x2000>, 781 <0x0 0xff136000 0 0x2000>; 782 interrupts = <GIC_PPI 9 783 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 784 }; 785 786 grf: syscon@ff140000 { 787 compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 788 reg = <0x0 0xff140000 0x0 0x1000>; 789 #address-cells = <1>; 790 #size-cells = <1>; 791 792 io_domains: io-domains { 793 compatible = "rockchip,px30-io-voltage-domain"; 794 status = "disabled"; 795 }; 796 797 lvds: lvds { 798 compatible = "rockchip,px30-lvds"; 799 phys = <&video_phy>; 800 phy-names = "phy"; 801 status = "disabled"; 802 803 ports { 804 #address-cells = <1>; 805 #size-cells = <0>; 806 807 port@0 { 808 reg = <0>; 809 #address-cells = <1>; 810 #size-cells = <0>; 811 812 lvds_vopb_in: endpoint@0 { 813 reg = <0>; 814 remote-endpoint = <&vopb_out_lvds>; 815 }; 816 817 lvds_vopl_in: endpoint@1 { 818 reg = <1>; 819 remote-endpoint = <&vopl_out_lvds>; 820 }; 821 }; 822 }; 823 }; 824 825 rgb: rgb { 826 compatible = "rockchip,px30-rgb"; 827 pinctrl-names = "default", "sleep"; 828 pinctrl-0 = <&lcdc_m0_rgb_pins>; 829 pinctrl-1 = <&lcdc_m0_sleep_pins>; 830 status = "disabled"; 831 832 ports { 833 #address-cells = <1>; 834 #size-cells = <0>; 835 836 port@0 { 837 reg = <0>; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 841 rgb_in_vopb: endpoint@0 { 842 reg = <0>; 843 remote-endpoint = <&vopb_out_rgb>; 844 }; 845 846 rgb_in_vopl: endpoint@1 { 847 reg = <1>; 848 remote-endpoint = <&vopl_out_rgb>; 849 }; 850 }; 851 }; 852 }; 853 }; 854 855 core_grf: syscon@ff148000 { 856 compatible = "syscon", "simple-mfd"; 857 reg = <0x0 0xff148000 0x0 0x1000>; 858 #address-cells = <1>; 859 #size-cells = <1>; 860 861 pvtm: pvtm { 862 compatible = "rockchip,px30-pvtm"; 863 #address-cells = <1>; 864 #size-cells = <0>; 865 status = "okay"; 866 867 pvtm@0 { 868 reg = <0>; 869 clocks = <&cru SCLK_PVTM>; 870 clock-names = "clk"; 871 }; 872 }; 873 }; 874 875 uart1: serial@ff158000 { 876 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 877 reg = <0x0 0xff158000 0x0 0x100>; 878 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 879 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 880 clock-names = "baudclk", "apb_pclk"; 881 dmas = <&dmac 2>, <&dmac 3>; 882 /*You can add it to enable dma*/ 883 /*dma-names = "tx", "rx";*/ 884 reg-shift = <2>; 885 reg-io-width = <4>; 886 pinctrl-names = "default"; 887 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 888 status = "disabled"; 889 }; 890 891 uart2: serial@ff160000 { 892 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 893 reg = <0x0 0xff160000 0x0 0x100>; 894 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 895 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 896 clock-names = "baudclk", "apb_pclk"; 897 dmas = <&dmac 4>, <&dmac 5>; 898 /*You can add it to enable dma*/ 899 /*dma-names = "tx", "rx";*/ 900 reg-shift = <2>; 901 reg-io-width = <4>; 902 pinctrl-names = "default"; 903 pinctrl-0 = <&uart2m0_xfer>; 904 status = "disabled"; 905 }; 906 907 uart3: serial@ff168000 { 908 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 909 reg = <0x0 0xff168000 0x0 0x100>; 910 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 912 clock-names = "baudclk", "apb_pclk"; 913 dmas = <&dmac 6>, <&dmac 7>; 914 /*You can add it to enable dma*/ 915 /*dma-names = "tx", "rx";*/ 916 reg-shift = <2>; 917 reg-io-width = <4>; 918 pinctrl-names = "default"; 919 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 920 status = "disabled"; 921 }; 922 923 uart4: serial@ff170000 { 924 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 925 reg = <0x0 0xff170000 0x0 0x100>; 926 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 927 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 928 clock-names = "baudclk", "apb_pclk"; 929 dmas = <&dmac 8>, <&dmac 9>; 930 /*You can add it to enable dma*/ 931 /*dma-names = "tx", "rx";*/ 932 reg-shift = <2>; 933 reg-io-width = <4>; 934 pinctrl-names = "default"; 935 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 936 status = "disabled"; 937 }; 938 939 uart5: serial@ff178000 { 940 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 941 reg = <0x0 0xff178000 0x0 0x100>; 942 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 943 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 944 clock-names = "baudclk", "apb_pclk"; 945 dmas = <&dmac 10>, <&dmac 11>; 946 /*You can add it to enable dma*/ 947 /*dma-names = "tx", "rx";*/ 948 reg-shift = <2>; 949 reg-io-width = <4>; 950 pinctrl-names = "default"; 951 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 952 status = "disabled"; 953 }; 954 955 i2c0: i2c@ff180000 { 956 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 957 reg = <0x0 0xff180000 0x0 0x1000>; 958 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 959 clock-names = "i2c", "pclk"; 960 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 961 pinctrl-names = "default"; 962 pinctrl-0 = <&i2c0_xfer>; 963 #address-cells = <1>; 964 #size-cells = <0>; 965 status = "disabled"; 966 }; 967 968 i2c1: i2c@ff190000 { 969 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 970 reg = <0x0 0xff190000 0x0 0x1000>; 971 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 972 clock-names = "i2c", "pclk"; 973 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 974 pinctrl-names = "default"; 975 pinctrl-0 = <&i2c1_xfer>; 976 #address-cells = <1>; 977 #size-cells = <0>; 978 status = "disabled"; 979 }; 980 981 i2c2: i2c@ff1a0000 { 982 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 983 reg = <0x0 0xff1a0000 0x0 0x1000>; 984 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 985 clock-names = "i2c", "pclk"; 986 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 987 pinctrl-names = "default"; 988 pinctrl-0 = <&i2c2_xfer>; 989 #address-cells = <1>; 990 #size-cells = <0>; 991 status = "disabled"; 992 }; 993 994 i2c3: i2c@ff1b0000 { 995 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 996 reg = <0x0 0xff1b0000 0x0 0x1000>; 997 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 998 clock-names = "i2c", "pclk"; 999 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1000 pinctrl-names = "default"; 1001 pinctrl-0 = <&i2c3_xfer>; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 status = "disabled"; 1005 }; 1006 1007 spi0: spi@ff1d0000 { 1008 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 1009 reg = <0x0 0xff1d0000 0x0 0x1000>; 1010 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 1012 clock-names = "spiclk", "apb_pclk"; 1013 dmas = <&dmac 12>, <&dmac 13>; 1014 dma-names = "tx", "rx"; 1015 pinctrl-names = "default"; 1016 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 1017 #address-cells = <1>; 1018 #size-cells = <0>; 1019 status = "disabled"; 1020 }; 1021 1022 spi1: spi@ff1d8000 { 1023 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 1024 reg = <0x0 0xff1d8000 0x0 0x1000>; 1025 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1026 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 1027 clock-names = "spiclk", "apb_pclk"; 1028 dmas = <&dmac 14>, <&dmac 15>; 1029 dma-names = "tx", "rx"; 1030 pinctrl-names = "default"; 1031 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 status = "disabled"; 1035 }; 1036 1037 wdt: watchdog@ff1e0000 { 1038 compatible = "snps,dw-wdt"; 1039 reg = <0x0 0xff1e0000 0x0 0x100>; 1040 clocks = <&cru PCLK_WDT_NS>; 1041 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1042 status = "disabled"; 1043 }; 1044 1045 pwm0: pwm@ff200000 { 1046 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 1047 reg = <0x0 0xff200000 0x0 0x10>; 1048 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 1049 clock-names = "pwm", "pclk"; 1050 pinctrl-names = "active"; 1051 pinctrl-0 = <&pwm0_pin>; 1052 #pwm-cells = <3>; 1053 status = "disabled"; 1054 }; 1055 1056 pwm1: pwm@ff200010 { 1057 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 1058 reg = <0x0 0xff200010 0x0 0x10>; 1059 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 1060 clock-names = "pwm", "pclk"; 1061 pinctrl-names = "active"; 1062 pinctrl-0 = <&pwm1_pin>; 1063 #pwm-cells = <3>; 1064 status = "disabled"; 1065 }; 1066 1067 pwm2: pwm@ff200020 { 1068 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 1069 reg = <0x0 0xff200020 0x0 0x10>; 1070 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 1071 clock-names = "pwm", "pclk"; 1072 pinctrl-names = "active"; 1073 pinctrl-0 = <&pwm2_pin>; 1074 #pwm-cells = <3>; 1075 status = "disabled"; 1076 }; 1077 1078 pwm3: pwm@ff200030 { 1079 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 1080 reg = <0x0 0xff200030 0x0 0x10>; 1081 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 1082 clock-names = "pwm", "pclk"; 1083 pinctrl-names = "active"; 1084 pinctrl-0 = <&pwm3_pin>; 1085 #pwm-cells = <3>; 1086 status = "disabled"; 1087 }; 1088 1089 pwm4: pwm@ff208000 { 1090 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 1091 reg = <0x0 0xff208000 0x0 0x10>; 1092 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 1093 clock-names = "pwm", "pclk"; 1094 pinctrl-names = "active"; 1095 pinctrl-0 = <&pwm4_pin>; 1096 #pwm-cells = <3>; 1097 status = "disabled"; 1098 }; 1099 1100 pwm5: pwm@ff208010 { 1101 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 1102 reg = <0x0 0xff208010 0x0 0x10>; 1103 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 1104 clock-names = "pwm", "pclk"; 1105 pinctrl-names = "active"; 1106 pinctrl-0 = <&pwm5_pin>; 1107 #pwm-cells = <3>; 1108 status = "disabled"; 1109 }; 1110 1111 pwm6: pwm@ff208020 { 1112 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 1113 reg = <0x0 0xff208020 0x0 0x10>; 1114 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 1115 clock-names = "pwm", "pclk"; 1116 pinctrl-names = "active"; 1117 pinctrl-0 = <&pwm6_pin>; 1118 #pwm-cells = <3>; 1119 status = "disabled"; 1120 }; 1121 1122 pwm7: pwm@ff208030 { 1123 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 1124 reg = <0x0 0xff208030 0x0 0x10>; 1125 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 1126 clock-names = "pwm", "pclk"; 1127 pinctrl-names = "active"; 1128 pinctrl-0 = <&pwm7_pin>; 1129 #pwm-cells = <3>; 1130 status = "disabled"; 1131 }; 1132 1133 rktimer: timer@ff210000 { 1134 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer"; 1135 reg = <0x0 0xff210000 0x0 0x1000>; 1136 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1137 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 1138 clock-names = "pclk", "timer"; 1139 }; 1140 1141 amba: bus { 1142 compatible = "simple-bus"; 1143 #address-cells = <2>; 1144 #size-cells = <2>; 1145 ranges; 1146 1147 dmac: dmac@ff240000 { 1148 compatible = "arm,pl330", "arm,primecell"; 1149 reg = <0x0 0xff240000 0x0 0x4000>; 1150 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1152 arm,pl330-periph-burst; 1153 clocks = <&cru ACLK_DMAC>; 1154 clock-names = "apb_pclk"; 1155 #dma-cells = <1>; 1156 }; 1157 }; 1158 1159 tsadc: tsadc@ff280000 { 1160 compatible = "rockchip,px30-tsadc"; 1161 reg = <0x0 0xff280000 0x0 0x100>; 1162 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1163 assigned-clocks = <&cru SCLK_TSADC>; 1164 assigned-clock-rates = <50000>; 1165 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 1166 clock-names = "tsadc", "apb_pclk"; 1167 resets = <&cru SRST_TSADC>; 1168 reset-names = "tsadc-apb"; 1169 rockchip,grf = <&grf>; 1170 rockchip,hw-tshut-temp = <120000>; 1171 pinctrl-names = "init", "default", "sleep"; 1172 pinctrl-0 = <&tsadc_otp_pin>; 1173 pinctrl-1 = <&tsadc_otp_out>; 1174 pinctrl-2 = <&tsadc_otp_pin>; 1175 #thermal-sensor-cells = <1>; 1176 status = "disabled"; 1177 }; 1178 1179 saradc: saradc@ff288000 { 1180 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 1181 reg = <0x0 0xff288000 0x0 0x100>; 1182 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1183 #io-channel-cells = <1>; 1184 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 1185 clock-names = "saradc", "apb_pclk"; 1186 resets = <&cru SRST_SARADC_P>; 1187 reset-names = "saradc-apb"; 1188 status = "disabled"; 1189 }; 1190 1191 otp: nvmem@ff290000 { 1192 compatible = "rockchip,px30-otp"; 1193 reg = <0x0 0xff290000 0x0 0x4000>; 1194 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, 1195 <&cru PCLK_OTP_PHY>; 1196 clock-names = "otp", "apb_pclk", "phy"; 1197 resets = <&cru SRST_OTP_PHY>; 1198 reset-names = "phy"; 1199 #address-cells = <1>; 1200 #size-cells = <1>; 1201 1202 /* Data cells */ 1203 cpu_id: id@7 { 1204 reg = <0x07 0x10>; 1205 }; 1206 cpu_leakage: cpu-leakage@17 { 1207 reg = <0x17 0x1>; 1208 }; 1209 performance: performance@1e { 1210 reg = <0x1e 0x1>; 1211 bits = <4 3>; 1212 }; 1213 }; 1214 1215 cru: clock-controller@ff2b0000 { 1216 compatible = "rockchip,px30-cru"; 1217 reg = <0x0 0xff2b0000 0x0 0x1000>; 1218 rockchip,grf = <&grf>; 1219 #clock-cells = <1>; 1220 #reset-cells = <1>; 1221 1222 assigned-clocks = <&cru PLL_NPLL>; 1223 assigned-clock-rates = <1188000000>; 1224 }; 1225 1226 pmucru: clock-controller@ff2bc000 { 1227 compatible = "rockchip,px30-pmucru"; 1228 reg = <0x0 0xff2bc000 0x0 0x1000>; 1229 rockchip,grf = <&grf>; 1230 #clock-cells = <1>; 1231 #reset-cells = <1>; 1232 1233 assigned-clocks = 1234 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 1235 <&pmucru SCLK_WIFI_PMU>, <&cru ARMCLK>, 1236 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 1237 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, 1238 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; 1239 assigned-clock-rates = 1240 <1200000000>, <100000000>, 1241 <26000000>, <600000000>, 1242 <200000000>, <200000000>, 1243 <150000000>, <150000000>, 1244 <100000000>, <200000000>; 1245 }; 1246 1247 usb2phy_grf: syscon@ff2c0000 { 1248 compatible = "rockchip,px30-usb2phy-grf", "syscon", 1249 "simple-mfd"; 1250 reg = <0x0 0xff2c0000 0x0 0x10000>; 1251 #address-cells = <1>; 1252 #size-cells = <1>; 1253 1254 u2phy: usb2-phy@100 { 1255 compatible = "rockchip,px30-usb2phy"; 1256 reg = <0x100 0x20>; 1257 clocks = <&pmucru SCLK_USBPHY_REF>; 1258 clock-names = "phyclk"; 1259 #clock-cells = <0>; 1260 assigned-clocks = <&cru USB480M>, <&cru SCLK_UART1_SRC>; 1261 assigned-clock-parents = <&u2phy>, <&cru USB480M>; 1262 clock-output-names = "usb480m_phy"; 1263 status = "disabled"; 1264 1265 u2phy_host: host-port { 1266 #phy-cells = <0>; 1267 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 1268 interrupt-names = "linestate"; 1269 status = "disabled"; 1270 }; 1271 1272 u2phy_otg: otg-port { 1273 #phy-cells = <0>; 1274 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1277 interrupt-names = "otg-bvalid", "otg-id", 1278 "linestate"; 1279 status = "disabled"; 1280 }; 1281 }; 1282 }; 1283 1284 video_phy: dsi_dphy: phy@ff2e0000 { 1285 compatible = "rockchip,px30-dsi-dphy", "rockchip,px30-video-phy"; 1286 reg = <0x0 0xff2e0000 0x0 0x10000>, 1287 <0x0 0xff450000 0x0 0x10000>; 1288 reg-names = "phy", "host"; 1289 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, 1290 <&cru PCLK_MIPIDSIPHY>, <&cru PCLK_MIPI_DSI>; 1291 clock-names = "ref", "pclk", "pclk_host"; 1292 resets = <&cru SRST_MIPIDSIPHY_P>; 1293 reset-names = "apb"; 1294 #phy-cells = <0>; 1295 power-domains = <&power PX30_PD_VO>; 1296 status = "disabled"; 1297 }; 1298 1299 mipi_dphy_rx0: mipi-dphy-rx0@ff2f0000 { 1300 compatible = "rockchip,rk3326-mipi-dphy"; 1301 reg = <0x0 0xff2f0000 0x0 0x4000>; 1302 clocks = <&cru PCLK_MIPICSIPHY>; 1303 clock-names = "dphy-ref"; 1304 power-domains = <&power PX30_PD_VI>; 1305 rockchip,grf = <&grf>; 1306 status = "disabled"; 1307 }; 1308 1309 usb20_otg: usb@ff300000 { 1310 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 1311 "snps,dwc2"; 1312 reg = <0x0 0xff300000 0x0 0x40000>; 1313 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1314 clocks = <&cru HCLK_OTG>; 1315 clock-names = "otg"; 1316 dr_mode = "otg"; 1317 g-np-tx-fifo-size = <16>; 1318 g-rx-fifo-size = <280>; 1319 g-tx-fifo-size = <256 128 128 64 32 16>; 1320 phys = <&u2phy_otg>; 1321 phy-names = "usb2-phy"; 1322 power-domains = <&power PX30_PD_USB>; 1323 status = "disabled"; 1324 }; 1325 1326 usb_host0_ehci: usb@ff340000 { 1327 compatible = "generic-ehci"; 1328 reg = <0x0 0xff340000 0x0 0x10000>; 1329 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1330 clocks = <&cru HCLK_HOST>, <&u2phy>; 1331 clock-names = "usbhost", "utmi"; 1332 phys = <&u2phy_host>; 1333 phy-names = "usb"; 1334 power-domains = <&power PX30_PD_USB>; 1335 status = "disabled"; 1336 }; 1337 1338 usb_host0_ohci: usb@ff350000 { 1339 compatible = "generic-ohci"; 1340 reg = <0x0 0xff350000 0x0 0x10000>; 1341 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1342 clocks = <&cru HCLK_HOST>, <&u2phy>; 1343 clock-names = "usbhost", "utmi"; 1344 phys = <&u2phy_host>; 1345 phy-names = "usb"; 1346 power-domains = <&power PX30_PD_USB>; 1347 status = "disabled"; 1348 }; 1349 1350 gmac: ethernet@ff360000 { 1351 compatible = "rockchip,px30-gmac"; 1352 reg = <0x0 0xff360000 0x0 0x10000>; 1353 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1354 interrupt-names = "macirq"; 1355 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 1356 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 1357 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 1358 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 1359 clock-names = "stmmaceth", "mac_clk_rx", 1360 "mac_clk_tx", "clk_mac_ref", 1361 "clk_mac_refout", "aclk_mac", 1362 "pclk_mac", "clk_mac_speed"; 1363 rockchip,grf = <&grf>; 1364 phy-mode = "rmii"; 1365 pinctrl-names = "default"; 1366 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 1367 power-domains = <&power PX30_PD_GMAC>; 1368 resets = <&cru SRST_GMAC_A>; 1369 reset-names = "stmmaceth"; 1370 status = "disabled"; 1371 }; 1372 1373 sdmmc: dwmmc@ff370000 { 1374 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 1375 reg = <0x0 0xff370000 0x0 0x4000>; 1376 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1377 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 1378 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1379 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1380 bus-width = <4>; 1381 fifo-depth = <0x100>; 1382 max-frequency = <150000000>; 1383 pinctrl-names = "default"; 1384 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 1385 power-domains = <&power PX30_PD_SDCARD>; 1386 status = "disabled"; 1387 }; 1388 1389 sdio: dwmmc@ff380000 { 1390 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 1391 reg = <0x0 0xff380000 0x0 0x4000>; 1392 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1393 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 1394 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1395 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1396 bus-width = <4>; 1397 fifo-depth = <0x100>; 1398 max-frequency = <150000000>; 1399 pinctrl-names = "default"; 1400 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 1401 power-domains = <&power PX30_PD_MMC_NAND>; 1402 status = "disabled"; 1403 }; 1404 1405 emmc: dwmmc@ff390000 { 1406 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 1407 reg = <0x0 0xff390000 0x0 0x4000>; 1408 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1409 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 1410 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 1411 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1412 bus-width = <8>; 1413 fifo-depth = <0x100>; 1414 max-frequency = <150000000>; 1415 pinctrl-names = "default"; 1416 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 1417 power-domains = <&power PX30_PD_MMC_NAND>; 1418 status = "disabled"; 1419 }; 1420 1421 sfc: spi@ff3a0000 { 1422 compatible = "rockchip,sfc"; 1423 reg = <0x0 0xff3a0000 0x0 0x4000>; 1424 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1425 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1426 clock-names = "clk_sfc", "hclk_sfc"; 1427 assigned-clocks = <&cru SCLK_SFC>; 1428 assigned-clock-rates = <100000000>; 1429 status = "disabled"; 1430 }; 1431 1432 nandc0: nandc@ff3b0000 { 1433 compatible = "rockchip,rk-nandc"; 1434 reg = <0x0 0xff3b0000 0x0 0x4000>; 1435 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1436 nandc_id = <0>; 1437 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 1438 clock-names = "clk_nandc", "hclk_nandc"; 1439 assigned-clocks = <&cru SCLK_NANDC>; 1440 assigned-clock-parents = <&cru SCLK_NANDC_DIV50>; 1441 power-domains = <&power PX30_PD_MMC_NAND>; 1442 status = "disabled"; 1443 }; 1444 1445 gpu: gpu@ff400000 { 1446 compatible = "rockchip,px30-mali", "arm,mali-bifrost"; 1447 reg = <0x0 0xff400000 0x0 0x4000>; 1448 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1451 interrupt-names = "GPU", "MMU", "JOB"; 1452 clocks = <&cru SCLK_GPU>; 1453 #cooling-cells = <2>; 1454 power-domains = <&power PX30_PD_GPU>; 1455 operating-points-v2 = <&gpu_opp_table>; 1456 upthreshold = <40>; 1457 downdifferential = <10>; 1458 status = "disabled"; 1459 power_model { 1460 compatible = "arm,mali-simple-power-model"; 1461 static-coefficient = <411000>; 1462 dynamic-coefficient = <733>; 1463 ts = <32000 4700 (-80) 2>; 1464 thermal-zone = "gpu-thermal"; 1465 }; 1466 }; 1467 1468 gpu_opp_table: gpu-opp-table { 1469 compatible = "operating-points-v2"; 1470 1471 rockchip,thermal-zone = "soc-thermal"; 1472 rockchip,temp-hysteresis = <5000>; 1473 rockchip,low-temp = <0>; 1474 rockchip,low-temp-min-volt = <1000000>; 1475 rockchip,low-temp-adjust-volt = < 1476 /* MHz MHz uV */ 1477 0 480 50000 1478 >; 1479 1480 rockchip,max-volt = <1175000>; 1481 rockchip,evb-irdrop = <25000>; 1482 1483 rockchip,pvtm-voltage-sel = < 1484 0 50000 0 1485 50001 54000 1 1486 54001 60000 2 1487 60001 99999 3 1488 >; 1489 rockchip,pvtm-ch = <0 0>; 1490 1491 opp-200000000 { 1492 opp-hz = /bits/ 64 <200000000>; 1493 opp-microvolt = <950000>; 1494 opp-microvolt-L0 = <950000>; 1495 opp-microvolt-L1 = <950000>; 1496 opp-microvolt-L2 = <950000>; 1497 opp-microvolt-L3 = <950000>; 1498 }; 1499 opp-300000000 { 1500 opp-hz = /bits/ 64 <300000000>; 1501 opp-microvolt = <975000>; 1502 opp-microvolt-L0 = <975000>; 1503 opp-microvolt-L1 = <950000>; 1504 opp-microvolt-L2 = <950000>; 1505 opp-microvolt-L3 = <950000>; 1506 }; 1507 opp-400000000 { 1508 opp-hz = /bits/ 64 <400000000>; 1509 opp-microvolt = <1050000>; 1510 opp-microvolt-L0 = <1050000>; 1511 opp-microvolt-L1 = <1025000>; 1512 opp-microvolt-L2 = <975000>; 1513 opp-microvolt-L3 = <950000>; 1514 }; 1515 opp-480000000 { 1516 opp-hz = /bits/ 64 <480000000>; 1517 opp-microvolt = <1125000>; 1518 opp-microvolt-L0 = <1125000>; 1519 opp-microvolt-L1 = <1100000>; 1520 opp-microvolt-L2 = <1050000>; 1521 opp-microvolt-L3 = <1000000>; 1522 }; 1523 }; 1524 1525 px30s_gpu_opp_table: px30s-gpu-opp-table { 1526 compatible = "operating-points-v2"; 1527 1528 rockchip,pvtm-voltage-sel = < 1529 0 69850 0 1530 69851 73800 1 1531 73801 77750 2 1532 77751 81700 3 1533 81701 99999 4 1534 >; 1535 rockchip,pvtm-ch = <0 0>; 1536 1537 opp-200000000 { 1538 opp-hz = /bits/ 64 <200000000>; 1539 opp-microvolt = <950000>; 1540 }; 1541 opp-300000000 { 1542 opp-hz = /bits/ 64 <300000000>; 1543 opp-microvolt = <950000>; 1544 }; 1545 opp-400000000 { 1546 opp-hz = /bits/ 64 <400000000>; 1547 opp-microvolt = <950000>; 1548 }; 1549 opp-520000000 { 1550 opp-hz = /bits/ 64 <520000000>; 1551 opp-microvolt = <1000000>; 1552 opp-microvolt-L0 = <1000000>; 1553 opp-microvolt-L1 = <975000>; 1554 opp-microvolt-L2 = <950000>; 1555 opp-microvolt-L3 = <950000>; 1556 opp-microvolt-L4 = <950000>; 1557 }; 1558 }; 1559 1560 mpp_srv: mpp-srv { 1561 compatible = "rockchip,mpp-service"; 1562 rockchip,taskqueue-count = <1>; 1563 rockchip,resetgroup-count = <1>; 1564 rockchip,grf = <&grf>; 1565 rockchip,grf-offset = <0x0410>; 1566 rockchip,grf-values = <0x80008000>, <0x80000000>, <0x80000000>; 1567 rockchip,grf-names = "grf_rkvdec", "grf_vdpu2", "grf_vepu2"; 1568 status = "disabled"; 1569 }; 1570 1571 vdpu: vdpu@ff442400 { 1572 compatible = "rockchip,vpu-decoder-px30"; 1573 reg = <0x0 0xff442400 0x0 0x400>; 1574 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1575 interrupt-names = "irq_dec"; 1576 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1577 clock-names = "aclk_vcodec", "hclk_vcodec"; 1578 resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>; 1579 reset-names = "shared_video_a", "shared_video_h"; 1580 iommus = <&vpu_mmu>; 1581 power-domains = <&power PX30_PD_VPU>; 1582 rockchip,srv = <&mpp_srv>; 1583 rockchip,taskqueue-node = <0>; 1584 rockchip,resetgroup-node = <0>; 1585 status = "disabled"; 1586 }; 1587 1588 vpu_mmu: iommu@ff442800 { 1589 compatible = "rockchip,iommu"; 1590 reg = <0x0 0xff442800 0x0 0x100>; 1591 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1592 interrupt-names = "vpu_mmu"; 1593 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1594 clock-names = "aclk", "iface"; 1595 power-domains = <&power PX30_PD_VPU>; 1596 rockchip,shootdown-entire; 1597 #iommu-cells = <0>; 1598 status = "disabled"; 1599 }; 1600 1601 vepu: vepu@ff442000 { 1602 compatible = "rockchip,vpu-encoder-px30"; 1603 reg = <0x0 0xff442000 0x0 0x400>; 1604 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1605 interrupt-names = "irq_enc"; 1606 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1607 clock-names = "aclk_vcodec", "hclk_vcodec"; 1608 resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>; 1609 reset-names = "shared_video_a", "shared_video_h"; 1610 iommus = <&vpu_mmu>; 1611 power-domains = <&power PX30_PD_VPU>; 1612 rockchip,srv = <&mpp_srv>; 1613 rockchip,taskqueue-node = <0>; 1614 rockchip,resetgroup-node = <0>; 1615 status = "disabled"; 1616 }; 1617 1618 hevc: hevc@ff440000 { 1619 compatible = "rockchip,hevc-decoder-px30"; 1620 reg = <0x0 0xff440000 0x0 0x400>; 1621 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1622 interrupt-names = "irq_dec"; 1623 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>, <&cru SCLK_CORE_VPU>; 1624 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 1625 resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>, 1626 <&cru SRST_VPU_NIU_A>, <&cru SRST_VPU_NIU_H>, 1627 <&cru SRST_VPU_CORE>; 1628 reset-names = "shared_video_a", "shared_video_h", 1629 "niu_a", "niu_h", 1630 "video_core"; 1631 iommus = <&hevc_mmu>; 1632 rockchip,srv = <&mpp_srv>; 1633 rockchip,taskqueue-node = <0>; 1634 rockchip,resetgroup-node = <0>; 1635 power-domains = <&power PX30_PD_VPU>; 1636 status = "disabled"; 1637 }; 1638 1639 hevc_mmu: iommu@ff440440 { 1640 compatible = "rockchip,iommu"; 1641 reg = <0x0 0xff440440 0x0 0x40>, <0x0 0xff440480 0x0 0x40>; 1642 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1643 interrupt-names = "hevc_mmu"; 1644 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1645 clock-names = "aclk", "iface"; 1646 power-domains = <&power PX30_PD_VPU>; 1647 rockchip,shootdown-entire; 1648 #iommu-cells = <0>; 1649 status = "disabled"; 1650 }; 1651 1652 dsi: dsi@ff450000 { 1653 compatible = "rockchip,px30-mipi-dsi"; 1654 reg = <0x0 0xff450000 0x0 0x10000>; 1655 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1656 clocks = <&cru PCLK_MIPI_DSI>; 1657 clock-names = "pclk"; 1658 phys = <&video_phy>; 1659 phy-names = "dphy"; 1660 power-domains = <&power PX30_PD_VO>; 1661 resets = <&cru SRST_MIPIDSI_HOST_P>; 1662 reset-names = "apb"; 1663 rockchip,grf = <&grf>; 1664 #address-cells = <1>; 1665 #size-cells = <0>; 1666 status = "disabled"; 1667 1668 ports { 1669 #address-cells = <1>; 1670 #size-cells = <0>; 1671 1672 port@0 { 1673 reg = <0>; 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 1677 dsi_in_vopb: endpoint@0 { 1678 reg = <0>; 1679 remote-endpoint = <&vopb_out_dsi>; 1680 }; 1681 1682 dsi_in_vopl: endpoint@1 { 1683 reg = <1>; 1684 remote-endpoint = <&vopl_out_dsi>; 1685 }; 1686 }; 1687 }; 1688 }; 1689 1690 vopb: vop@ff460000 { 1691 compatible = "rockchip,px30-vop-big"; 1692 reg = <0x0 0xff460000 0x0 0x1fc>, <0x0 0xff460a00 0x0 0x400>; 1693 rockchip,grf = <&grf>; 1694 reg-names = "regs", "gamma_lut"; 1695 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1696 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 1697 <&cru HCLK_VOPB>; 1698 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1699 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>; 1700 reset-names = "axi", "ahb", "dclk"; 1701 iommus = <&vopb_mmu>; 1702 power-domains = <&power PX30_PD_VO>; 1703 status = "disabled"; 1704 1705 vopb_out: port { 1706 #address-cells = <1>; 1707 #size-cells = <0>; 1708 1709 vopb_out_dsi: endpoint@0 { 1710 reg = <0>; 1711 remote-endpoint = <&dsi_in_vopb>; 1712 }; 1713 1714 vopb_out_lvds: endpoint@1 { 1715 reg = <1>; 1716 remote-endpoint = <&lvds_vopb_in>; 1717 }; 1718 1719 vopb_out_rgb: endpoint@2 { 1720 reg = <2>; 1721 remote-endpoint = <&rgb_in_vopb>; 1722 }; 1723 }; 1724 }; 1725 1726 vopb_mmu: iommu@ff460f00 { 1727 compatible = "rockchip,iommu"; 1728 reg = <0x0 0xff460f00 0x0 0x100>; 1729 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1730 interrupt-names = "vopb_mmu"; 1731 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 1732 clock-names = "aclk", "iface"; 1733 power-domains = <&power PX30_PD_VO>; 1734 #iommu-cells = <0>; 1735 rockchip,disable-device-link-resume; 1736 status = "disabled"; 1737 }; 1738 1739 vopl: vop@ff470000 { 1740 compatible = "rockchip,px30-vop-lit"; 1741 reg = <0x0 0xff470000 0x0 0x1fc>, <0x0 0xff470a00 0x0 0x400>; 1742 rockchip,grf = <&grf>; 1743 reg-names = "regs", "gamma_lut"; 1744 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1745 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 1746 <&cru HCLK_VOPL>; 1747 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1748 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>; 1749 reset-names = "axi", "ahb", "dclk"; 1750 iommus = <&vopl_mmu>; 1751 power-domains = <&power PX30_PD_VO>; 1752 status = "disabled"; 1753 1754 vopl_out: port { 1755 #address-cells = <1>; 1756 #size-cells = <0>; 1757 1758 vopl_out_dsi: endpoint@0 { 1759 reg = <0>; 1760 remote-endpoint = <&dsi_in_vopl>; 1761 }; 1762 1763 vopl_out_lvds: endpoint@1 { 1764 reg = <1>; 1765 remote-endpoint = <&lvds_vopl_in>; 1766 }; 1767 1768 vopl_out_rgb: endpoint@2 { 1769 reg = <2>; 1770 remote-endpoint = <&rgb_in_vopl>; 1771 }; 1772 }; 1773 }; 1774 1775 vopl_mmu: iommu@ff470f00 { 1776 compatible = "rockchip,iommu"; 1777 reg = <0x0 0xff470f00 0x0 0x100>; 1778 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1779 interrupt-names = "vopl_mmu"; 1780 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 1781 clock-names = "aclk", "iface"; 1782 power-domains = <&power PX30_PD_VO>; 1783 #iommu-cells = <0>; 1784 rockchip,disable-device-link-resume; 1785 status = "disabled"; 1786 }; 1787 1788 rk_rga: rk_rga@ff480000 { 1789 compatible = "rockchip,rga2"; 1790 //dev_mode = <1>; 1791 reg = <0x0 0xff480000 0x0 0x1000>; 1792 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1793 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 1794 clock-names = "aclk_rga", "hclk_rga", "clk_rga"; 1795 power-domains = <&power PX30_PD_VO>; 1796 status = "disabled"; 1797 }; 1798 1799 cif: cif@ff490000 { 1800 compatible = "rockchip,cif"; 1801 reg = <0x0 0xff490000 0x0 0x200>; 1802 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1803 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>, <&cru SCLK_CIF_OUT>; 1804 clock-names = "aclk_cif0", "hclk_cif0", "pclk_cif", "cif0_out"; 1805 resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>; 1806 reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_pclkin"; 1807 power-domains = <&power PX30_PD_VI>; 1808 pinctrl-names = "cif_pin_all"; 1809 pinctrl-0 = <&dvp_d2d9_m0>; 1810 iommus = <&vip_mmu>; 1811 status = "disabled"; 1812 }; 1813 1814 cif_new: cif-new@ff490000 { 1815 compatible = "rockchip,px30-cif"; 1816 reg = <0x0 0xff490000 0x0 0x200>; 1817 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1818 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>, <&cru SCLK_CIF_OUT>; 1819 clock-names = "aclk_cif", "hclk_cif", "pclk_cif", "cif_out"; 1820 resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>; 1821 reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_pclkin"; 1822 power-domains = <&power PX30_PD_VI>; 1823 iommus = <&vip_mmu>; 1824 status = "disabled"; 1825 }; 1826 1827 vip_mmu: iommu@ff490800{ 1828 compatible = "rockchip,iommu"; 1829 reg = <0x0 0xff490800 0x0 0x100>; 1830 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1831 interrupt-names = "vip_mmu"; 1832 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>; 1833 clock-names = "aclk", "iface"; 1834 power-domains = <&power PX30_PD_VI>; 1835 rk_iommu,disable_reset_quirk; 1836 #iommu-cells = <0>; 1837 status = "disabled"; 1838 }; 1839 1840 rk_isp: rk_isp@ff4a0000 { 1841 compatible = "rockchip,px30-isp", "rockchip,isp"; 1842 reg = <0x0 0xff4a0000 0x0 0x8000>; 1843 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1844 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>, <&cru SCLK_ISP>, 1845 <&cru PCLK_ISP>, <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, <&cru PCLK_MIPICSIPHY>; 1846 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", 1847 "pclkin_isp", "clk_cif_pll", "clk_cif_out", "pclk_dphyrx"; 1848 resets = <&cru SRST_ISP>, <&cru SRST_MIPICSIPHY_P>; 1849 reset-names = "rst_isp", "rst_mipicsiphy"; 1850 power-domains = <&power PX30_PD_VI>; 1851 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit"; 1852 pinctrl-0 = <&cif_clkout_m0>; 1853 pinctrl-1 = <&dvp_d2d9_m0>; 1854 pinctrl-2 = <&dvp_d2d9_m0 &dvp_d10d11_m0>; 1855 pinctrl-3 = <&dvp_d0d1_m0 &dvp_d2d9_m0 &dvp_d10d11_m0>; 1856 rockchip,isp,mipiphy = <1>; 1857 rockchip,isp,csiphy,reg = <0xff2f0000 0x4000>; 1858 rockchip,grf = <&grf>; 1859 rockchip,cru = <&cru>; 1860 rockchip,isp,iommu-enable = <1>; 1861 iommus = <&isp_mmu>; 1862 status = "disabled"; 1863 }; 1864 1865 rkisp1: rkisp1@ff4a0000 { 1866 compatible = "rockchip,rk3326-rkisp1"; 1867 reg = <0x0 0xff4a0000 0x0 0x8000>; 1868 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1871 interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; 1872 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, 1873 <&cru SCLK_ISP>, <&cru PCLK_ISP>; 1874 clock-names = "aclk_isp", "hclk_isp", 1875 "clk_isp", "pclk_isp"; 1876 devfreq = <&dmc>; 1877 power-domains = <&power PX30_PD_VI>; 1878 iommus = <&isp_mmu>; 1879 rockchip,grf = <&grf>; 1880 status = "disabled"; 1881 }; 1882 1883 isp_mmu: iommu@ff4a8000 { 1884 compatible = "rockchip,iommu"; 1885 reg = <0x0 0xff4a8000 0x0 0x100>; 1886 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1887 interrupt-names = "isp_mmu"; 1888 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1889 clock-names = "aclk", "iface"; 1890 power-domains = <&power PX30_PD_VI>; 1891 rk_iommu,disable_reset_quirk; 1892 #iommu-cells = <0>; 1893 status = "disabled"; 1894 }; 1895 1896 qos_gmac: qos@ff518000 { 1897 compatible = "syscon"; 1898 reg = <0x0 0xff518000 0x0 0x20>; 1899 }; 1900 1901 qos_gpu: qos@ff520000 { 1902 compatible = "syscon"; 1903 reg = <0x0 0xff520000 0x0 0x20>; 1904 }; 1905 1906 qos_sdmmc: qos@ff52c000 { 1907 compatible = "syscon"; 1908 reg = <0x0 0xff52c000 0x0 0x20>; 1909 }; 1910 1911 qos_emmc: qos@ff538000 { 1912 compatible = "syscon"; 1913 reg = <0x0 0xff538000 0x0 0x20>; 1914 }; 1915 1916 qos_nand: qos@ff538080 { 1917 compatible = "syscon"; 1918 reg = <0x0 0xff538080 0x0 0x20>; 1919 }; 1920 1921 qos_sdio: qos@ff538100 { 1922 compatible = "syscon"; 1923 reg = <0x0 0xff538100 0x0 0x20>; 1924 }; 1925 1926 qos_sfc: qos@ff538180 { 1927 compatible = "syscon"; 1928 reg = <0x0 0xff538180 0x0 0x20>; 1929 }; 1930 1931 qos_usb_host: qos@ff540000 { 1932 compatible = "syscon"; 1933 reg = <0x0 0xff540000 0x0 0x20>; 1934 }; 1935 1936 qos_usb_otg: qos@ff540080 { 1937 compatible = "syscon"; 1938 reg = <0x0 0xff540080 0x0 0x20>; 1939 }; 1940 1941 qos_isp_128: qos@ff548000 { 1942 compatible = "syscon"; 1943 reg = <0x0 0xff548000 0x0 0x20>; 1944 }; 1945 1946 qos_isp_rd: qos@ff548080 { 1947 compatible = "syscon"; 1948 reg = <0x0 0xff548080 0x0 0x20>; 1949 }; 1950 1951 qos_isp_wr: qos@ff548100 { 1952 compatible = "syscon"; 1953 reg = <0x0 0xff548100 0x0 0x20>; 1954 }; 1955 1956 qos_isp_m1: qos@ff548180 { 1957 compatible = "syscon"; 1958 reg = <0x0 0xff548180 0x0 0x20>; 1959 }; 1960 1961 qos_vip: qos@ff548200 { 1962 compatible = "syscon"; 1963 reg = <0x0 0xff548200 0x0 0x20>; 1964 }; 1965 1966 qos_rga_rd: qos@ff550000 { 1967 compatible = "syscon"; 1968 reg = <0x0 0xff550000 0x0 0x20>; 1969 }; 1970 1971 qos_rga_wr: qos@ff550080 { 1972 compatible = "syscon"; 1973 reg = <0x0 0xff550080 0x0 0x20>; 1974 }; 1975 1976 qos_vop_m0: qos@ff550100 { 1977 compatible = "syscon"; 1978 reg = <0x0 0xff550100 0x0 0x20>; 1979 }; 1980 1981 qos_vop_m1: qos@ff550180 { 1982 compatible = "syscon"; 1983 reg = <0x0 0xff550180 0x0 0x20>; 1984 }; 1985 1986 qos_vpu: qos@ff558000 { 1987 compatible = "syscon"; 1988 reg = <0x0 0xff558000 0x0 0x20>; 1989 }; 1990 1991 qos_vpu_r128: qos@ff558080 { 1992 compatible = "syscon"; 1993 reg = <0x0 0xff558080 0x0 0x20>; 1994 }; 1995 1996 dfi: dfi@ff610000 { 1997 reg = <0x00 0xff610000 0x00 0x400>; 1998 compatible = "rockchip,px30-dfi"; 1999 rockchip,pmugrf = <&pmugrf>; 2000 status = "disabled"; 2001 }; 2002 2003 dmc: dmc { 2004 compatible = "rockchip,px30-dmc"; 2005 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2006 interrupt-names = "complete_irq"; 2007 devfreq-events = <&dfi>; 2008 clocks = <&cru SCLK_DDRCLK>; 2009 clock-names = "dmc_clk"; 2010 operating-points-v2 = <&dmc_opp_table>; 2011 ddr_timing = <&ddr_timing>; 2012 upthreshold = <40>; 2013 downdifferential = <20>; 2014 system-status-freq = < 2015 /*system status freq(KHz)*/ 2016 SYS_STATUS_NORMAL 528000 2017 SYS_STATUS_REBOOT 450000 2018 SYS_STATUS_SUSPEND 194000 2019 SYS_STATUS_VIDEO_1080P 450000 2020 SYS_STATUS_BOOST 528000 2021 SYS_STATUS_ISP 666000 2022 SYS_STATUS_PERFORMANCE 1056000 2023 >; 2024 auto-min-freq = <328000>; 2025 auto-freq-en = <1>; 2026 #cooling-cells = <2>; 2027 status = "disabled"; 2028 2029 ddr_power_model: ddr_power_model { 2030 compatible = "ddr_power_model"; 2031 dynamic-power-coefficient = <120>; 2032 static-power-coefficient = <200>; 2033 ts = <32000 4700 (-80) 2>; 2034 thermal-zone = "soc-thermal"; 2035 }; 2036 }; 2037 2038 dmc_fsp: dmc-fsp { 2039 compatible = "rockchip,px30s-dmc-fsp"; 2040 2041 debug_print_level = <0>; 2042 phy_de_skew_en = <1>; 2043 ddr3_params = <&ddr3_params>; 2044 ddr4_params = <&ddr4_params>; 2045 lpddr2_params = <&lpddr2_params>; 2046 lpddr3_params = <&lpddr3_params>; 2047 lpddr4_params = <&lpddr4_params>; 2048 ddr_timing = <&ddr_timing>; 2049 status = "okay"; 2050 }; 2051 2052 dmc_opp_table: dmc-opp-table { 2053 compatible = "operating-points-v2"; 2054 2055 rockchip,max-volt = <1150000>; 2056 rockchip,evb-irdrop = <25000>; 2057 2058 rockchip,pvtm-voltage-sel = < 2059 0 50000 0 2060 50001 54000 1 2061 54001 60000 2 2062 60001 99999 3 2063 >; 2064 rockchip,pvtm-ch = <0 0>; 2065 2066 opp-194000000 { 2067 opp-hz = /bits/ 64 <194000000>; 2068 opp-microvolt = <950000>; 2069 opp-microvolt-L0 = <950000>; 2070 opp-microvolt-L1 = <950000>; 2071 opp-microvolt-L2 = <950000>; 2072 opp-microvolt-L3 = <950000>; 2073 }; 2074 opp-328000000 { 2075 opp-hz = /bits/ 64 <328000000>; 2076 opp-microvolt = <950000>; 2077 opp-microvolt-L0 = <950000>; 2078 opp-microvolt-L1 = <950000>; 2079 opp-microvolt-L2 = <950000>; 2080 opp-microvolt-L3 = <950000>; 2081 }; 2082 opp-450000000 { 2083 opp-hz = /bits/ 64 <450000000>; 2084 opp-microvolt = <950000>; 2085 opp-microvolt-L0 = <950000>; 2086 opp-microvolt-L1 = <950000>; 2087 opp-microvolt-L2 = <950000>; 2088 opp-microvolt-L3 = <950000>; 2089 }; 2090 opp-528000000 { 2091 opp-hz = /bits/ 64 <528000000>; 2092 opp-microvolt = <975000>; 2093 opp-microvolt-L0 = <975000>; 2094 opp-microvolt-L1 = <975000>; 2095 opp-microvolt-L2 = <950000>; 2096 opp-microvolt-L3 = <950000>; 2097 }; 2098 opp-666000000 { 2099 opp-hz = /bits/ 64 <666000000>; 2100 opp-microvolt = <1050000>; 2101 opp-microvolt-L0 = <1050000>; 2102 opp-microvolt-L1 = <1000000>; 2103 opp-microvolt-L2 = <975000>; 2104 opp-microvolt-L3 = <950000>; 2105 }; 2106 opp-786000000 { 2107 opp-hz = /bits/ 64 <786000000>; 2108 opp-microvolt = <1100000>; 2109 opp-microvolt-L0 = <1100000>; 2110 opp-microvolt-L1 = <1050000>; 2111 opp-microvolt-L2 = <1025000>; 2112 opp-microvolt-L3 = <1000000>; 2113 status = "disabled"; 2114 }; 2115 }; 2116 2117 px30s_dmc_opp_table: px30s-dmc-opp-table { 2118 compatible = "operating-points-v2"; 2119 2120 opp-194000000 { 2121 opp-hz = /bits/ 64 <194000000>; 2122 opp-microvolt = <950000>; 2123 }; 2124 opp-328000000 { 2125 opp-hz = /bits/ 64 <328000000>; 2126 opp-microvolt = <950000>; 2127 }; 2128 opp-528000000 { 2129 opp-hz = /bits/ 64 <528000000>; 2130 opp-microvolt = <950000>; 2131 status = "disabled"; 2132 }; 2133 opp-666000000 { 2134 opp-hz = /bits/ 64 <666000000>; 2135 opp-microvolt = <950000>; 2136 }; 2137 opp-786000000 { 2138 opp-hz = /bits/ 64 <786000000>; 2139 opp-microvolt = <950000>; 2140 status = "disabled"; 2141 }; 2142 opp-924000000 { 2143 opp-hz = /bits/ 64 <924000000>; 2144 opp-microvolt = <950000>; 2145 status = "disabled"; 2146 }; 2147 /* 1056M only for LP4 */ 2148 opp-1056000000 { 2149 opp-hz = /bits/ 64 <1056000000>; 2150 opp-microvolt = <950000>; 2151 status = "disabled"; 2152 }; 2153 }; 2154 2155 dmcdbg: dmcdbg { 2156 compatible = "rockchip,px30-dmcdbg"; 2157 status = "okay"; 2158 }; 2159 2160 rockchip_system_monitor: rockchip-system-monitor { 2161 compatible = "rockchip,system-monitor"; 2162 2163 rockchip,thermal-zone = "soc-thermal"; 2164 rockchip,polling-delay = <200>; /* milliseconds */ 2165 }; 2166 2167 pinctrl: pinctrl { 2168 compatible = "rockchip,px30-pinctrl"; 2169 rockchip,grf = <&grf>; 2170 rockchip,pmu = <&pmugrf>; 2171 #address-cells = <2>; 2172 #size-cells = <2>; 2173 ranges; 2174 2175 gpio0: gpio0@ff040000 { 2176 compatible = "rockchip,gpio-bank"; 2177 reg = <0x0 0xff040000 0x0 0x100>; 2178 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 2179 clocks = <&pmucru PCLK_GPIO0_PMU>; 2180 gpio-controller; 2181 #gpio-cells = <2>; 2182 2183 interrupt-controller; 2184 #interrupt-cells = <2>; 2185 }; 2186 2187 gpio1: gpio1@ff250000 { 2188 compatible = "rockchip,gpio-bank"; 2189 reg = <0x0 0xff250000 0x0 0x100>; 2190 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 2191 clocks = <&cru PCLK_GPIO1>; 2192 gpio-controller; 2193 #gpio-cells = <2>; 2194 2195 interrupt-controller; 2196 #interrupt-cells = <2>; 2197 }; 2198 2199 gpio2: gpio2@ff260000 { 2200 compatible = "rockchip,gpio-bank"; 2201 reg = <0x0 0xff260000 0x0 0x100>; 2202 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2203 clocks = <&cru PCLK_GPIO2>; 2204 gpio-controller; 2205 #gpio-cells = <2>; 2206 2207 interrupt-controller; 2208 #interrupt-cells = <2>; 2209 }; 2210 2211 gpio3: gpio3@ff270000 { 2212 compatible = "rockchip,gpio-bank"; 2213 reg = <0x0 0xff270000 0x0 0x100>; 2214 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2215 clocks = <&cru PCLK_GPIO3>; 2216 gpio-controller; 2217 #gpio-cells = <2>; 2218 2219 interrupt-controller; 2220 #interrupt-cells = <2>; 2221 }; 2222 2223 pcfg_pull_up: pcfg-pull-up { 2224 bias-pull-up; 2225 }; 2226 2227 pcfg_pull_down: pcfg-pull-down { 2228 bias-pull-down; 2229 }; 2230 2231 pcfg_pull_none: pcfg-pull-none { 2232 bias-disable; 2233 }; 2234 2235 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 2236 bias-disable; 2237 drive-strength = <2>; 2238 }; 2239 2240 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 2241 bias-pull-up; 2242 drive-strength = <2>; 2243 }; 2244 2245 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 2246 bias-pull-up; 2247 drive-strength = <4>; 2248 }; 2249 2250 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 2251 bias-disable; 2252 drive-strength = <4>; 2253 }; 2254 2255 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 2256 bias-pull-down; 2257 drive-strength = <4>; 2258 }; 2259 2260 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 2261 bias-disable; 2262 drive-strength = <8>; 2263 }; 2264 2265 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 2266 bias-pull-up; 2267 drive-strength = <8>; 2268 }; 2269 2270 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 2271 bias-disable; 2272 drive-strength = <12>; 2273 }; 2274 2275 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 2276 bias-pull-up; 2277 drive-strength = <12>; 2278 }; 2279 2280 pcfg_pull_none_smt: pcfg-pull-none-smt { 2281 bias-disable; 2282 input-schmitt-enable; 2283 }; 2284 2285 pcfg_output_high: pcfg-output-high { 2286 output-high; 2287 }; 2288 2289 pcfg_output_low: pcfg-output-low { 2290 output-low; 2291 }; 2292 2293 pcfg_input_high: pcfg-input-high { 2294 bias-pull-up; 2295 input-enable; 2296 }; 2297 2298 pcfg_input: pcfg-input { 2299 input-enable; 2300 }; 2301 2302 i2c0 { 2303 i2c0_xfer: i2c0-xfer { 2304 rockchip,pins = 2305 <0 RK_PB0 1 &pcfg_pull_none_smt>, 2306 <0 RK_PB1 1 &pcfg_pull_none_smt>; 2307 }; 2308 }; 2309 2310 i2c1 { 2311 i2c1_xfer: i2c1-xfer { 2312 rockchip,pins = 2313 <0 RK_PC2 1 &pcfg_pull_none_smt>, 2314 <0 RK_PC3 1 &pcfg_pull_none_smt>; 2315 }; 2316 }; 2317 2318 i2c2 { 2319 i2c2_xfer: i2c2-xfer { 2320 rockchip,pins = 2321 <2 RK_PB7 2 &pcfg_pull_none_smt>, 2322 <2 RK_PC0 2 &pcfg_pull_none_smt>; 2323 }; 2324 }; 2325 2326 i2c3 { 2327 i2c3_xfer: i2c3-xfer { 2328 rockchip,pins = 2329 <1 RK_PB4 4 &pcfg_pull_none_smt>, 2330 <1 RK_PB5 4 &pcfg_pull_none_smt>; 2331 }; 2332 }; 2333 2334 tsadc { 2335 tsadc_otp_gpio: tsadc_otp_pin: tsadc-otp-pin { 2336 rockchip,pins = 2337 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2338 }; 2339 2340 tsadc_otp_out: tsadc-otp-out { 2341 rockchip,pins = 2342 <0 RK_PA6 1 &pcfg_pull_none>; 2343 }; 2344 }; 2345 2346 uart0 { 2347 uart0_xfer: uart0-xfer { 2348 rockchip,pins = 2349 <0 RK_PB2 1 &pcfg_pull_up>, 2350 <0 RK_PB3 1 &pcfg_pull_up>; 2351 }; 2352 2353 uart0_cts: uart0-cts { 2354 rockchip,pins = 2355 <0 RK_PB4 1 &pcfg_pull_none>; 2356 }; 2357 2358 uart0_rts: uart0-rts { 2359 rockchip,pins = 2360 <0 RK_PB5 1 &pcfg_pull_none>; 2361 }; 2362 }; 2363 2364 uart1 { 2365 uart1_xfer: uart1-xfer { 2366 rockchip,pins = 2367 <1 RK_PC1 1 &pcfg_pull_up>, 2368 <1 RK_PC0 1 &pcfg_pull_up>; 2369 }; 2370 2371 uart1_cts: uart1-cts { 2372 rockchip,pins = 2373 <1 RK_PC2 1 &pcfg_pull_none>; 2374 }; 2375 2376 uart1_rts: uart1-rts { 2377 rockchip,pins = 2378 <1 RK_PC3 1 &pcfg_pull_none>; 2379 }; 2380 2381 uart1_rts_gpio: uart1-rts-gpio { 2382 rockchip,pins = 2383 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 2384 }; 2385 }; 2386 2387 uart2-m0 { 2388 uart2m0_xfer: uart2m0-xfer { 2389 rockchip,pins = 2390 <1 RK_PD2 2 &pcfg_pull_up>, 2391 <1 RK_PD3 2 &pcfg_pull_up>; 2392 }; 2393 }; 2394 2395 uart2-m1 { 2396 uart2m1_xfer: uart2m1-xfer { 2397 rockchip,pins = 2398 <2 RK_PB4 2 &pcfg_pull_up>, 2399 <2 RK_PB6 2 &pcfg_pull_up>; 2400 }; 2401 }; 2402 2403 uart3-m0 { 2404 uart3m0_xfer: uart3m0-xfer { 2405 rockchip,pins = 2406 <0 RK_PC0 2 &pcfg_pull_up>, 2407 <0 RK_PC1 2 &pcfg_pull_up>; 2408 }; 2409 2410 uart3m0_cts: uart3m0-cts { 2411 rockchip,pins = 2412 <0 RK_PC2 2 &pcfg_pull_none>; 2413 }; 2414 2415 uart3m0_rts: uart3m0-rts { 2416 rockchip,pins = 2417 <0 RK_PC3 2 &pcfg_pull_none>; 2418 }; 2419 }; 2420 2421 uart3-m1 { 2422 uart3m1_xfer: uart3m1-xfer { 2423 rockchip,pins = 2424 <1 RK_PB6 2 &pcfg_pull_up>, 2425 <1 RK_PB7 2 &pcfg_pull_up>; 2426 }; 2427 2428 uart3m1_cts: uart3m1-cts { 2429 rockchip,pins = 2430 <1 RK_PB4 2 &pcfg_pull_none>; 2431 }; 2432 2433 uart3m1_rts: uart3m1-rts { 2434 rockchip,pins = 2435 <1 RK_PB5 2 &pcfg_pull_none>; 2436 }; 2437 }; 2438 2439 uart4 { 2440 uart4_xfer: uart4-xfer { 2441 rockchip,pins = 2442 <1 RK_PD4 2 &pcfg_pull_up>, 2443 <1 RK_PD5 2 &pcfg_pull_up>; 2444 }; 2445 2446 uart4_cts: uart4-cts { 2447 rockchip,pins = 2448 <1 RK_PD6 2 &pcfg_pull_none>; 2449 }; 2450 2451 uart4_rts: uart4-rts { 2452 rockchip,pins = 2453 <1 RK_PD7 2 &pcfg_pull_none>; 2454 }; 2455 }; 2456 2457 uart5 { 2458 uart5_xfer: uart5-xfer { 2459 rockchip,pins = 2460 <3 RK_PA2 4 &pcfg_pull_up>, 2461 <3 RK_PA1 4 &pcfg_pull_up>; 2462 }; 2463 2464 uart5_cts: uart5-cts { 2465 rockchip,pins = 2466 <3 RK_PA3 4 &pcfg_pull_none>; 2467 }; 2468 2469 uart5_rts: uart5-rts { 2470 rockchip,pins = 2471 <3 RK_PA5 4 &pcfg_pull_none>; 2472 }; 2473 }; 2474 2475 spi0 { 2476 spi0_clk: spi0-clk { 2477 rockchip,pins = 2478 <1 RK_PB7 3 &pcfg_pull_up_4ma>; 2479 }; 2480 2481 spi0_csn: spi0-csn { 2482 rockchip,pins = 2483 <1 RK_PB6 3 &pcfg_pull_up_4ma>; 2484 }; 2485 2486 spi0_miso: spi0-miso { 2487 rockchip,pins = 2488 <1 RK_PB5 3 &pcfg_pull_up_4ma>; 2489 }; 2490 2491 spi0_mosi: spi0-mosi { 2492 rockchip,pins = 2493 <1 RK_PB4 3 &pcfg_pull_up_4ma>; 2494 }; 2495 2496 spi0_clk_hs: spi0-clk-hs { 2497 rockchip,pins = 2498 <1 RK_PB7 3 &pcfg_pull_up_8ma>; 2499 }; 2500 2501 spi0_miso_hs: spi0-miso-hs { 2502 rockchip,pins = 2503 <1 RK_PB5 3 &pcfg_pull_up_8ma>; 2504 }; 2505 2506 spi0_mosi_hs: spi0-mosi-hs { 2507 rockchip,pins = 2508 <1 RK_PB4 3 &pcfg_pull_up_8ma>; 2509 }; 2510 }; 2511 2512 spi1 { 2513 spi1_clk: spi1-clk { 2514 rockchip,pins = 2515 <3 RK_PB7 4 &pcfg_pull_up_4ma>; 2516 }; 2517 2518 spi1_csn0: spi1-csn0 { 2519 rockchip,pins = 2520 <3 RK_PB1 4 &pcfg_pull_up_4ma>; 2521 }; 2522 2523 spi1_csn1: spi1-csn1 { 2524 rockchip,pins = 2525 <3 RK_PB2 2 &pcfg_pull_up_4ma>; 2526 }; 2527 2528 spi1_miso: spi1-miso { 2529 rockchip,pins = 2530 <3 RK_PB6 4 &pcfg_pull_up_4ma>; 2531 }; 2532 2533 spi1_mosi: spi1-mosi { 2534 rockchip,pins = 2535 <3 RK_PB4 4 &pcfg_pull_up_4ma>; 2536 }; 2537 2538 spi1_clk_hs: spi1-clk-hs { 2539 rockchip,pins = 2540 <3 RK_PB7 4 &pcfg_pull_up_8ma>; 2541 }; 2542 2543 spi1_miso_hs: spi1-miso-hs { 2544 rockchip,pins = 2545 <3 RK_PB6 4 &pcfg_pull_up_8ma>; 2546 }; 2547 2548 spi1_mosi_hs: spi1-mosi-hs { 2549 rockchip,pins = 2550 <3 RK_PB4 4 &pcfg_pull_up_8ma>; 2551 }; 2552 }; 2553 2554 pdm { 2555 pdm_clk0m0: pdm-clk0m0 { 2556 rockchip,pins = 2557 <3 RK_PC6 2 &pcfg_pull_none>; 2558 }; 2559 2560 pdm_clk0m1: pdm-clk0m1 { 2561 rockchip,pins = 2562 <2 RK_PC6 1 &pcfg_pull_none>; 2563 }; 2564 2565 pdm_clk1: pdm-clk1 { 2566 rockchip,pins = 2567 <3 RK_PC7 2 &pcfg_pull_none>; 2568 }; 2569 2570 pdm_sdi0m0: pdm-sdi0m0 { 2571 rockchip,pins = 2572 <3 RK_PD3 2 &pcfg_pull_none>; 2573 }; 2574 2575 pdm_sdi0m1: pdm-sdi0m1 { 2576 rockchip,pins = 2577 <2 RK_PC5 2 &pcfg_pull_none>; 2578 }; 2579 2580 pdm_sdi1: pdm-sdi1 { 2581 rockchip,pins = 2582 <3 RK_PD0 2 &pcfg_pull_none>; 2583 }; 2584 2585 pdm_sdi2: pdm-sdi2 { 2586 rockchip,pins = 2587 <3 RK_PD1 2 &pcfg_pull_none>; 2588 }; 2589 2590 pdm_sdi3: pdm-sdi3 { 2591 rockchip,pins = 2592 <3 RK_PD2 2 &pcfg_pull_none>; 2593 }; 2594 2595 pdm_clk0m0_sleep: pdm-clk0m0-sleep { 2596 rockchip,pins = 2597 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 2598 }; 2599 2600 pdm_clk0m_sleep1: pdm-clk0m1-sleep { 2601 rockchip,pins = 2602 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 2603 }; 2604 2605 pdm_clk1_sleep: pdm-clk1-sleep { 2606 rockchip,pins = 2607 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 2608 }; 2609 2610 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 2611 rockchip,pins = 2612 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 2613 }; 2614 2615 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 2616 rockchip,pins = 2617 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 2618 }; 2619 2620 pdm_sdi1_sleep: pdm-sdi1-sleep { 2621 rockchip,pins = 2622 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 2623 }; 2624 2625 pdm_sdi2_sleep: pdm-sdi2-sleep { 2626 rockchip,pins = 2627 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 2628 }; 2629 2630 pdm_sdi3_sleep: pdm-sdi3-sleep { 2631 rockchip,pins = 2632 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 2633 }; 2634 }; 2635 2636 i2s0 { 2637 i2s0_8ch_mclk: i2s0-8ch-mclk { 2638 rockchip,pins = 2639 <3 RK_PC1 2 &pcfg_pull_none_smt>; 2640 }; 2641 2642 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 2643 rockchip,pins = 2644 <3 RK_PC3 2 &pcfg_pull_none_smt>; 2645 }; 2646 2647 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 2648 rockchip,pins = 2649 <3 RK_PB4 2 &pcfg_pull_none_smt>; 2650 }; 2651 2652 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 2653 rockchip,pins = 2654 <3 RK_PC2 2 &pcfg_pull_none_smt>; 2655 }; 2656 2657 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 2658 rockchip,pins = 2659 <3 RK_PB5 2 &pcfg_pull_none_smt>; 2660 }; 2661 2662 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 2663 rockchip,pins = 2664 <3 RK_PC4 2 &pcfg_pull_none>; 2665 }; 2666 2667 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 2668 rockchip,pins = 2669 <3 RK_PC0 2 &pcfg_pull_none>; 2670 }; 2671 2672 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 2673 rockchip,pins = 2674 <3 RK_PB7 2 &pcfg_pull_none>; 2675 }; 2676 2677 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 2678 rockchip,pins = 2679 <3 RK_PB6 2 &pcfg_pull_none>; 2680 }; 2681 2682 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 2683 rockchip,pins = 2684 <3 RK_PC5 2 &pcfg_pull_none>; 2685 }; 2686 2687 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 2688 rockchip,pins = 2689 <3 RK_PB3 2 &pcfg_pull_none>; 2690 }; 2691 2692 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 2693 rockchip,pins = 2694 <3 RK_PB1 2 &pcfg_pull_none>; 2695 }; 2696 2697 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 2698 rockchip,pins = 2699 <3 RK_PB0 2 &pcfg_pull_none>; 2700 }; 2701 }; 2702 2703 i2s1 { 2704 i2s1_2ch_mclk: i2s1-2ch-mclk { 2705 rockchip,pins = 2706 <2 RK_PC3 1 &pcfg_pull_none_smt>; 2707 }; 2708 2709 i2s1_2ch_sclk: i2s1-2ch-sclk { 2710 rockchip,pins = 2711 <2 RK_PC2 1 &pcfg_pull_none_smt>; 2712 }; 2713 2714 i2s1_2ch_lrck: i2s1-2ch-lrck { 2715 rockchip,pins = 2716 <2 RK_PC1 1 &pcfg_pull_none_smt>; 2717 }; 2718 2719 i2s1_2ch_sdi: i2s1-2ch-sdi { 2720 rockchip,pins = 2721 <2 RK_PC5 1 &pcfg_pull_none>; 2722 }; 2723 2724 i2s1_2ch_sdo: i2s1-2ch-sdo { 2725 rockchip,pins = 2726 <2 RK_PC4 1 &pcfg_pull_none>; 2727 }; 2728 }; 2729 2730 i2s2 { 2731 i2s2_2ch_mclk: i2s2-2ch-mclk { 2732 rockchip,pins = 2733 <3 RK_PA1 2 &pcfg_pull_none_smt>; 2734 }; 2735 2736 i2s2_2ch_sclk: i2s2-2ch-sclk { 2737 rockchip,pins = 2738 <3 RK_PA2 2 &pcfg_pull_none_smt>; 2739 }; 2740 2741 i2s2_2ch_lrck: i2s2-2ch-lrck { 2742 rockchip,pins = 2743 <3 RK_PA3 2 &pcfg_pull_none_smt>; 2744 }; 2745 2746 i2s2_2ch_sdi: i2s2-2ch-sdi { 2747 rockchip,pins = 2748 <3 RK_PA5 2 &pcfg_pull_none>; 2749 }; 2750 2751 i2s2_2ch_sdo: i2s2-2ch-sdo { 2752 rockchip,pins = 2753 <3 RK_PA7 2 &pcfg_pull_none>; 2754 }; 2755 }; 2756 2757 sdmmc { 2758 sdmmc_clk: sdmmc-clk { 2759 rockchip,pins = 2760 <1 RK_PD6 1 &pcfg_pull_none_8ma>; 2761 }; 2762 2763 sdmmc_cmd: sdmmc-cmd { 2764 rockchip,pins = 2765 <1 RK_PD7 1 &pcfg_pull_up_8ma>; 2766 }; 2767 2768 sdmmc_det: sdmmc-det { 2769 rockchip,pins = 2770 <0 RK_PA3 1 &pcfg_pull_up_8ma>; 2771 }; 2772 2773 sdmmc_bus1: sdmmc-bus1 { 2774 rockchip,pins = 2775 <1 RK_PD2 1 &pcfg_pull_up_8ma>; 2776 }; 2777 2778 sdmmc_bus4: sdmmc-bus4 { 2779 rockchip,pins = 2780 <1 RK_PD2 1 &pcfg_pull_up_8ma>, 2781 <1 RK_PD3 1 &pcfg_pull_up_8ma>, 2782 <1 RK_PD4 1 &pcfg_pull_up_8ma>, 2783 <1 RK_PD5 1 &pcfg_pull_up_8ma>; 2784 }; 2785 }; 2786 2787 sdio { 2788 sdio_clk: sdio-clk { 2789 rockchip,pins = 2790 <1 RK_PC5 1 &pcfg_pull_none>; 2791 }; 2792 2793 sdio_cmd: sdio-cmd { 2794 rockchip,pins = 2795 <1 RK_PC4 1 &pcfg_pull_up>; 2796 }; 2797 2798 sdio_bus4: sdio-bus4 { 2799 rockchip,pins = 2800 <1 RK_PC6 1 &pcfg_pull_up>, 2801 <1 RK_PC7 1 &pcfg_pull_up>, 2802 <1 RK_PD0 1 &pcfg_pull_up>, 2803 <1 RK_PD1 1 &pcfg_pull_up>; 2804 }; 2805 }; 2806 2807 emmc { 2808 emmc_clk: emmc-clk { 2809 rockchip,pins = 2810 <1 RK_PB1 2 &pcfg_pull_none_8ma>; 2811 }; 2812 2813 emmc_cmd: emmc-cmd { 2814 rockchip,pins = 2815 <1 RK_PB2 2 &pcfg_pull_up_8ma>; 2816 }; 2817 2818 emmc_rstnout: emmc-rstnout { 2819 rockchip,pins = 2820 <1 RK_PB3 2 &pcfg_pull_none>; 2821 }; 2822 2823 emmc_bus1: emmc-bus1 { 2824 rockchip,pins = 2825 <1 RK_PA0 2 &pcfg_pull_up_8ma>; 2826 }; 2827 2828 emmc_bus4: emmc-bus4 { 2829 rockchip,pins = 2830 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 2831 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 2832 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 2833 <1 RK_PA3 2 &pcfg_pull_up_8ma>; 2834 }; 2835 2836 emmc_bus8: emmc-bus8 { 2837 rockchip,pins = 2838 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 2839 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 2840 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 2841 <1 RK_PA3 2 &pcfg_pull_up_8ma>, 2842 <1 RK_PA4 2 &pcfg_pull_up_8ma>, 2843 <1 RK_PA5 2 &pcfg_pull_up_8ma>, 2844 <1 RK_PA6 2 &pcfg_pull_up_8ma>, 2845 <1 RK_PA7 2 &pcfg_pull_up_8ma>; 2846 }; 2847 }; 2848 2849 flash { 2850 flash_cs0: flash-cs0 { 2851 rockchip,pins = 2852 <1 RK_PB0 1 &pcfg_pull_none>; 2853 }; 2854 2855 flash_rdy: flash-rdy { 2856 rockchip,pins = 2857 <1 RK_PB1 1 &pcfg_pull_none>; 2858 }; 2859 2860 flash_dqs: flash-dqs { 2861 rockchip,pins = 2862 <1 RK_PB2 1 &pcfg_pull_none>; 2863 }; 2864 2865 flash_ale: flash-ale { 2866 rockchip,pins = 2867 <1 RK_PB3 1 &pcfg_pull_none>; 2868 }; 2869 2870 flash_cle: flash-cle { 2871 rockchip,pins = 2872 <1 RK_PB4 1 &pcfg_pull_none>; 2873 }; 2874 2875 flash_wrn: flash-wrn { 2876 rockchip,pins = 2877 <1 RK_PB5 1 &pcfg_pull_none>; 2878 }; 2879 2880 flash_csl: flash-csl { 2881 rockchip,pins = 2882 <1 RK_PB6 1 &pcfg_pull_none>; 2883 }; 2884 2885 flash_rdn: flash-rdn { 2886 rockchip,pins = 2887 <1 RK_PB7 1 &pcfg_pull_none>; 2888 }; 2889 2890 flash_bus8: flash-bus8 { 2891 rockchip,pins = 2892 <1 RK_PA0 1 &pcfg_pull_up_12ma>, 2893 <1 RK_PA1 1 &pcfg_pull_up_12ma>, 2894 <1 RK_PA2 1 &pcfg_pull_up_12ma>, 2895 <1 RK_PA3 1 &pcfg_pull_up_12ma>, 2896 <1 RK_PA4 1 &pcfg_pull_up_12ma>, 2897 <1 RK_PA5 1 &pcfg_pull_up_12ma>, 2898 <1 RK_PA6 1 &pcfg_pull_up_12ma>, 2899 <1 RK_PA7 1 &pcfg_pull_up_12ma>; 2900 }; 2901 }; 2902 2903 lcdc { 2904 lcdc_m0_rgb_pins: lcdc-m0-rgb-pins { 2905 rockchip,pins = 2906 <3 RK_PA0 1 &pcfg_pull_none_8ma>, /* LCDC_DCLK */ 2907 <3 RK_PA1 1 &pcfg_pull_none_8ma>, /* LCDC_HSYNC */ 2908 <3 RK_PA2 1 &pcfg_pull_none_8ma>, /* LCDC_VSYNC */ 2909 <3 RK_PA3 1 &pcfg_pull_none_8ma>, /* LCDC_DEN */ 2910 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* LCDC_D0 */ 2911 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* LCDC_D1 */ 2912 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* LCDC_D2 */ 2913 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* LCDC_D3 */ 2914 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* LCDC_D4 */ 2915 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* LCDC_D5 */ 2916 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* LCDC_D6 */ 2917 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* LCDC_D7 */ 2918 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* LCDC_D8 */ 2919 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* LCDC_D9 */ 2920 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* LCDC_D10 */ 2921 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* LCDC_D11 */ 2922 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* LCDC_D12 */ 2923 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* LCDC_D13 */ 2924 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* LCDC_D14 */ 2925 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* LCDC_D15 */ 2926 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* LCDC_D16 */ 2927 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* LCDC_D17 */ 2928 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* LCDC_D18 */ 2929 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* LCDC_D19 */ 2930 <3 RK_PD0 1 &pcfg_pull_none_8ma>, /* LCDC_D20 */ 2931 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* LCDC_D21 */ 2932 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* LCDC_D22 */ 2933 <3 RK_PD3 1 &pcfg_pull_none_8ma>; /* LCDC_D23 */ 2934 }; 2935 2936 lcdc_m0_sleep_pins: lcdc-m0-sleep-pins { 2937 rockchip,pins = 2938 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */ 2939 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_HSYNC */ 2940 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_VSYNC */ 2941 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DEN */ 2942 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D0 */ 2943 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D1 */ 2944 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D2 */ 2945 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D3 */ 2946 <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D4 */ 2947 <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D5 */ 2948 <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D6 */ 2949 <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D7 */ 2950 <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D8 */ 2951 <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D9 */ 2952 <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */ 2953 <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */ 2954 <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */ 2955 <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */ 2956 <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */ 2957 <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */ 2958 <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */ 2959 <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */ 2960 <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */ 2961 <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */ 2962 <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */ 2963 <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */ 2964 <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */ 2965 <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_D23 */ 2966 }; 2967 }; 2968 2969 pwm0 { 2970 pwm0_pin: pwm0-pin { 2971 rockchip,pins = 2972 <0 RK_PB7 1 &pcfg_pull_none>; 2973 }; 2974 }; 2975 2976 pwm1 { 2977 pwm1_pin: pwm1-pin { 2978 rockchip,pins = 2979 <0 RK_PC0 1 &pcfg_pull_none>; 2980 }; 2981 }; 2982 2983 pwm2 { 2984 pwm2_pin: pwm2-pin { 2985 rockchip,pins = 2986 <2 RK_PB5 1 &pcfg_pull_none>; 2987 }; 2988 }; 2989 2990 pwm3 { 2991 pwm3_pin: pwm3-pin { 2992 rockchip,pins = 2993 <0 RK_PC1 1 &pcfg_pull_none>; 2994 }; 2995 }; 2996 2997 pwm4 { 2998 pwm4_pin: pwm4-pin { 2999 rockchip,pins = 3000 <3 RK_PC2 3 &pcfg_pull_none>; 3001 }; 3002 }; 3003 3004 pwm5 { 3005 pwm5_pin: pwm5-pin { 3006 rockchip,pins = 3007 <3 RK_PC3 3 &pcfg_pull_none>; 3008 }; 3009 }; 3010 3011 pwm6 { 3012 pwm6_pin: pwm6-pin { 3013 rockchip,pins = 3014 <3 RK_PC4 3 &pcfg_pull_none>; 3015 }; 3016 }; 3017 3018 pwm7 { 3019 pwm7_pin: pwm7-pin { 3020 rockchip,pins = 3021 <3 RK_PC5 3 &pcfg_pull_none>; 3022 }; 3023 }; 3024 3025 gmac { 3026 rmii_pins: rmii-pins { 3027 rockchip,pins = 3028 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */ 3029 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */ 3030 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */ 3031 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */ 3032 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */ 3033 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */ 3034 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */ 3035 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */ 3036 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */ 3037 }; 3038 3039 mac_refclk_12ma: mac-refclk-12ma { 3040 rockchip,pins = 3041 <2 RK_PB2 2 &pcfg_pull_none_12ma>; 3042 }; 3043 3044 mac_refclk: mac-refclk { 3045 rockchip,pins = 3046 <2 RK_PB2 2 &pcfg_pull_none>; 3047 }; 3048 }; 3049 3050 cif-m0 { 3051 cif_clkout_m0: cif-clkout-m0 { 3052 rockchip,pins = 3053 <2 RK_PB3 1 &pcfg_pull_none_12ma>;/* cif_clkout */ 3054 }; 3055 3056 dvp_d2d9_m0: dvp-d2d9-m0 { 3057 rockchip,pins = 3058 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */ 3059 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */ 3060 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */ 3061 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */ 3062 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */ 3063 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */ 3064 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */ 3065 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */ 3066 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */ 3067 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */ 3068 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */ 3069 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */ 3070 }; 3071 3072 dvp_d0d1_m0: dvp-d0d1-m0 { 3073 rockchip,pins = 3074 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */ 3075 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */ 3076 }; 3077 3078 dvp_d10d11_m0:d10-d11-m0 { 3079 rockchip,pins = 3080 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */ 3081 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */ 3082 }; 3083 }; 3084 3085 cif-m1 { 3086 cif_clkout_m1: cif-clkout-m1 { 3087 rockchip,pins = 3088 <3 RK_PD0 3 &pcfg_pull_none>; 3089 }; 3090 3091 dvp_d2d9_m1: dvp-d2d9-m1 { 3092 rockchip,pins = 3093 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */ 3094 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */ 3095 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */ 3096 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */ 3097 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */ 3098 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */ 3099 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */ 3100 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */ 3101 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */ 3102 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */ 3103 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */ 3104 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */ 3105 }; 3106 3107 dvp_d0d1_m1: dvp-d0d1-m1 { 3108 rockchip,pins = 3109 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */ 3110 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */ 3111 }; 3112 3113 dvp_d10d11_m1:d10-d11-m1 { 3114 rockchip,pins = 3115 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */ 3116 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */ 3117 }; 3118 }; 3119 3120 isp { 3121 isp_prelight: isp-prelight { 3122 rockchip,pins = 3123 <3 RK_PD1 4 &pcfg_pull_none>; 3124 }; 3125 }; 3126 }; 3127}; 3128#include "px30s-pinctrl.dtsi" 3129