1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2022 Fuzhou Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun#include <dt-bindings/display/media-bus-format.h>
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun/ {
9*4882a593Smuzhiyun	reserved-memory {
10*4882a593Smuzhiyun		#address-cells = <1>;
11*4882a593Smuzhiyun		#size-cells = <1>;
12*4882a593Smuzhiyun		ranges;
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun		linux,cma {
15*4882a593Smuzhiyun			compatible = "shared-dma-pool";
16*4882a593Smuzhiyun			inactive;
17*4882a593Smuzhiyun			reusable;
18*4882a593Smuzhiyun			size = <0x1000000>;
19*4882a593Smuzhiyun			linux,cma-default;
20*4882a593Smuzhiyun		};
21*4882a593Smuzhiyun	};
22*4882a593Smuzhiyun};
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun&display_subsystem {
25*4882a593Smuzhiyun	status = "okay";
26*4882a593Smuzhiyun};
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun&i2c0 {
29*4882a593Smuzhiyun	clock-frequency = <400000>;
30*4882a593Smuzhiyun	status = "okay";
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun	sii9022: sii9022@39 {
33*4882a593Smuzhiyun		compatible = "sil,sii9022";
34*4882a593Smuzhiyun		reg = <0x39>;
35*4882a593Smuzhiyun		pinctrl-names = "default";
36*4882a593Smuzhiyun		pinctrl-0 = <&sii902x_hdmi_int>;
37*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
38*4882a593Smuzhiyun		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_HIGH>;
39*4882a593Smuzhiyun		reset-gpio = <&gpio1 RK_PD1 GPIO_ACTIVE_LOW>;
40*4882a593Smuzhiyun		enable-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
41*4882a593Smuzhiyun		/*
42*4882a593Smuzhiyun		 * MEDIA_BUS_FMT_YUYV8_1X16 for bt1120
43*4882a593Smuzhiyun		 * MEDIA_BUS_FMT_UYVY8_2X8  for bt656
44*4882a593Smuzhiyun		 */
45*4882a593Smuzhiyun		bus-format = <MEDIA_BUS_FMT_YUYV8_1X16>;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun		ports {
48*4882a593Smuzhiyun			#address-cells = <1>;
49*4882a593Smuzhiyun			#size-cells = <0>;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun			port@0 {
52*4882a593Smuzhiyun				reg = <0>;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun				sii9022_in_rgb: endpoint {
55*4882a593Smuzhiyun					remote-endpoint = <&rgb_out_sii9022>;
56*4882a593Smuzhiyun				};
57*4882a593Smuzhiyun			};
58*4882a593Smuzhiyun		};
59*4882a593Smuzhiyun	};
60*4882a593Smuzhiyun};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun&pinctrl {
63*4882a593Smuzhiyun	sii902x {
64*4882a593Smuzhiyun		sii902x_hdmi_int: sii902x-hdmi-int {
65*4882a593Smuzhiyun			rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
66*4882a593Smuzhiyun		};
67*4882a593Smuzhiyun	};
68*4882a593Smuzhiyun};
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun&rgb {
71*4882a593Smuzhiyun	status = "okay";
72*4882a593Smuzhiyun	pinctrl-names = "default";
73*4882a593Smuzhiyun	/*
74*4882a593Smuzhiyun	 * <&bt1120_pins> for bt1120
75*4882a593Smuzhiyun	 * <&bt656_pins>  for bt656
76*4882a593Smuzhiyun	 */
77*4882a593Smuzhiyun	pinctrl-0 = <&bt1120_pins>;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun	ports {
80*4882a593Smuzhiyun		port@1 {
81*4882a593Smuzhiyun			reg = <1>;
82*4882a593Smuzhiyun			#address-cells = <1>;
83*4882a593Smuzhiyun			#size-cells = <0>;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun			rgb_out_sii9022: endpoint@0 {
86*4882a593Smuzhiyun				reg = <0>;
87*4882a593Smuzhiyun				remote-endpoint = <&sii9022_in_rgb>;
88*4882a593Smuzhiyun			};
89*4882a593Smuzhiyun		};
90*4882a593Smuzhiyun	};
91*4882a593Smuzhiyun};
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun&rgb_in_vop {
94*4882a593Smuzhiyun	status = "okay";
95*4882a593Smuzhiyun};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun/*
98*4882a593Smuzhiyun * The pins of sdmmc1 and lcd are multiplexed
99*4882a593Smuzhiyun */
100*4882a593Smuzhiyun&sdio {
101*4882a593Smuzhiyun	status = "disabled";
102*4882a593Smuzhiyun};
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun&sdio_pwrseq {
105*4882a593Smuzhiyun	status = "disabled";
106*4882a593Smuzhiyun};
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun&vop {
109*4882a593Smuzhiyun	status = "okay";
110*4882a593Smuzhiyun};
111