1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5 6/dts-v1/; 7 8#include "rv1103g-evb-v11.dts" 9#include <dt-bindings/display/media-bus-format.h> 10 11/ { 12 model = "Rockchip RV1103G EVB V11 Board + RK EVB BT1120&BT656 TO HDMI V10 Ext Board"; 13 compatible = "rockchip,rv1103g-evb-v11-sii902x-bt6562hdmi", "rockchip,rv1103"; 14 15 reserved-memory { 16 #address-cells = <1>; 17 #size-cells = <1>; 18 ranges; 19 20 linux,cma { 21 compatible = "shared-dma-pool"; 22 inactive; 23 reusable; 24 size = <0x1000000>; 25 linux,cma-default; 26 }; 27 }; 28}; 29 30&display_subsystem { 31 status = "okay"; 32}; 33 34&i2c4 { 35 pinctrl-names = "default"; 36 pinctrl-0 = <&i2c4m2_xfer>; 37 clock-frequency = <400000>; 38 status = "okay"; 39 40 sii9022: sii9022@39 { 41 compatible = "sil,sii9022"; 42 reg = <0x39>; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&sii902x_hdmi_int>; 45 interrupt-parent = <&gpio3>; 46 interrupts = <RK_PC6 IRQ_TYPE_LEVEL_HIGH>; 47 reset-gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; 48 enable-gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; 49 bus-format = <MEDIA_BUS_FMT_UYVY8_2X8>; 50 51 ports { 52 #address-cells = <1>; 53 #size-cells = <0>; 54 55 port@0 { 56 reg = <0>; 57 58 sii9022_in_rgb: endpoint { 59 remote-endpoint = <&rgb_out_sii9022>; 60 }; 61 }; 62 }; 63 }; 64}; 65 66&pinctrl { 67 sii902x { 68 sii902x_hdmi_int: sii902x-hdmi-int { 69 rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; 70 }; 71 }; 72}; 73 74&rgb { 75 status = "okay"; 76 pinctrl-names = "default"; 77 pinctrl-0 = <&bt656_pins>; 78 79 ports { 80 port@1 { 81 reg = <1>; 82 #address-cells = <1>; 83 #size-cells = <0>; 84 85 rgb_out_sii9022: endpoint@0 { 86 reg = <0>; 87 remote-endpoint = <&sii9022_in_rgb>; 88 }; 89 }; 90 }; 91}; 92 93&rgb_in_vop { 94 status = "okay"; 95}; 96 97/* 98 * The pins of vcc3v3_sd/vcc3v3_wifi and lcd are multiplexed 99 */ 100&vcc3v3_sd { 101 status = "disabled"; 102}; 103 104&vcc3v3_wifi { 105 status = "disabled"; 106}; 107 108&vop { 109 status = "okay"; 110}; 111