1// SPDX-License-Identifier: GPL-2.0 2// 3// Copyright 2015 Freescale Semiconductor, Inc. 4 5#include <dt-bindings/clock/imx6ul-clock.h> 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/input.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include "imx6ul-pinfunc.h" 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 /* 15 * The decompressor and also some bootloaders rely on a 16 * pre-existing /chosen node to be available to insert the 17 * command line and merge other ATAGS info. 18 */ 19 chosen {}; 20 21 aliases { 22 ethernet0 = &fec1; 23 ethernet1 = &fec2; 24 gpio0 = &gpio1; 25 gpio1 = &gpio2; 26 gpio2 = &gpio3; 27 gpio3 = &gpio4; 28 gpio4 = &gpio5; 29 i2c0 = &i2c1; 30 i2c1 = &i2c2; 31 i2c2 = &i2c3; 32 i2c3 = &i2c4; 33 mmc0 = &usdhc1; 34 mmc1 = &usdhc2; 35 serial0 = &uart1; 36 serial1 = &uart2; 37 serial2 = &uart3; 38 serial3 = &uart4; 39 serial4 = &uart5; 40 serial5 = &uart6; 41 serial6 = &uart7; 42 serial7 = &uart8; 43 sai1 = &sai1; 44 sai2 = &sai2; 45 sai3 = &sai3; 46 spi0 = &ecspi1; 47 spi1 = &ecspi2; 48 spi2 = &ecspi3; 49 spi3 = &ecspi4; 50 usbphy0 = &usbphy1; 51 usbphy1 = &usbphy2; 52 }; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 cpu0: cpu@0 { 59 compatible = "arm,cortex-a7"; 60 device_type = "cpu"; 61 reg = <0>; 62 clock-frequency = <696000000>; 63 clock-latency = <61036>; /* two CLK32 periods */ 64 #cooling-cells = <2>; 65 operating-points = 66 /* kHz uV */ 67 <696000 1275000>, 68 <528000 1175000>, 69 <396000 1025000>, 70 <198000 950000>; 71 fsl,soc-operating-points = 72 /* KHz uV */ 73 <696000 1275000>, 74 <528000 1175000>, 75 <396000 1175000>, 76 <198000 1175000>; 77 clocks = <&clks IMX6UL_CLK_ARM>, 78 <&clks IMX6UL_CLK_PLL2_BUS>, 79 <&clks IMX6UL_CLK_PLL2_PFD2>, 80 <&clks IMX6UL_CA7_SECONDARY_SEL>, 81 <&clks IMX6UL_CLK_STEP>, 82 <&clks IMX6UL_CLK_PLL1_SW>, 83 <&clks IMX6UL_CLK_PLL1_SYS>; 84 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", 85 "secondary_sel", "step", "pll1_sw", 86 "pll1_sys"; 87 arm-supply = <®_arm>; 88 soc-supply = <®_soc>; 89 nvmem-cells = <&cpu_speed_grade>; 90 nvmem-cell-names = "speed_grade"; 91 }; 92 }; 93 94 timer { 95 compatible = "arm,armv7-timer"; 96 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 97 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 98 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 99 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 100 interrupt-parent = <&intc>; 101 status = "disabled"; 102 }; 103 104 ckil: clock-cli { 105 compatible = "fixed-clock"; 106 #clock-cells = <0>; 107 clock-frequency = <32768>; 108 clock-output-names = "ckil"; 109 }; 110 111 osc: clock-osc { 112 compatible = "fixed-clock"; 113 #clock-cells = <0>; 114 clock-frequency = <24000000>; 115 clock-output-names = "osc"; 116 }; 117 118 ipp_di0: clock-di0 { 119 compatible = "fixed-clock"; 120 #clock-cells = <0>; 121 clock-frequency = <0>; 122 clock-output-names = "ipp_di0"; 123 }; 124 125 ipp_di1: clock-di1 { 126 compatible = "fixed-clock"; 127 #clock-cells = <0>; 128 clock-frequency = <0>; 129 clock-output-names = "ipp_di1"; 130 }; 131 132 pmu { 133 compatible = "arm,cortex-a7-pmu"; 134 interrupt-parent = <&gpc>; 135 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 136 }; 137 138 soc { 139 #address-cells = <1>; 140 #size-cells = <1>; 141 compatible = "simple-bus"; 142 interrupt-parent = <&gpc>; 143 ranges; 144 145 ocram: sram@900000 { 146 compatible = "mmio-sram"; 147 reg = <0x00900000 0x20000>; 148 ranges = <0 0x00900000 0x20000>; 149 #address-cells = <1>; 150 #size-cells = <1>; 151 }; 152 153 intc: interrupt-controller@a01000 { 154 compatible = "arm,gic-400", "arm,cortex-a7-gic"; 155 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 156 #interrupt-cells = <3>; 157 interrupt-controller; 158 interrupt-parent = <&intc>; 159 reg = <0x00a01000 0x1000>, 160 <0x00a02000 0x2000>, 161 <0x00a04000 0x2000>, 162 <0x00a06000 0x2000>; 163 }; 164 165 dma_apbh: dma-apbh@1804000 { 166 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; 167 reg = <0x01804000 0x2000>; 168 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, 169 <0 13 IRQ_TYPE_LEVEL_HIGH>, 170 <0 13 IRQ_TYPE_LEVEL_HIGH>, 171 <0 13 IRQ_TYPE_LEVEL_HIGH>; 172 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 173 #dma-cells = <1>; 174 dma-channels = <4>; 175 clocks = <&clks IMX6UL_CLK_APBHDMA>; 176 }; 177 178 gpmi: nand-controller@1806000 { 179 compatible = "fsl,imx6q-gpmi-nand"; 180 #address-cells = <1>; 181 #size-cells = <1>; 182 reg = <0x01806000 0x2000>, <0x01808000 0x2000>; 183 reg-names = "gpmi-nand", "bch"; 184 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; 185 interrupt-names = "bch"; 186 clocks = <&clks IMX6UL_CLK_GPMI_IO>, 187 <&clks IMX6UL_CLK_GPMI_APB>, 188 <&clks IMX6UL_CLK_GPMI_BCH>, 189 <&clks IMX6UL_CLK_GPMI_BCH_APB>, 190 <&clks IMX6UL_CLK_PER_BCH>; 191 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 192 "gpmi_bch_apb", "per1_bch"; 193 dmas = <&dma_apbh 0>; 194 dma-names = "rx-tx"; 195 status = "disabled"; 196 }; 197 198 aips1: bus@2000000 { 199 compatible = "fsl,aips-bus", "simple-bus"; 200 #address-cells = <1>; 201 #size-cells = <1>; 202 reg = <0x02000000 0x100000>; 203 ranges; 204 205 spba-bus@2000000 { 206 compatible = "fsl,spba-bus", "simple-bus"; 207 #address-cells = <1>; 208 #size-cells = <1>; 209 reg = <0x02000000 0x40000>; 210 ranges; 211 212 ecspi1: spi@2008000 { 213 #address-cells = <1>; 214 #size-cells = <0>; 215 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 216 reg = <0x02008000 0x4000>; 217 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&clks IMX6UL_CLK_ECSPI1>, 219 <&clks IMX6UL_CLK_ECSPI1>; 220 clock-names = "ipg", "per"; 221 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; 222 dma-names = "rx", "tx"; 223 status = "disabled"; 224 }; 225 226 ecspi2: spi@200c000 { 227 #address-cells = <1>; 228 #size-cells = <0>; 229 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 230 reg = <0x0200c000 0x4000>; 231 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&clks IMX6UL_CLK_ECSPI2>, 233 <&clks IMX6UL_CLK_ECSPI2>; 234 clock-names = "ipg", "per"; 235 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; 236 dma-names = "rx", "tx"; 237 status = "disabled"; 238 }; 239 240 ecspi3: spi@2010000 { 241 #address-cells = <1>; 242 #size-cells = <0>; 243 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 244 reg = <0x02010000 0x4000>; 245 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&clks IMX6UL_CLK_ECSPI3>, 247 <&clks IMX6UL_CLK_ECSPI3>; 248 clock-names = "ipg", "per"; 249 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; 250 dma-names = "rx", "tx"; 251 status = "disabled"; 252 }; 253 254 ecspi4: spi@2014000 { 255 #address-cells = <1>; 256 #size-cells = <0>; 257 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 258 reg = <0x02014000 0x4000>; 259 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&clks IMX6UL_CLK_ECSPI4>, 261 <&clks IMX6UL_CLK_ECSPI4>; 262 clock-names = "ipg", "per"; 263 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; 264 dma-names = "rx", "tx"; 265 status = "disabled"; 266 }; 267 268 uart7: serial@2018000 { 269 compatible = "fsl,imx6ul-uart", 270 "fsl,imx6q-uart"; 271 reg = <0x02018000 0x4000>; 272 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&clks IMX6UL_CLK_UART7_IPG>, 274 <&clks IMX6UL_CLK_UART7_SERIAL>; 275 clock-names = "ipg", "per"; 276 status = "disabled"; 277 }; 278 279 uart1: serial@2020000 { 280 compatible = "fsl,imx6ul-uart", 281 "fsl,imx6q-uart"; 282 reg = <0x02020000 0x4000>; 283 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&clks IMX6UL_CLK_UART1_IPG>, 285 <&clks IMX6UL_CLK_UART1_SERIAL>; 286 clock-names = "ipg", "per"; 287 status = "disabled"; 288 }; 289 290 uart8: serial@2024000 { 291 compatible = "fsl,imx6ul-uart", 292 "fsl,imx6q-uart"; 293 reg = <0x02024000 0x4000>; 294 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&clks IMX6UL_CLK_UART8_IPG>, 296 <&clks IMX6UL_CLK_UART8_SERIAL>; 297 clock-names = "ipg", "per"; 298 status = "disabled"; 299 }; 300 301 sai1: sai@2028000 { 302 #sound-dai-cells = <0>; 303 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; 304 reg = <0x02028000 0x4000>; 305 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&clks IMX6UL_CLK_SAI1_IPG>, 307 <&clks IMX6UL_CLK_SAI1>, 308 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; 309 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 310 dmas = <&sdma 35 24 0>, 311 <&sdma 36 24 0>; 312 dma-names = "rx", "tx"; 313 status = "disabled"; 314 }; 315 316 sai2: sai@202c000 { 317 #sound-dai-cells = <0>; 318 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; 319 reg = <0x0202c000 0x4000>; 320 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&clks IMX6UL_CLK_SAI2_IPG>, 322 <&clks IMX6UL_CLK_SAI2>, 323 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; 324 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 325 dmas = <&sdma 37 24 0>, 326 <&sdma 38 24 0>; 327 dma-names = "rx", "tx"; 328 status = "disabled"; 329 }; 330 331 sai3: sai@2030000 { 332 #sound-dai-cells = <0>; 333 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; 334 reg = <0x02030000 0x4000>; 335 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&clks IMX6UL_CLK_SAI3_IPG>, 337 <&clks IMX6UL_CLK_SAI3>, 338 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; 339 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 340 dmas = <&sdma 39 24 0>, 341 <&sdma 40 24 0>; 342 dma-names = "rx", "tx"; 343 status = "disabled"; 344 }; 345 346 asrc: asrc@2034000 { 347 compatible = "fsl,imx6ul-asrc", "fsl,imx53-asrc"; 348 reg = <0x2034000 0x4000>; 349 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 350 clocks = <&clks IMX6UL_CLK_ASRC_IPG>, 351 <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>, 352 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 353 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 354 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 355 <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>, 356 <&clks IMX6UL_CLK_SPBA>; 357 clock-names = "mem", "ipg", "asrck_0", 358 "asrck_1", "asrck_2", "asrck_3", "asrck_4", 359 "asrck_5", "asrck_6", "asrck_7", "asrck_8", 360 "asrck_9", "asrck_a", "asrck_b", "asrck_c", 361 "asrck_d", "asrck_e", "asrck_f", "spba"; 362 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, 363 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; 364 dma-names = "rxa", "rxb", "rxc", 365 "txa", "txb", "txc"; 366 fsl,asrc-rate = <48000>; 367 fsl,asrc-width = <16>; 368 status = "okay"; 369 }; 370 }; 371 372 tsc: tsc@2040000 { 373 compatible = "fsl,imx6ul-tsc"; 374 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; 375 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&clks IMX6UL_CLK_IPG>, 378 <&clks IMX6UL_CLK_ADC2>; 379 clock-names = "tsc", "adc"; 380 status = "disabled"; 381 }; 382 383 pwm1: pwm@2080000 { 384 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 385 reg = <0x02080000 0x4000>; 386 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&clks IMX6UL_CLK_PWM1>, 388 <&clks IMX6UL_CLK_PWM1>; 389 clock-names = "ipg", "per"; 390 #pwm-cells = <3>; 391 status = "disabled"; 392 }; 393 394 pwm2: pwm@2084000 { 395 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 396 reg = <0x02084000 0x4000>; 397 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&clks IMX6UL_CLK_PWM2>, 399 <&clks IMX6UL_CLK_PWM2>; 400 clock-names = "ipg", "per"; 401 #pwm-cells = <3>; 402 status = "disabled"; 403 }; 404 405 pwm3: pwm@2088000 { 406 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 407 reg = <0x02088000 0x4000>; 408 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&clks IMX6UL_CLK_PWM3>, 410 <&clks IMX6UL_CLK_PWM3>; 411 clock-names = "ipg", "per"; 412 #pwm-cells = <3>; 413 status = "disabled"; 414 }; 415 416 pwm4: pwm@208c000 { 417 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 418 reg = <0x0208c000 0x4000>; 419 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&clks IMX6UL_CLK_PWM4>, 421 <&clks IMX6UL_CLK_PWM4>; 422 clock-names = "ipg", "per"; 423 #pwm-cells = <3>; 424 status = "disabled"; 425 }; 426 427 can1: flexcan@2090000 { 428 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; 429 reg = <0x02090000 0x4000>; 430 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&clks IMX6UL_CLK_CAN1_IPG>, 432 <&clks IMX6UL_CLK_CAN1_SERIAL>; 433 clock-names = "ipg", "per"; 434 fsl,stop-mode = <&gpr 0x10 1 0x10 17>; 435 status = "disabled"; 436 }; 437 438 can2: flexcan@2094000 { 439 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; 440 reg = <0x02094000 0x4000>; 441 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&clks IMX6UL_CLK_CAN2_IPG>, 443 <&clks IMX6UL_CLK_CAN2_SERIAL>; 444 clock-names = "ipg", "per"; 445 fsl,stop-mode = <&gpr 0x10 2 0x10 18>; 446 status = "disabled"; 447 }; 448 449 gpt1: timer@2098000 { 450 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; 451 reg = <0x02098000 0x4000>; 452 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&clks IMX6UL_CLK_GPT1_BUS>, 454 <&clks IMX6UL_CLK_GPT1_SERIAL>; 455 clock-names = "ipg", "per"; 456 }; 457 458 gpio1: gpio@209c000 { 459 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 460 reg = <0x0209c000 0x4000>; 461 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&clks IMX6UL_CLK_GPIO1>; 464 gpio-controller; 465 #gpio-cells = <2>; 466 interrupt-controller; 467 #interrupt-cells = <2>; 468 gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>, 469 <&iomuxc 16 33 16>; 470 }; 471 472 gpio2: gpio@20a0000 { 473 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 474 reg = <0x020a0000 0x4000>; 475 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&clks IMX6UL_CLK_GPIO2>; 478 gpio-controller; 479 #gpio-cells = <2>; 480 interrupt-controller; 481 #interrupt-cells = <2>; 482 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>; 483 }; 484 485 gpio3: gpio@20a4000 { 486 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 487 reg = <0x020a4000 0x4000>; 488 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&clks IMX6UL_CLK_GPIO3>; 491 gpio-controller; 492 #gpio-cells = <2>; 493 interrupt-controller; 494 #interrupt-cells = <2>; 495 gpio-ranges = <&iomuxc 0 65 29>; 496 }; 497 498 gpio4: gpio@20a8000 { 499 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 500 reg = <0x020a8000 0x4000>; 501 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&clks IMX6UL_CLK_GPIO4>; 504 gpio-controller; 505 #gpio-cells = <2>; 506 interrupt-controller; 507 #interrupt-cells = <2>; 508 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>; 509 }; 510 511 gpio5: gpio@20ac000 { 512 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 513 reg = <0x020ac000 0x4000>; 514 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&clks IMX6UL_CLK_GPIO5>; 517 gpio-controller; 518 #gpio-cells = <2>; 519 interrupt-controller; 520 #interrupt-cells = <2>; 521 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>; 522 }; 523 524 fec2: ethernet@20b4000 { 525 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; 526 reg = <0x020b4000 0x4000>; 527 interrupt-names = "int0", "pps"; 528 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&clks IMX6UL_CLK_ENET>, 531 <&clks IMX6UL_CLK_ENET_AHB>, 532 <&clks IMX6UL_CLK_ENET_PTP>, 533 <&clks IMX6UL_CLK_ENET2_REF_125M>, 534 <&clks IMX6UL_CLK_ENET2_REF_125M>; 535 clock-names = "ipg", "ahb", "ptp", 536 "enet_clk_ref", "enet_out"; 537 fsl,num-tx-queues = <1>; 538 fsl,num-rx-queues = <1>; 539 fsl,stop-mode = <&gpr 0x10 4>; 540 status = "disabled"; 541 }; 542 543 kpp: keypad@20b8000 { 544 compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp"; 545 reg = <0x020b8000 0x4000>; 546 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&clks IMX6UL_CLK_KPP>; 548 status = "disabled"; 549 }; 550 551 wdog1: watchdog@20bc000 { 552 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; 553 reg = <0x020bc000 0x4000>; 554 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&clks IMX6UL_CLK_WDOG1>; 556 }; 557 558 wdog2: watchdog@20c0000 { 559 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; 560 reg = <0x020c0000 0x4000>; 561 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&clks IMX6UL_CLK_WDOG2>; 563 status = "disabled"; 564 }; 565 566 clks: clock-controller@20c4000 { 567 compatible = "fsl,imx6ul-ccm"; 568 reg = <0x020c4000 0x4000>; 569 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 571 #clock-cells = <1>; 572 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; 573 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; 574 }; 575 576 anatop: anatop@20c8000 { 577 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", 578 "syscon", "simple-mfd"; 579 reg = <0x020c8000 0x1000>; 580 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 583 584 reg_3p0: regulator-3p0 { 585 compatible = "fsl,anatop-regulator"; 586 regulator-name = "vdd3p0"; 587 regulator-min-microvolt = <2625000>; 588 regulator-max-microvolt = <3400000>; 589 anatop-reg-offset = <0x120>; 590 anatop-vol-bit-shift = <8>; 591 anatop-vol-bit-width = <5>; 592 anatop-min-bit-val = <0>; 593 anatop-min-voltage = <2625000>; 594 anatop-max-voltage = <3400000>; 595 anatop-enable-bit = <0>; 596 }; 597 598 reg_arm: regulator-vddcore { 599 compatible = "fsl,anatop-regulator"; 600 regulator-name = "cpu"; 601 regulator-min-microvolt = <725000>; 602 regulator-max-microvolt = <1450000>; 603 regulator-always-on; 604 anatop-reg-offset = <0x140>; 605 anatop-vol-bit-shift = <0>; 606 anatop-vol-bit-width = <5>; 607 anatop-delay-reg-offset = <0x170>; 608 anatop-delay-bit-shift = <24>; 609 anatop-delay-bit-width = <2>; 610 anatop-min-bit-val = <1>; 611 anatop-min-voltage = <725000>; 612 anatop-max-voltage = <1450000>; 613 }; 614 615 reg_soc: regulator-vddsoc { 616 compatible = "fsl,anatop-regulator"; 617 regulator-name = "vddsoc"; 618 regulator-min-microvolt = <725000>; 619 regulator-max-microvolt = <1450000>; 620 regulator-always-on; 621 anatop-reg-offset = <0x140>; 622 anatop-vol-bit-shift = <18>; 623 anatop-vol-bit-width = <5>; 624 anatop-delay-reg-offset = <0x170>; 625 anatop-delay-bit-shift = <28>; 626 anatop-delay-bit-width = <2>; 627 anatop-min-bit-val = <1>; 628 anatop-min-voltage = <725000>; 629 anatop-max-voltage = <1450000>; 630 }; 631 632 tempmon: tempmon { 633 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; 634 interrupt-parent = <&gpc>; 635 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 636 fsl,tempmon = <&anatop>; 637 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; 638 nvmem-cell-names = "calib", "temp_grade"; 639 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; 640 }; 641 }; 642 643 usbphy1: usbphy@20c9000 { 644 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; 645 reg = <0x020c9000 0x1000>; 646 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&clks IMX6UL_CLK_USBPHY1>; 648 phy-3p0-supply = <®_3p0>; 649 fsl,anatop = <&anatop>; 650 }; 651 652 usbphy2: usbphy@20ca000 { 653 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; 654 reg = <0x020ca000 0x1000>; 655 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&clks IMX6UL_CLK_USBPHY2>; 657 phy-3p0-supply = <®_3p0>; 658 fsl,anatop = <&anatop>; 659 }; 660 661 snvs: snvs@20cc000 { 662 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 663 reg = <0x020cc000 0x4000>; 664 665 snvs_rtc: snvs-rtc-lp { 666 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 667 regmap = <&snvs>; 668 offset = <0x34>; 669 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 671 }; 672 673 snvs_poweroff: snvs-poweroff { 674 compatible = "syscon-poweroff"; 675 regmap = <&snvs>; 676 offset = <0x38>; 677 value = <0x60>; 678 mask = <0x60>; 679 status = "disabled"; 680 }; 681 682 snvs_pwrkey: snvs-powerkey { 683 compatible = "fsl,sec-v4.0-pwrkey"; 684 regmap = <&snvs>; 685 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 686 linux,keycode = <KEY_POWER>; 687 wakeup-source; 688 status = "disabled"; 689 }; 690 691 snvs_lpgpr: snvs-lpgpr { 692 compatible = "fsl,imx6ul-snvs-lpgpr"; 693 }; 694 }; 695 696 epit1: epit@20d0000 { 697 reg = <0x020d0000 0x4000>; 698 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 699 }; 700 701 epit2: epit@20d4000 { 702 reg = <0x020d4000 0x4000>; 703 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 704 }; 705 706 src: reset-controller@20d8000 { 707 compatible = "fsl,imx6ul-src", "fsl,imx51-src"; 708 reg = <0x020d8000 0x4000>; 709 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 711 #reset-cells = <1>; 712 }; 713 714 gpc: gpc@20dc000 { 715 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; 716 reg = <0x020dc000 0x4000>; 717 interrupt-controller; 718 #interrupt-cells = <3>; 719 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 720 interrupt-parent = <&intc>; 721 }; 722 723 iomuxc: pinctrl@20e0000 { 724 compatible = "fsl,imx6ul-iomuxc"; 725 reg = <0x020e0000 0x4000>; 726 }; 727 728 gpr: iomuxc-gpr@20e4000 { 729 compatible = "fsl,imx6ul-iomuxc-gpr", 730 "fsl,imx6q-iomuxc-gpr", "syscon"; 731 reg = <0x020e4000 0x4000>; 732 }; 733 734 gpt2: timer@20e8000 { 735 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; 736 reg = <0x020e8000 0x4000>; 737 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&clks IMX6UL_CLK_GPT2_BUS>, 739 <&clks IMX6UL_CLK_GPT2_SERIAL>; 740 clock-names = "ipg", "per"; 741 status = "disabled"; 742 }; 743 744 sdma: sdma@20ec000 { 745 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma", 746 "fsl,imx35-sdma"; 747 reg = <0x020ec000 0x4000>; 748 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&clks IMX6UL_CLK_IPG>, 750 <&clks IMX6UL_CLK_SDMA>; 751 clock-names = "ipg", "ahb"; 752 #dma-cells = <3>; 753 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 754 }; 755 756 pwm5: pwm@20f0000 { 757 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 758 reg = <0x020f0000 0x4000>; 759 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 760 clocks = <&clks IMX6UL_CLK_PWM5>, 761 <&clks IMX6UL_CLK_PWM5>; 762 clock-names = "ipg", "per"; 763 #pwm-cells = <3>; 764 status = "disabled"; 765 }; 766 767 pwm6: pwm@20f4000 { 768 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 769 reg = <0x020f4000 0x4000>; 770 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&clks IMX6UL_CLK_PWM6>, 772 <&clks IMX6UL_CLK_PWM6>; 773 clock-names = "ipg", "per"; 774 #pwm-cells = <3>; 775 status = "disabled"; 776 }; 777 778 pwm7: pwm@20f8000 { 779 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 780 reg = <0x020f8000 0x4000>; 781 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 782 clocks = <&clks IMX6UL_CLK_PWM7>, 783 <&clks IMX6UL_CLK_PWM7>; 784 clock-names = "ipg", "per"; 785 #pwm-cells = <3>; 786 status = "disabled"; 787 }; 788 789 pwm8: pwm@20fc000 { 790 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 791 reg = <0x020fc000 0x4000>; 792 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 793 clocks = <&clks IMX6UL_CLK_PWM8>, 794 <&clks IMX6UL_CLK_PWM8>; 795 clock-names = "ipg", "per"; 796 #pwm-cells = <3>; 797 status = "disabled"; 798 }; 799 }; 800 801 aips2: bus@2100000 { 802 compatible = "fsl,aips-bus", "simple-bus"; 803 #address-cells = <1>; 804 #size-cells = <1>; 805 reg = <0x02100000 0x100000>; 806 ranges; 807 808 crypto: crypto@2140000 { 809 compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0"; 810 #address-cells = <1>; 811 #size-cells = <1>; 812 reg = <0x2140000 0x3c000>; 813 ranges = <0 0x2140000 0x3c000>; 814 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>, 816 <&clks IMX6UL_CLK_CAAM_MEM>; 817 clock-names = "ipg", "aclk", "mem"; 818 819 sec_jr0: jr@1000 { 820 compatible = "fsl,sec-v4.0-job-ring"; 821 reg = <0x1000 0x1000>; 822 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 823 }; 824 825 sec_jr1: jr@2000 { 826 compatible = "fsl,sec-v4.0-job-ring"; 827 reg = <0x2000 0x1000>; 828 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 829 }; 830 831 sec_jr2: jr@3000 { 832 compatible = "fsl,sec-v4.0-job-ring"; 833 reg = <0x3000 0x1000>; 834 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 835 }; 836 }; 837 838 usbotg1: usb@2184000 { 839 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; 840 reg = <0x02184000 0x200>; 841 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 842 clocks = <&clks IMX6UL_CLK_USBOH3>; 843 fsl,usbphy = <&usbphy1>; 844 fsl,usbmisc = <&usbmisc 0>; 845 fsl,anatop = <&anatop>; 846 ahb-burst-config = <0x0>; 847 tx-burst-size-dword = <0x10>; 848 rx-burst-size-dword = <0x10>; 849 status = "disabled"; 850 }; 851 852 usbotg2: usb@2184200 { 853 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; 854 reg = <0x02184200 0x200>; 855 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 856 clocks = <&clks IMX6UL_CLK_USBOH3>; 857 fsl,usbphy = <&usbphy2>; 858 fsl,usbmisc = <&usbmisc 1>; 859 ahb-burst-config = <0x0>; 860 tx-burst-size-dword = <0x10>; 861 rx-burst-size-dword = <0x10>; 862 status = "disabled"; 863 }; 864 865 usbmisc: usbmisc@2184800 { 866 #index-cells = <1>; 867 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc"; 868 reg = <0x02184800 0x200>; 869 }; 870 871 fec1: ethernet@2188000 { 872 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; 873 reg = <0x02188000 0x4000>; 874 interrupt-names = "int0", "pps"; 875 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 877 clocks = <&clks IMX6UL_CLK_ENET>, 878 <&clks IMX6UL_CLK_ENET_AHB>, 879 <&clks IMX6UL_CLK_ENET_PTP>, 880 <&clks IMX6UL_CLK_ENET_REF>, 881 <&clks IMX6UL_CLK_ENET_REF>; 882 clock-names = "ipg", "ahb", "ptp", 883 "enet_clk_ref", "enet_out"; 884 fsl,num-tx-queues = <1>; 885 fsl,num-rx-queues = <1>; 886 fsl,stop-mode = <&gpr 0x10 3>; 887 status = "disabled"; 888 }; 889 890 usdhc1: mmc@2190000 { 891 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; 892 reg = <0x02190000 0x4000>; 893 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 894 clocks = <&clks IMX6UL_CLK_USDHC1>, 895 <&clks IMX6UL_CLK_USDHC1>, 896 <&clks IMX6UL_CLK_USDHC1>; 897 clock-names = "ipg", "ahb", "per"; 898 fsl,tuning-step = <2>; 899 fsl,tuning-start-tap = <20>; 900 bus-width = <4>; 901 status = "disabled"; 902 }; 903 904 usdhc2: mmc@2194000 { 905 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; 906 reg = <0x02194000 0x4000>; 907 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 908 clocks = <&clks IMX6UL_CLK_USDHC2>, 909 <&clks IMX6UL_CLK_USDHC2>, 910 <&clks IMX6UL_CLK_USDHC2>; 911 clock-names = "ipg", "ahb", "per"; 912 bus-width = <4>; 913 fsl,tuning-step = <2>; 914 fsl,tuning-start-tap = <20>; 915 status = "disabled"; 916 }; 917 918 adc1: adc@2198000 { 919 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc"; 920 reg = <0x02198000 0x4000>; 921 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&clks IMX6UL_CLK_ADC1>; 923 num-channels = <2>; 924 clock-names = "adc"; 925 fsl,adck-max-frequency = <30000000>, <40000000>, 926 <20000000>; 927 status = "disabled"; 928 }; 929 930 i2c1: i2c@21a0000 { 931 #address-cells = <1>; 932 #size-cells = <0>; 933 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 934 reg = <0x021a0000 0x4000>; 935 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 936 clocks = <&clks IMX6UL_CLK_I2C1>; 937 status = "disabled"; 938 }; 939 940 i2c2: i2c@21a4000 { 941 #address-cells = <1>; 942 #size-cells = <0>; 943 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 944 reg = <0x021a4000 0x4000>; 945 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&clks IMX6UL_CLK_I2C2>; 947 status = "disabled"; 948 }; 949 950 i2c3: i2c@21a8000 { 951 #address-cells = <1>; 952 #size-cells = <0>; 953 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 954 reg = <0x021a8000 0x4000>; 955 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 956 clocks = <&clks IMX6UL_CLK_I2C3>; 957 status = "disabled"; 958 }; 959 960 memory-controller@21b0000 { 961 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; 962 reg = <0x021b0000 0x4000>; 963 clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>; 964 }; 965 966 weim: weim@21b8000 { 967 #address-cells = <2>; 968 #size-cells = <1>; 969 compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim"; 970 reg = <0x021b8000 0x4000>; 971 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 972 clocks = <&clks IMX6UL_CLK_EIM>; 973 fsl,weim-cs-gpr = <&gpr>; 974 status = "disabled"; 975 }; 976 977 ocotp: efuse@21bc000 { 978 #address-cells = <1>; 979 #size-cells = <1>; 980 compatible = "fsl,imx6ul-ocotp", "syscon"; 981 reg = <0x021bc000 0x4000>; 982 clocks = <&clks IMX6UL_CLK_OCOTP>; 983 984 tempmon_calib: calib@38 { 985 reg = <0x38 4>; 986 }; 987 988 tempmon_temp_grade: temp-grade@20 { 989 reg = <0x20 4>; 990 }; 991 992 cpu_speed_grade: speed-grade@10 { 993 reg = <0x10 4>; 994 }; 995 }; 996 997 csi: csi@21c4000 { 998 compatible = "fsl,imx6ul-csi"; 999 reg = <0x021c4000 0x4000>; 1000 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1001 clocks = <&clks IMX6UL_CLK_CSI>; 1002 clock-names = "mclk"; 1003 status = "disabled"; 1004 }; 1005 1006 lcdif: lcdif@21c8000 { 1007 compatible = "fsl,imx6ul-lcdif", "fsl,imx6sx-lcdif"; 1008 reg = <0x021c8000 0x4000>; 1009 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>, 1011 <&clks IMX6UL_CLK_LCDIF_APB>, 1012 <&clks IMX6UL_CLK_DUMMY>; 1013 clock-names = "pix", "axi", "disp_axi"; 1014 status = "disabled"; 1015 }; 1016 1017 pxp: pxp@21cc000 { 1018 compatible = "fsl,imx6ul-pxp"; 1019 reg = <0x021cc000 0x4000>; 1020 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1021 clocks = <&clks IMX6UL_CLK_PXP>; 1022 clock-names = "axi"; 1023 }; 1024 1025 qspi: spi@21e0000 { 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 compatible = "fsl,imx6ul-qspi"; 1029 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; 1030 reg-names = "QuadSPI", "QuadSPI-memory"; 1031 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1032 clocks = <&clks IMX6UL_CLK_QSPI>, 1033 <&clks IMX6UL_CLK_QSPI>; 1034 clock-names = "qspi_en", "qspi"; 1035 status = "disabled"; 1036 }; 1037 1038 wdog3: watchdog@21e4000 { 1039 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; 1040 reg = <0x021e4000 0x4000>; 1041 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1042 clocks = <&clks IMX6UL_CLK_WDOG3>; 1043 status = "disabled"; 1044 }; 1045 1046 uart2: serial@21e8000 { 1047 compatible = "fsl,imx6ul-uart", 1048 "fsl,imx6q-uart"; 1049 reg = <0x021e8000 0x4000>; 1050 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1051 clocks = <&clks IMX6UL_CLK_UART2_IPG>, 1052 <&clks IMX6UL_CLK_UART2_SERIAL>; 1053 clock-names = "ipg", "per"; 1054 status = "disabled"; 1055 }; 1056 1057 uart3: serial@21ec000 { 1058 compatible = "fsl,imx6ul-uart", 1059 "fsl,imx6q-uart"; 1060 reg = <0x021ec000 0x4000>; 1061 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1062 clocks = <&clks IMX6UL_CLK_UART3_IPG>, 1063 <&clks IMX6UL_CLK_UART3_SERIAL>; 1064 clock-names = "ipg", "per"; 1065 status = "disabled"; 1066 }; 1067 1068 uart4: serial@21f0000 { 1069 compatible = "fsl,imx6ul-uart", 1070 "fsl,imx6q-uart"; 1071 reg = <0x021f0000 0x4000>; 1072 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1073 clocks = <&clks IMX6UL_CLK_UART4_IPG>, 1074 <&clks IMX6UL_CLK_UART4_SERIAL>; 1075 clock-names = "ipg", "per"; 1076 status = "disabled"; 1077 }; 1078 1079 uart5: serial@21f4000 { 1080 compatible = "fsl,imx6ul-uart", 1081 "fsl,imx6q-uart"; 1082 reg = <0x021f4000 0x4000>; 1083 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1084 clocks = <&clks IMX6UL_CLK_UART5_IPG>, 1085 <&clks IMX6UL_CLK_UART5_SERIAL>; 1086 clock-names = "ipg", "per"; 1087 status = "disabled"; 1088 }; 1089 1090 i2c4: i2c@21f8000 { 1091 #address-cells = <1>; 1092 #size-cells = <0>; 1093 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 1094 reg = <0x021f8000 0x4000>; 1095 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1096 clocks = <&clks IMX6UL_CLK_I2C4>; 1097 status = "disabled"; 1098 }; 1099 1100 uart6: serial@21fc000 { 1101 compatible = "fsl,imx6ul-uart", 1102 "fsl,imx6q-uart"; 1103 reg = <0x021fc000 0x4000>; 1104 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1105 clocks = <&clks IMX6UL_CLK_UART6_IPG>, 1106 <&clks IMX6UL_CLK_UART6_SERIAL>; 1107 clock-names = "ipg", "per"; 1108 status = "disabled"; 1109 }; 1110 }; 1111 }; 1112}; 1113