1 /* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR MIT) 2 * 3 * Rockchip isp2 driver 4 * Copyright (C) 2017 Rockchip Electronics Co., Ltd. 5 */ 6 7 #ifndef _UAPI_RK_ISP2_CONFIG_H 8 #define _UAPI_RK_ISP2_CONFIG_H 9 10 #include <linux/const.h> 11 #include <linux/types.h> 12 #include <linux/v4l2-controls.h> 13 14 #define RKISP_API_VERSION KERNEL_VERSION(2, 2, 2) 15 16 /****************ISP SUBDEV IOCTL*****************************/ 17 18 #define RKISP_CMD_TRIGGER_READ_BACK \ 19 _IOW('V', BASE_VIDIOC_PRIVATE + 0, struct isp2x_csi_trigger) 20 21 #define RKISP_CMD_GET_ISP_INFO \ 22 _IOR('V', BASE_VIDIOC_PRIVATE + 1, struct rkisp_isp_info) 23 24 #define RKISP_CMD_GET_SHARED_BUF \ 25 _IOR('V', BASE_VIDIOC_PRIVATE + 2, struct rkisp_thunderboot_resmem) 26 27 #define RKISP_CMD_FREE_SHARED_BUF \ 28 _IO('V', BASE_VIDIOC_PRIVATE + 3) 29 30 #define RKISP_CMD_GET_LDCHBUF_INFO \ 31 _IOR('V', BASE_VIDIOC_PRIVATE + 4, struct rkisp_ldchbuf_info) 32 33 #define RKISP_CMD_SET_LDCHBUF_SIZE \ 34 _IOW('V', BASE_VIDIOC_PRIVATE + 5, struct rkisp_ldchbuf_size) 35 36 #define RKISP_CMD_GET_SHM_BUFFD \ 37 _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct rkisp_thunderboot_shmem) 38 39 #define RKISP_CMD_GET_FBCBUF_FD \ 40 _IOR('V', BASE_VIDIOC_PRIVATE + 7, struct isp2x_buf_idxfd) 41 42 #define RKISP_CMD_GET_MESHBUF_INFO \ 43 _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct rkisp_meshbuf_info) 44 45 #define RKISP_CMD_SET_MESHBUF_SIZE \ 46 _IOW('V', BASE_VIDIOC_PRIVATE + 9, struct rkisp_meshbuf_size) 47 48 #define RKISP_CMD_INFO2DDR \ 49 _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct rkisp_info2ddr) 50 51 #define RKISP_CMD_MESHBUF_FREE \ 52 _IOW('V', BASE_VIDIOC_PRIVATE + 11, long long) 53 54 /* BASE_VIDIOC_PRIVATE + 12 for RKISP_CMD_GET_TB_HEAD_V32 */ 55 56 /* for all isp device stop and no power off but resolution change */ 57 #define RKISP_CMD_MULTI_DEV_FORCE_ENUM \ 58 _IO('V', BASE_VIDIOC_PRIVATE + 13) 59 60 /****************ISP VIDEO IOCTL******************************/ 61 62 #define RKISP_CMD_GET_CSI_MEMORY_MODE \ 63 _IOR('V', BASE_VIDIOC_PRIVATE + 100, int) 64 65 #define RKISP_CMD_SET_CSI_MEMORY_MODE \ 66 _IOW('V', BASE_VIDIOC_PRIVATE + 101, int) 67 68 #define RKISP_CMD_GET_CMSK \ 69 _IOR('V', BASE_VIDIOC_PRIVATE + 102, struct rkisp_cmsk_cfg) 70 71 #define RKISP_CMD_SET_CMSK \ 72 _IOW('V', BASE_VIDIOC_PRIVATE + 103, struct rkisp_cmsk_cfg) 73 74 #define RKISP_CMD_GET_STREAM_INFO \ 75 _IOR('V', BASE_VIDIOC_PRIVATE + 104, struct rkisp_stream_info) 76 77 #define RKISP_CMD_GET_MIRROR_FLIP \ 78 _IOR('V', BASE_VIDIOC_PRIVATE + 105, struct rkisp_mirror_flip) 79 80 #define RKISP_CMD_SET_MIRROR_FLIP \ 81 _IOW('V', BASE_VIDIOC_PRIVATE + 106, struct rkisp_mirror_flip) 82 83 #define RKISP_CMD_GET_WRAP_LINE \ 84 _IOR('V', BASE_VIDIOC_PRIVATE + 107, struct rkisp_wrap_info) 85 /* set wrap line before VIDIOC_S_FMT */ 86 #define RKISP_CMD_SET_WRAP_LINE \ 87 _IOW('V', BASE_VIDIOC_PRIVATE + 108, struct rkisp_wrap_info) 88 89 #define RKISP_CMD_SET_FPS \ 90 _IOW('V', BASE_VIDIOC_PRIVATE + 109, int) 91 92 #define RKISP_CMD_GET_FPS \ 93 _IOR('V', BASE_VIDIOC_PRIVATE + 110, int) 94 95 #define RKISP_CMD_GET_TB_STREAM_INFO \ 96 _IOR('V', BASE_VIDIOC_PRIVATE + 111, struct rkisp_tb_stream_info) 97 98 #define RKISP_CMD_FREE_TB_STREAM_BUF \ 99 _IO('V', BASE_VIDIOC_PRIVATE + 112) 100 101 #define RKISP_CMD_SET_IQTOOL_CONN_ID \ 102 _IOW('V', BASE_VIDIOC_PRIVATE + 113, int) 103 /*************************************************************/ 104 105 #define ISP2X_ID_DPCC (0) 106 #define ISP2X_ID_BLS (1) 107 #define ISP2X_ID_SDG (2) 108 #define ISP2X_ID_SIHST (3) 109 #define ISP2X_ID_LSC (4) 110 #define ISP2X_ID_AWB_GAIN (5) 111 #define ISP2X_ID_BDM (7) 112 #define ISP2X_ID_CCM (8) 113 #define ISP2X_ID_GOC (9) 114 #define ISP2X_ID_CPROC (10) 115 #define ISP2X_ID_SIAF (11) 116 #define ISP2X_ID_SIAWB (12) 117 #define ISP2X_ID_IE (13) 118 #define ISP2X_ID_YUVAE (14) 119 #define ISP2X_ID_WDR (15) 120 #define ISP2X_ID_RK_IESHARP (16) 121 #define ISP2X_ID_RAWAF (17) 122 #define ISP2X_ID_RAWAE0 (18) 123 #define ISP2X_ID_RAWAE1 (19) 124 #define ISP2X_ID_RAWAE2 (20) 125 #define ISP2X_ID_RAWAE3 (21) 126 #define ISP2X_ID_RAWAWB (22) 127 #define ISP2X_ID_RAWHIST0 (23) 128 #define ISP2X_ID_RAWHIST1 (24) 129 #define ISP2X_ID_RAWHIST2 (25) 130 #define ISP2X_ID_RAWHIST3 (26) 131 #define ISP2X_ID_HDRMGE (27) 132 #define ISP2X_ID_RAWNR (28) 133 #define ISP2X_ID_HDRTMO (29) 134 #define ISP2X_ID_GIC (30) 135 #define ISP2X_ID_DHAZ (31) 136 #define ISP2X_ID_3DLUT (32) 137 #define ISP2X_ID_LDCH (33) 138 #define ISP2X_ID_GAIN (34) 139 #define ISP2X_ID_DEBAYER (35) 140 #define ISP2X_ID_MAX (63) 141 142 #define ISP2X_MODULE_DPCC _BITULL(ISP2X_ID_DPCC) 143 #define ISP2X_MODULE_BLS _BITULL(ISP2X_ID_BLS) 144 #define ISP2X_MODULE_SDG _BITULL(ISP2X_ID_SDG) 145 #define ISP2X_MODULE_SIHST _BITULL(ISP2X_ID_SIHST) 146 #define ISP2X_MODULE_LSC _BITULL(ISP2X_ID_LSC) 147 #define ISP2X_MODULE_AWB_GAIN _BITULL(ISP2X_ID_AWB_GAIN) 148 #define ISP2X_MODULE_BDM _BITULL(ISP2X_ID_BDM) 149 #define ISP2X_MODULE_CCM _BITULL(ISP2X_ID_CCM) 150 #define ISP2X_MODULE_GOC _BITULL(ISP2X_ID_GOC) 151 #define ISP2X_MODULE_CPROC _BITULL(ISP2X_ID_CPROC) 152 #define ISP2X_MODULE_SIAF _BITULL(ISP2X_ID_SIAF) 153 #define ISP2X_MODULE_SIAWB _BITULL(ISP2X_ID_SIAWB) 154 #define ISP2X_MODULE_IE _BITULL(ISP2X_ID_IE) 155 #define ISP2X_MODULE_YUVAE _BITULL(ISP2X_ID_YUVAE) 156 #define ISP2X_MODULE_WDR _BITULL(ISP2X_ID_WDR) 157 #define ISP2X_MODULE_RK_IESHARP _BITULL(ISP2X_ID_RK_IESHARP) 158 #define ISP2X_MODULE_RAWAF _BITULL(ISP2X_ID_RAWAF) 159 #define ISP2X_MODULE_RAWAE0 _BITULL(ISP2X_ID_RAWAE0) 160 #define ISP2X_MODULE_RAWAE1 _BITULL(ISP2X_ID_RAWAE1) 161 #define ISP2X_MODULE_RAWAE2 _BITULL(ISP2X_ID_RAWAE2) 162 #define ISP2X_MODULE_RAWAE3 _BITULL(ISP2X_ID_RAWAE3) 163 #define ISP2X_MODULE_RAWAWB _BITULL(ISP2X_ID_RAWAWB) 164 #define ISP2X_MODULE_RAWHIST0 _BITULL(ISP2X_ID_RAWHIST0) 165 #define ISP2X_MODULE_RAWHIST1 _BITULL(ISP2X_ID_RAWHIST1) 166 #define ISP2X_MODULE_RAWHIST2 _BITULL(ISP2X_ID_RAWHIST2) 167 #define ISP2X_MODULE_RAWHIST3 _BITULL(ISP2X_ID_RAWHIST3) 168 #define ISP2X_MODULE_HDRMGE _BITULL(ISP2X_ID_HDRMGE) 169 #define ISP2X_MODULE_RAWNR _BITULL(ISP2X_ID_RAWNR) 170 #define ISP2X_MODULE_HDRTMO _BITULL(ISP2X_ID_HDRTMO) 171 #define ISP2X_MODULE_GIC _BITULL(ISP2X_ID_GIC) 172 #define ISP2X_MODULE_DHAZ _BITULL(ISP2X_ID_DHAZ) 173 #define ISP2X_MODULE_3DLUT _BITULL(ISP2X_ID_3DLUT) 174 #define ISP2X_MODULE_LDCH _BITULL(ISP2X_ID_LDCH) 175 #define ISP2X_MODULE_GAIN _BITULL(ISP2X_ID_GAIN) 176 #define ISP2X_MODULE_DEBAYER _BITULL(ISP2X_ID_DEBAYER) 177 178 #define ISP2X_MODULE_FORCE _BITULL(ISP2X_ID_MAX) 179 180 /* 181 * Measurement types 182 */ 183 #define ISP2X_STAT_SIAWB _BITUL(0) 184 #define ISP2X_STAT_YUVAE _BITUL(1) 185 #define ISP2X_STAT_SIAF _BITUL(2) 186 #define ISP2X_STAT_SIHST _BITUL(3) 187 #define ISP2X_STAT_EMB_DATA _BITUL(4) 188 #define ISP2X_STAT_RAWAWB _BITUL(5) 189 #define ISP2X_STAT_RAWAF _BITUL(6) 190 #define ISP2X_STAT_RAWAE0 _BITUL(7) 191 #define ISP2X_STAT_RAWAE1 _BITUL(8) 192 #define ISP2X_STAT_RAWAE2 _BITUL(9) 193 #define ISP2X_STAT_RAWAE3 _BITUL(10) 194 #define ISP2X_STAT_RAWHST0 _BITUL(11) 195 #define ISP2X_STAT_RAWHST1 _BITUL(12) 196 #define ISP2X_STAT_RAWHST2 _BITUL(13) 197 #define ISP2X_STAT_RAWHST3 _BITUL(14) 198 #define ISP2X_STAT_BLS _BITUL(15) 199 #define ISP2X_STAT_HDRTMO _BITUL(16) 200 #define ISP2X_STAT_DHAZ _BITUL(17) 201 202 #define ISP2X_LSC_GRAD_TBL_SIZE 8 203 #define ISP2X_LSC_SIZE_TBL_SIZE 8 204 #define ISP2X_LSC_DATA_TBL_SIZE 290 205 206 #define ISP2X_DEGAMMA_CURVE_SIZE 17 207 208 #define ISP2X_GAIN_HDRMGE_GAIN_NUM 3 209 #define ISP2X_GAIN_IDX_NUM 15 210 #define ISP2X_GAIN_LUT_NUM 17 211 212 #define ISP2X_AWB_MAX_GRID 1 213 #define ISP2X_RAWAWB_SUM_NUM 7 214 #define ISP2X_RAWAWB_MULWD_NUM 8 215 #define ISP2X_RAWAWB_RAMDATA_NUM 225 216 217 #define ISP2X_RAWAEBIG_SUBWIN_NUM 4 218 #define ISP2X_RAWAEBIG_MEAN_NUM 225 219 #define ISP2X_RAWAELITE_MEAN_NUM 25 220 #define ISP2X_YUVAE_SUBWIN_NUM 4 221 #define ISP2X_YUVAE_MEAN_NUM 225 222 223 #define ISP2X_RAWHISTBIG_SUBWIN_NUM 225 224 #define ISP2X_RAWHISTLITE_SUBWIN_NUM 25 225 #define ISP2X_SIHIST_WIN_NUM 1 226 #define ISP2X_HIST_WEIGHT_NUM 225 227 #define ISP2X_HIST_BIN_N_MAX 256 228 #define ISP2X_SIHIST_BIN_N_MAX 32 229 230 #define ISP2X_RAWAF_WIN_NUM 2 231 #define ISP2X_RAWAF_LINE_NUM 5 232 #define ISP2X_RAWAF_GAMMA_NUM 17 233 #define ISP2X_RAWAF_SUMDATA_ROW 15 234 #define ISP2X_RAWAF_SUMDATA_COLUMN 15 235 #define ISP2X_RAWAF_SUMDATA_NUM 225 236 #define ISP2X_AFM_MAX_WINDOWS 3 237 238 #define ISP2X_DPCC_PDAF_POINT_NUM 16 239 240 #define ISP2X_HDRMGE_L_CURVE_NUM 17 241 #define ISP2X_HDRMGE_E_CURVE_NUM 17 242 243 #define ISP2X_RAWNR_LUMA_RATION_NUM 8 244 245 #define ISP2X_HDRTMO_MINMAX_NUM 32 246 247 #define ISP2X_GIC_SIGMA_Y_NUM 15 248 249 #define ISP2X_CCM_CURVE_NUM 17 250 251 /* WDR */ 252 #define ISP2X_WDR_SIZE 48 253 254 #define ISP2X_DHAZ_CONV_COEFF_NUM 6 255 #define ISP2X_DHAZ_HIST_IIR_NUM 64 256 257 #define ISP2X_GAMMA_OUT_MAX_SAMPLES 45 258 259 #define ISP2X_MIPI_LUMA_MEAN_MAX 16 260 #define ISP2X_MIPI_RAW_MAX 3 261 #define ISP2X_RAW0_Y_STATE (1 << 0) 262 #define ISP2X_RAW1_Y_STATE (1 << 1) 263 #define ISP2X_RAW2_Y_STATE (1 << 2) 264 265 #define ISP2X_3DLUT_DATA_NUM 729 266 267 #define ISP2X_LDCH_MESH_XY_NUM 0x80000 268 #define ISP2X_LDCH_BUF_NUM 2 269 270 #define ISP2X_THUNDERBOOT_VIDEO_BUF_NUM 30 271 272 #define ISP2X_FBCBUF_FD_NUM 64 273 274 #define ISP2X_MESH_BUF_NUM 2 275 276 enum rkisp_isp_mode { 277 /* frame input related */ 278 RKISP_ISP_NORMAL = _BITUL(0), 279 RKISP_ISP_HDR2 = _BITUL(1), 280 RKISP_ISP_HDR3 = _BITUL(2), 281 RKISP_ISP_COMPR = _BITUL(3), 282 283 /* isp function related */ 284 RKISP_ISP_BIGMODE = _BITUL(28), 285 }; 286 287 struct rkisp_isp_info { 288 enum rkisp_isp_mode mode; 289 __u32 act_width; 290 __u32 act_height; 291 __u8 compr_bit; 292 } __attribute__ ((packed)); 293 294 enum isp2x_mesh_buf_stat { 295 MESH_BUF_INIT = 0, 296 MESH_BUF_WAIT2CHIP, 297 MESH_BUF_CHIPINUSE, 298 }; 299 300 struct rkisp_meshbuf_info { 301 __u64 module_id; 302 __u32 unite_isp_id; 303 __s32 buf_fd[ISP2X_MESH_BUF_NUM]; 304 __u32 buf_size[ISP2X_MESH_BUF_NUM]; 305 } __attribute__ ((packed)); 306 307 struct rkisp_meshbuf_size { 308 __u64 module_id; 309 __u32 unite_isp_id; 310 __u32 meas_width; 311 __u32 meas_height; 312 int buf_cnt; 313 } __attribute__ ((packed)); 314 315 struct isp2x_mesh_head { 316 enum isp2x_mesh_buf_stat stat; 317 __u32 data_oft; 318 } __attribute__ ((packed)); 319 320 #define RKISP_CMSK_WIN_MAX 12 321 #define RKISP_CMSK_WIN_MAX_V30 8 322 #define RKISP_CMSK_MOSAIC_MODE 0 323 #define RKISP_CMSK_COVER_MODE 1 324 325 /* struct rkisp_cmsk_win 326 * Priacy Mask Window configture, support windows 327 * RKISP_CMSK_WIN_MAX_V30 for rk3588 support 8 windows, and 328 * support for mainpath and selfpath output stream channel. 329 * 330 * RKISP_CMSK_WIN_MAX for rv1106 support 12 windows, and 331 * support for mainpath selfpath and bypasspath output stream channel. 332 * 333 * mode: 0:mosaic mode, 1:cover mode 334 * win_index: window index 0~11. windows overlap, priority win11 > win0. 335 * cover_color_y: cover mode effective, share for stream channel when same win_index. 336 * cover_color_u: cover mode effective, share for stream channel when same win_index. 337 * cover_color_v: cover mode effective, share for stream channel when same win_index. 338 * 339 * h_offs: window horizontal offset, share for stream channel when same win_index. 2 align. 340 * v_offs: window vertical offset, share for stream channel when same win_index. 2 align. 341 * h_size: window horizontal size, share for stream channel when same win_index. 8 align for rk3588, 2 align for rv1106. 342 * v_size: window vertical size, share for stream channel when same win_index. 8 align for rk3588, 2 align for rv1106. 343 */ 344 struct rkisp_cmsk_win { 345 unsigned short mode; 346 unsigned short win_en; 347 348 unsigned char cover_color_y; 349 unsigned char cover_color_u; 350 unsigned char cover_color_v; 351 352 unsigned short h_offs; 353 unsigned short v_offs; 354 unsigned short h_size; 355 unsigned short v_size; 356 } __attribute__ ((packed)); 357 358 /* struct rkisp_cmsk_cfg 359 * win: priacy mask window 360 * mosaic_block: Mosaic block size, 0:8x8 1:16x16 2:32x32 3:64x64, share for all windows 361 * width_ro: isp full resolution, h_offs + h_size <= width_ro. 362 * height_ro: isp full resolution, v_offs + v_size <= height_ro. 363 */ 364 struct rkisp_cmsk_cfg { 365 struct rkisp_cmsk_win win[RKISP_CMSK_WIN_MAX]; 366 unsigned int mosaic_block; 367 unsigned int width_ro; 368 unsigned int height_ro; 369 } __attribute__ ((packed)); 370 371 /* struct rkisp_stream_info 372 * cur_frame_id: stream current frame id 373 * input_frame_loss: isp input frame loss num 374 * output_frame_loss: stream output frame loss num 375 * stream_on: stream on/off 376 */ 377 struct rkisp_stream_info { 378 unsigned int cur_frame_id; 379 unsigned int input_frame_loss; 380 unsigned int output_frame_loss; 381 unsigned char stream_on; 382 unsigned char stream_id; 383 } __attribute__ ((packed)); 384 385 /* struct rkisp_mirror_flip 386 * mirror: global for all output stream 387 * flip: independent for all output stream 388 */ 389 struct rkisp_mirror_flip { 390 unsigned char mirror; 391 unsigned char flip; 392 } __attribute__ ((packed)); 393 394 struct rkisp_wrap_info { 395 int width; 396 int height; 397 }; 398 399 #define RKISP_TB_STREAM_BUF_MAX 5 400 struct rkisp_tb_stream_buf { 401 unsigned int dma_addr; 402 unsigned int sequence; 403 long long timestamp; 404 } __attribute__ ((packed)); 405 406 /* struct rkisp_tb_stream_info 407 * frame_size: nv12 frame buf size, bytesperline * height_16align * 1.5 408 * buf_max: memory size / frame_size 409 * buf_cnt: the num of frame write to buf. 410 */ 411 struct rkisp_tb_stream_info { 412 unsigned int width; 413 unsigned int height; 414 unsigned int bytesperline; 415 unsigned int frame_size; 416 unsigned int buf_max; 417 unsigned int buf_cnt; 418 struct rkisp_tb_stream_buf buf[RKISP_TB_STREAM_BUF_MAX]; 419 } __attribute__ ((packed)); 420 421 /* trigger event mode 422 * T_TRY: trigger maybe with retry 423 * T_TRY_YES: trigger to retry 424 * T_TRY_NO: trigger no to retry 425 * 426 * T_START_X1: isp read one frame 427 * T_START_X2: isp read hdr two frame 428 * T_START_X3: isp read hdr three frame 429 * T_START_C: isp read hdr linearised and compressed data 430 */ 431 enum isp2x_trigger_mode { 432 T_TRY = _BITUL(0), 433 T_TRY_YES = _BITUL(1), 434 T_TRY_NO = _BITUL(2), 435 436 T_START_X1 = _BITUL(4), 437 T_START_X2 = _BITUL(5), 438 T_START_X3 = _BITUL(6), 439 T_START_C = _BITUL(7), 440 }; 441 442 struct isp2x_csi_trigger { 443 /* timestamp in ns */ 444 __u64 sof_timestamp; 445 __u64 frame_timestamp; 446 __u32 frame_id; 447 int times; 448 enum isp2x_trigger_mode mode; 449 } __attribute__ ((packed)); 450 451 /* isp csi dmatx/dmarx memory mode 452 * 0: raw12/raw10/raw8 8bit memory compact 453 * 1: raw12/raw10 16bit memory one pixel 454 * big endian for rv1126/rv1109 455 * |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| 456 * | 3| 2| 1| 0| -| -| -| -|11|10| 9| 8| 7| 6| 5| 4| 457 * little align for rk356x 458 * |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| 459 * | -| -| -| -|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| 460 * 2: raw12/raw10 16bit memory one pixel 461 * big align for rv1126/rv1109/rk356x 462 * |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| 463 * |11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| -| -| -| -| 464 */ 465 enum isp_csi_memory { 466 CSI_MEM_COMPACT = 0, 467 CSI_MEM_WORD_BIG_END = 1, 468 CSI_MEM_WORD_LITTLE_ALIGN = 1, 469 CSI_MEM_WORD_BIG_ALIGN = 2, 470 }; 471 472 #define RKISP_INFO2DDR_BUF_MAX 4 473 /* 32bit flag for user set to memory after buf used */ 474 #define RKISP_INFO2DDR_BUF_INIT 0x5AA5 475 476 enum rkisp_info2ddr_owner { 477 RKISP_INFO2DRR_OWNER_NULL, 478 RKISP_INFO2DRR_OWNER_GAIN, 479 RKISP_INFO2DRR_OWNER_AWB, 480 }; 481 482 /* struct rkisp_info2ddr 483 * awb and gain debug info write to ddr 484 * 485 * owner: 0: off, 1: gain, 2: awb. 486 * u: gain or awb mode parameters. 487 * buf_cnt: buf num to request. return actual result. 488 * buf_fd: fd of memory alloc result. 489 * wsize: data width to request. if useless to 0. return actual result. 490 * vsize: data height to request. if useless to 0. return actual result. 491 */ 492 struct rkisp_info2ddr { 493 enum rkisp_info2ddr_owner owner; 494 495 union { 496 struct { 497 __u8 gain2ddr_mode; 498 } gain; 499 500 struct { 501 __u8 awb2ddr_sel; 502 } awb; 503 } u; 504 505 __u8 buf_cnt; 506 __s32 buf_fd[RKISP_INFO2DDR_BUF_MAX]; 507 508 __u32 wsize; 509 __u32 vsize; 510 } __attribute__ ((packed)); 511 512 struct isp2x_ispgain_buf { 513 __u32 gain_dmaidx; 514 __u32 mfbc_dmaidx; 515 __u32 gain_size; 516 __u32 mfbc_size; 517 __u32 frame_id; 518 } __attribute__ ((packed)); 519 520 struct isp2x_buf_idxfd { 521 __u32 buf_num; 522 __u32 index[ISP2X_FBCBUF_FD_NUM]; 523 __s32 dmafd[ISP2X_FBCBUF_FD_NUM]; 524 } __attribute__ ((packed)); 525 526 struct isp2x_window { 527 __u16 h_offs; 528 __u16 v_offs; 529 __u16 h_size; 530 __u16 v_size; 531 } __attribute__ ((packed)); 532 533 struct isp2x_bls_fixed_val { 534 __s16 r; 535 __s16 gr; 536 __s16 gb; 537 __s16 b; 538 } __attribute__ ((packed)); 539 540 struct isp2x_bls_cfg { 541 __u8 enable_auto; 542 __u8 en_windows; 543 struct isp2x_window bls_window1; 544 struct isp2x_window bls_window2; 545 __u8 bls_samples; 546 struct isp2x_bls_fixed_val fixed_val; 547 } __attribute__ ((packed)); 548 549 struct isp2x_bls_stat { 550 __u16 meas_r; 551 __u16 meas_gr; 552 __u16 meas_gb; 553 __u16 meas_b; 554 } __attribute__ ((packed)); 555 556 struct isp2x_dpcc_pdaf_point { 557 __u8 y; 558 __u8 x; 559 } __attribute__ ((packed)); 560 561 struct isp2x_dpcc_cfg { 562 /* mode 0x0000 */ 563 __u8 stage1_enable; 564 __u8 grayscale_mode; 565 566 /* output_mode 0x0004 */ 567 __u8 sw_rk_out_sel; 568 __u8 sw_dpcc_output_sel; 569 __u8 stage1_rb_3x3; 570 __u8 stage1_g_3x3; 571 __u8 stage1_incl_rb_center; 572 __u8 stage1_incl_green_center; 573 574 /* set_use 0x0008 */ 575 __u8 stage1_use_fix_set; 576 __u8 stage1_use_set_3; 577 __u8 stage1_use_set_2; 578 __u8 stage1_use_set_1; 579 580 /* methods_set_1 0x000c */ 581 __u8 sw_rk_red_blue1_en; 582 __u8 rg_red_blue1_enable; 583 __u8 rnd_red_blue1_enable; 584 __u8 ro_red_blue1_enable; 585 __u8 lc_red_blue1_enable; 586 __u8 pg_red_blue1_enable; 587 __u8 sw_rk_green1_en; 588 __u8 rg_green1_enable; 589 __u8 rnd_green1_enable; 590 __u8 ro_green1_enable; 591 __u8 lc_green1_enable; 592 __u8 pg_green1_enable; 593 594 /* methods_set_2 0x0010 */ 595 __u8 sw_rk_red_blue2_en; 596 __u8 rg_red_blue2_enable; 597 __u8 rnd_red_blue2_enable; 598 __u8 ro_red_blue2_enable; 599 __u8 lc_red_blue2_enable; 600 __u8 pg_red_blue2_enable; 601 __u8 sw_rk_green2_en; 602 __u8 rg_green2_enable; 603 __u8 rnd_green2_enable; 604 __u8 ro_green2_enable; 605 __u8 lc_green2_enable; 606 __u8 pg_green2_enable; 607 608 /* methods_set_3 0x0014 */ 609 __u8 sw_rk_red_blue3_en; 610 __u8 rg_red_blue3_enable; 611 __u8 rnd_red_blue3_enable; 612 __u8 ro_red_blue3_enable; 613 __u8 lc_red_blue3_enable; 614 __u8 pg_red_blue3_enable; 615 __u8 sw_rk_green3_en; 616 __u8 rg_green3_enable; 617 __u8 rnd_green3_enable; 618 __u8 ro_green3_enable; 619 __u8 lc_green3_enable; 620 __u8 pg_green3_enable; 621 622 /* line_thresh_1 0x0018 */ 623 __u8 sw_mindis1_rb; 624 __u8 sw_mindis1_g; 625 __u8 line_thr_1_rb; 626 __u8 line_thr_1_g; 627 628 /* line_mad_fac_1 0x001c */ 629 __u8 sw_dis_scale_min1; 630 __u8 sw_dis_scale_max1; 631 __u8 line_mad_fac_1_rb; 632 __u8 line_mad_fac_1_g; 633 634 /* pg_fac_1 0x0020 */ 635 __u8 pg_fac_1_rb; 636 __u8 pg_fac_1_g; 637 638 /* rnd_thresh_1 0x0024 */ 639 __u8 rnd_thr_1_rb; 640 __u8 rnd_thr_1_g; 641 642 /* rg_fac_1 0x0028 */ 643 __u8 rg_fac_1_rb; 644 __u8 rg_fac_1_g; 645 646 /* line_thresh_2 0x002c */ 647 __u8 sw_mindis2_rb; 648 __u8 sw_mindis2_g; 649 __u8 line_thr_2_rb; 650 __u8 line_thr_2_g; 651 652 /* line_mad_fac_2 0x0030 */ 653 __u8 sw_dis_scale_min2; 654 __u8 sw_dis_scale_max2; 655 __u8 line_mad_fac_2_rb; 656 __u8 line_mad_fac_2_g; 657 658 /* pg_fac_2 0x0034 */ 659 __u8 pg_fac_2_rb; 660 __u8 pg_fac_2_g; 661 662 /* rnd_thresh_2 0x0038 */ 663 __u8 rnd_thr_2_rb; 664 __u8 rnd_thr_2_g; 665 666 /* rg_fac_2 0x003c */ 667 __u8 rg_fac_2_rb; 668 __u8 rg_fac_2_g; 669 670 /* line_thresh_3 0x0040 */ 671 __u8 sw_mindis3_rb; 672 __u8 sw_mindis3_g; 673 __u8 line_thr_3_rb; 674 __u8 line_thr_3_g; 675 676 /* line_mad_fac_3 0x0044 */ 677 __u8 sw_dis_scale_min3; 678 __u8 sw_dis_scale_max3; 679 __u8 line_mad_fac_3_rb; 680 __u8 line_mad_fac_3_g; 681 682 /* pg_fac_3 0x0048 */ 683 __u8 pg_fac_3_rb; 684 __u8 pg_fac_3_g; 685 686 /* rnd_thresh_3 0x004c */ 687 __u8 rnd_thr_3_rb; 688 __u8 rnd_thr_3_g; 689 690 /* rg_fac_3 0x0050 */ 691 __u8 rg_fac_3_rb; 692 __u8 rg_fac_3_g; 693 694 /* ro_limits 0x0054 */ 695 __u8 ro_lim_3_rb; 696 __u8 ro_lim_3_g; 697 __u8 ro_lim_2_rb; 698 __u8 ro_lim_2_g; 699 __u8 ro_lim_1_rb; 700 __u8 ro_lim_1_g; 701 702 /* rnd_offs 0x0058 */ 703 __u8 rnd_offs_3_rb; 704 __u8 rnd_offs_3_g; 705 __u8 rnd_offs_2_rb; 706 __u8 rnd_offs_2_g; 707 __u8 rnd_offs_1_rb; 708 __u8 rnd_offs_1_g; 709 710 /* bpt_ctrl 0x005c */ 711 __u8 bpt_rb_3x3; 712 __u8 bpt_g_3x3; 713 __u8 bpt_incl_rb_center; 714 __u8 bpt_incl_green_center; 715 __u8 bpt_use_fix_set; 716 __u8 bpt_use_set_3; 717 __u8 bpt_use_set_2; 718 __u8 bpt_use_set_1; 719 __u8 bpt_cor_en; 720 __u8 bpt_det_en; 721 722 /* bpt_number 0x0060 */ 723 __u16 bp_number; 724 725 /* bpt_addr 0x0064 */ 726 __u16 bp_table_addr; 727 728 /* bpt_data 0x0068 */ 729 __u16 bpt_v_addr; 730 __u16 bpt_h_addr; 731 732 /* bp_cnt 0x006c */ 733 __u32 bp_cnt; 734 735 /* pdaf_en 0x0070 */ 736 __u8 sw_pdaf_en; 737 738 /* pdaf_point_en 0x0074 */ 739 __u8 pdaf_point_en[ISP2X_DPCC_PDAF_POINT_NUM]; 740 741 /* pdaf_offset 0x0078 */ 742 __u16 pdaf_offsety; 743 __u16 pdaf_offsetx; 744 745 /* pdaf_wrap 0x007c */ 746 __u16 pdaf_wrapy; 747 __u16 pdaf_wrapx; 748 749 /* pdaf_scope 0x0080 */ 750 __u16 pdaf_wrapy_num; 751 __u16 pdaf_wrapx_num; 752 753 /* pdaf_point_0 0x0084 */ 754 struct isp2x_dpcc_pdaf_point point[ISP2X_DPCC_PDAF_POINT_NUM]; 755 756 /* pdaf_forward_med 0x00a4 */ 757 __u8 pdaf_forward_med; 758 } __attribute__ ((packed)); 759 760 struct isp2x_hdrmge_curve { 761 __u16 curve_1[ISP2X_HDRMGE_L_CURVE_NUM]; 762 __u16 curve_0[ISP2X_HDRMGE_L_CURVE_NUM]; 763 } __attribute__ ((packed)); 764 765 struct isp2x_hdrmge_cfg { 766 __u8 mode; 767 768 __u16 gain0_inv; 769 __u16 gain0; 770 771 __u16 gain1_inv; 772 __u16 gain1; 773 774 __u8 gain2; 775 776 __u8 lm_dif_0p15; 777 __u8 lm_dif_0p9; 778 __u8 ms_diff_0p15; 779 __u8 ms_dif_0p8; 780 781 struct isp2x_hdrmge_curve curve; 782 __u16 e_y[ISP2X_HDRMGE_E_CURVE_NUM]; 783 } __attribute__ ((packed)); 784 785 struct isp2x_rawnr_cfg { 786 __u8 gauss_en; 787 __u8 log_bypass; 788 789 __u16 filtpar0; 790 __u16 filtpar1; 791 __u16 filtpar2; 792 793 __u32 dgain0; 794 __u32 dgain1; 795 __u32 dgain2; 796 797 __u16 luration[ISP2X_RAWNR_LUMA_RATION_NUM]; 798 __u16 lulevel[ISP2X_RAWNR_LUMA_RATION_NUM]; 799 800 __u32 gauss; 801 __u16 sigma; 802 __u16 pix_diff; 803 804 __u32 thld_diff; 805 806 __u8 gas_weig_scl2; 807 __u8 gas_weig_scl1; 808 __u16 thld_chanelw; 809 810 __u16 lamda; 811 812 __u16 fixw0; 813 __u16 fixw1; 814 __u16 fixw2; 815 __u16 fixw3; 816 817 __u32 wlamda0; 818 __u32 wlamda1; 819 __u32 wlamda2; 820 821 __u16 rgain_filp; 822 __u16 bgain_filp; 823 } __attribute__ ((packed)); 824 825 struct isp2x_lsc_cfg { 826 __u16 r_data_tbl[ISP2X_LSC_DATA_TBL_SIZE]; 827 __u16 gr_data_tbl[ISP2X_LSC_DATA_TBL_SIZE]; 828 __u16 gb_data_tbl[ISP2X_LSC_DATA_TBL_SIZE]; 829 __u16 b_data_tbl[ISP2X_LSC_DATA_TBL_SIZE]; 830 831 __u16 x_grad_tbl[ISP2X_LSC_GRAD_TBL_SIZE]; 832 __u16 y_grad_tbl[ISP2X_LSC_GRAD_TBL_SIZE]; 833 834 __u16 x_size_tbl[ISP2X_LSC_SIZE_TBL_SIZE]; 835 __u16 y_size_tbl[ISP2X_LSC_SIZE_TBL_SIZE]; 836 } __attribute__ ((packed)); 837 838 enum isp2x_goc_mode { 839 ISP2X_GOC_MODE_LOGARITHMIC, 840 ISP2X_GOC_MODE_EQUIDISTANT 841 }; 842 843 struct isp2x_goc_cfg { 844 enum isp2x_goc_mode mode; 845 __u8 gamma_y[17]; 846 } __attribute__ ((packed)); 847 848 struct isp2x_hdrtmo_predict { 849 __u8 global_tmo; 850 __s32 iir_max; 851 __s32 global_tmo_strength; 852 853 __u8 scene_stable; 854 __s32 k_rolgmean; 855 __s32 iir; 856 } __attribute__ ((packed)); 857 858 struct isp2x_hdrtmo_cfg { 859 __u16 cnt_vsize; 860 __u8 gain_ld_off2; 861 __u8 gain_ld_off1; 862 __u8 big_en; 863 __u8 nobig_en; 864 __u8 newhst_en; 865 __u8 cnt_mode; 866 867 __u16 expl_lgratio; 868 __u8 lgscl_ratio; 869 __u8 cfg_alpha; 870 871 __u16 set_gainoff; 872 __u16 set_palpha; 873 874 __u16 set_lgmax; 875 __u16 set_lgmin; 876 877 __u8 set_weightkey; 878 __u16 set_lgmean; 879 880 __u16 set_lgrange1; 881 __u16 set_lgrange0; 882 883 __u16 set_lgavgmax; 884 885 __u8 clipgap1_i; 886 __u8 clipgap0_i; 887 __u8 clipratio1; 888 __u8 clipratio0; 889 __u8 ratiol; 890 891 __u16 lgscl_inv; 892 __u16 lgscl; 893 894 __u16 lgmax; 895 896 __u16 hist_low; 897 __u16 hist_min; 898 899 __u8 hist_shift; 900 __u16 hist_0p3; 901 __u16 hist_high; 902 903 __u16 palpha_lwscl; 904 __u16 palpha_lw0p5; 905 __u16 palpha_0p18; 906 907 __u16 maxgain; 908 __u16 maxpalpha; 909 910 struct isp2x_hdrtmo_predict predict; 911 } __attribute__ ((packed)); 912 913 struct isp2x_hdrtmo_stat { 914 __u16 lglow; 915 __u16 lgmin; 916 __u16 lghigh; 917 __u16 lgmax; 918 __u16 weightkey; 919 __u16 lgmean; 920 __u16 lgrange1; 921 __u16 lgrange0; 922 __u16 palpha; 923 __u16 lgavgmax; 924 __u16 linecnt; 925 __u32 min_max[ISP2X_HDRTMO_MINMAX_NUM]; 926 } __attribute__ ((packed)); 927 928 struct isp2x_gic_cfg { 929 __u8 edge_open; 930 931 __u16 regmingradthrdark2; 932 __u16 regmingradthrdark1; 933 __u16 regminbusythre; 934 935 __u16 regdarkthre; 936 __u16 regmaxcorvboth; 937 __u16 regdarktthrehi; 938 939 __u8 regkgrad2dark; 940 __u8 regkgrad1dark; 941 __u8 regstrengthglobal_fix; 942 __u8 regdarkthrestep; 943 __u8 regkgrad2; 944 __u8 regkgrad1; 945 __u8 reggbthre; 946 947 __u16 regmaxcorv; 948 __u16 regmingradthr2; 949 __u16 regmingradthr1; 950 951 __u8 gr_ratio; 952 __u16 dnloscale; 953 __u16 dnhiscale; 954 __u8 reglumapointsstep; 955 956 __u16 gvaluelimitlo; 957 __u16 gvaluelimithi; 958 __u8 fusionratiohilimt1; 959 960 __u8 regstrength_fix; 961 962 __u16 sigma_y[ISP2X_GIC_SIGMA_Y_NUM]; 963 964 __u8 noise_cut_en; 965 __u16 noise_coe_a; 966 967 __u16 noise_coe_b; 968 __u16 diff_clip; 969 } __attribute__ ((packed)); 970 971 struct isp2x_debayer_cfg { 972 __u8 filter_c_en; 973 __u8 filter_g_en; 974 975 __u8 thed1; 976 __u8 thed0; 977 __u8 dist_scale; 978 __u8 max_ratio; 979 __u8 clip_en; 980 981 __s8 filter1_coe5; 982 __s8 filter1_coe4; 983 __s8 filter1_coe3; 984 __s8 filter1_coe2; 985 __s8 filter1_coe1; 986 987 __s8 filter2_coe5; 988 __s8 filter2_coe4; 989 __s8 filter2_coe3; 990 __s8 filter2_coe2; 991 __s8 filter2_coe1; 992 993 __u16 hf_offset; 994 __u8 gain_offset; 995 __u8 offset; 996 997 __u8 shift_num; 998 __u8 order_max; 999 __u8 order_min; 1000 } __attribute__ ((packed)); 1001 1002 struct isp2x_ccm_cfg { 1003 __s16 coeff0_r; 1004 __s16 coeff1_r; 1005 __s16 coeff2_r; 1006 __s16 offset_r; 1007 1008 __s16 coeff0_g; 1009 __s16 coeff1_g; 1010 __s16 coeff2_g; 1011 __s16 offset_g; 1012 1013 __s16 coeff0_b; 1014 __s16 coeff1_b; 1015 __s16 coeff2_b; 1016 __s16 offset_b; 1017 1018 __u16 coeff0_y; 1019 __u16 coeff1_y; 1020 __u16 coeff2_y; 1021 1022 __u16 alp_y[ISP2X_CCM_CURVE_NUM]; 1023 1024 __u8 bound_bit; 1025 } __attribute__ ((packed)); 1026 1027 struct isp2x_gammaout_cfg { 1028 __u8 equ_segm; 1029 __u16 offset; 1030 __u16 gamma_y[ISP2X_GAMMA_OUT_MAX_SAMPLES]; 1031 } __attribute__ ((packed)); 1032 1033 enum isp2x_wdr_mode { 1034 ISP2X_WDR_MODE_BLOCK, 1035 ISP2X_WDR_MODE_GLOBAL 1036 }; 1037 1038 struct isp2x_wdr_cfg { 1039 enum isp2x_wdr_mode mode; 1040 unsigned int c_wdr[ISP2X_WDR_SIZE]; 1041 } __attribute__ ((packed)); 1042 1043 struct isp2x_dhaz_cfg { 1044 __u8 enhance_en; 1045 __u8 hist_chn; 1046 __u8 hpara_en; 1047 __u8 hist_en; 1048 __u8 dc_en; 1049 __u8 big_en; 1050 __u8 nobig_en; 1051 1052 __u8 yblk_th; 1053 __u8 yhist_th; 1054 __u8 dc_max_th; 1055 __u8 dc_min_th; 1056 1057 __u16 wt_max; 1058 __u8 bright_max; 1059 __u8 bright_min; 1060 1061 __u8 tmax_base; 1062 __u8 dark_th; 1063 __u8 air_max; 1064 __u8 air_min; 1065 1066 __u16 tmax_max; 1067 __u16 tmax_off; 1068 1069 __u8 hist_th_off; 1070 __u8 hist_gratio; 1071 1072 __u16 hist_min; 1073 __u16 hist_k; 1074 1075 __u16 enhance_value; 1076 __u16 hist_scale; 1077 1078 __u16 iir_wt_sigma; 1079 __u16 iir_sigma; 1080 __u16 stab_fnum; 1081 1082 __u16 iir_tmax_sigma; 1083 __u16 iir_air_sigma; 1084 1085 __u16 cfg_wt; 1086 __u16 cfg_air; 1087 __u16 cfg_alpha; 1088 1089 __u16 cfg_gratio; 1090 __u16 cfg_tmax; 1091 1092 __u16 dc_weitcur; 1093 __u16 dc_thed; 1094 1095 __u8 sw_dhaz_dc_bf_h3; 1096 __u8 sw_dhaz_dc_bf_h2; 1097 __u8 sw_dhaz_dc_bf_h1; 1098 __u8 sw_dhaz_dc_bf_h0; 1099 1100 __u8 sw_dhaz_dc_bf_h5; 1101 __u8 sw_dhaz_dc_bf_h4; 1102 1103 __u16 air_weitcur; 1104 __u16 air_thed; 1105 1106 __u8 air_bf_h2; 1107 __u8 air_bf_h1; 1108 __u8 air_bf_h0; 1109 1110 __u8 gaus_h2; 1111 __u8 gaus_h1; 1112 __u8 gaus_h0; 1113 1114 __u8 conv_t0[ISP2X_DHAZ_CONV_COEFF_NUM]; 1115 __u8 conv_t1[ISP2X_DHAZ_CONV_COEFF_NUM]; 1116 __u8 conv_t2[ISP2X_DHAZ_CONV_COEFF_NUM]; 1117 } __attribute__ ((packed)); 1118 1119 struct isp2x_dhaz_stat { 1120 __u16 dhaz_adp_air_base; 1121 __u16 dhaz_adp_wt; 1122 1123 __u16 dhaz_adp_gratio; 1124 __u16 dhaz_adp_tmax; 1125 1126 __u16 h_r_iir[ISP2X_DHAZ_HIST_IIR_NUM]; 1127 __u16 h_g_iir[ISP2X_DHAZ_HIST_IIR_NUM]; 1128 __u16 h_b_iir[ISP2X_DHAZ_HIST_IIR_NUM]; 1129 } __attribute__ ((packed)); 1130 1131 struct isp2x_cproc_cfg { 1132 __u8 c_out_range; 1133 __u8 y_in_range; 1134 __u8 y_out_range; 1135 __u8 contrast; 1136 __u8 brightness; 1137 __u8 sat; 1138 __u8 hue; 1139 } __attribute__ ((packed)); 1140 1141 struct isp2x_ie_cfg { 1142 __u16 effect; 1143 __u16 color_sel; 1144 __u16 eff_mat_1; 1145 __u16 eff_mat_2; 1146 __u16 eff_mat_3; 1147 __u16 eff_mat_4; 1148 __u16 eff_mat_5; 1149 __u16 eff_tint; 1150 } __attribute__ ((packed)); 1151 1152 struct isp2x_rkiesharp_cfg { 1153 __u8 coring_thr; 1154 __u8 full_range; 1155 __u8 switch_avg; 1156 __u8 yavg_thr[4]; 1157 __u8 delta1[5]; 1158 __u8 delta2[5]; 1159 __u8 maxnumber[5]; 1160 __u8 minnumber[5]; 1161 __u8 gauss_flat_coe[9]; 1162 __u8 gauss_noise_coe[9]; 1163 __u8 gauss_other_coe[9]; 1164 __u8 line1_filter_coe[6]; 1165 __u8 line2_filter_coe[9]; 1166 __u8 line3_filter_coe[6]; 1167 __u16 grad_seq[4]; 1168 __u8 sharp_factor[5]; 1169 __u8 uv_gauss_flat_coe[15]; 1170 __u8 uv_gauss_noise_coe[15]; 1171 __u8 uv_gauss_other_coe[15]; 1172 __u8 lap_mat_coe[9]; 1173 } __attribute__ ((packed)); 1174 1175 struct isp2x_superimp_cfg { 1176 __u8 transparency_mode; 1177 __u8 ref_image; 1178 1179 __u16 offset_x; 1180 __u16 offset_y; 1181 1182 __u8 y_comp; 1183 __u8 cb_comp; 1184 __u8 cr_comp; 1185 } __attribute__ ((packed)); 1186 1187 struct isp2x_gamma_corr_curve { 1188 __u16 gamma_y[ISP2X_DEGAMMA_CURVE_SIZE]; 1189 } __attribute__ ((packed)); 1190 1191 struct isp2x_gamma_curve_x_axis_pnts { 1192 __u32 gamma_dx0; 1193 __u32 gamma_dx1; 1194 } __attribute__ ((packed)); 1195 1196 struct isp2x_sdg_cfg { 1197 struct isp2x_gamma_corr_curve curve_r; 1198 struct isp2x_gamma_corr_curve curve_g; 1199 struct isp2x_gamma_corr_curve curve_b; 1200 struct isp2x_gamma_curve_x_axis_pnts xa_pnts; 1201 } __attribute__ ((packed)); 1202 1203 struct isp2x_bdm_config { 1204 unsigned char demosaic_th; 1205 } __attribute__ ((packed)); 1206 1207 struct isp2x_gain_cfg { 1208 __u8 dhaz_en; 1209 __u8 wdr_en; 1210 __u8 tmo_en; 1211 __u8 lsc_en; 1212 __u8 mge_en; 1213 1214 __u32 mge_gain[ISP2X_GAIN_HDRMGE_GAIN_NUM]; 1215 __u16 idx[ISP2X_GAIN_IDX_NUM]; 1216 __u16 lut[ISP2X_GAIN_LUT_NUM]; 1217 } __attribute__ ((packed)); 1218 1219 struct isp2x_3dlut_cfg { 1220 __u8 bypass_en; 1221 __u32 actual_size; /* word unit */ 1222 __u16 lut_r[ISP2X_3DLUT_DATA_NUM]; 1223 __u16 lut_g[ISP2X_3DLUT_DATA_NUM]; 1224 __u16 lut_b[ISP2X_3DLUT_DATA_NUM]; 1225 } __attribute__ ((packed)); 1226 1227 enum isp2x_ldch_buf_stat { 1228 LDCH_BUF_INIT = 0, 1229 LDCH_BUF_WAIT2CHIP, 1230 LDCH_BUF_CHIPINUSE, 1231 }; 1232 1233 struct rkisp_ldchbuf_info { 1234 __s32 buf_fd[ISP2X_LDCH_BUF_NUM]; 1235 __u32 buf_size[ISP2X_LDCH_BUF_NUM]; 1236 } __attribute__ ((packed)); 1237 1238 struct rkisp_ldchbuf_size { 1239 __u32 meas_width; 1240 __u32 meas_height; 1241 } __attribute__ ((packed)); 1242 1243 struct isp2x_ldch_head { 1244 enum isp2x_ldch_buf_stat stat; 1245 __u32 data_oft; 1246 } __attribute__ ((packed)); 1247 1248 struct isp2x_ldch_cfg { 1249 __u32 hsize; 1250 __u32 vsize; 1251 __s32 buf_fd; 1252 } __attribute__ ((packed)); 1253 1254 struct isp2x_awb_gain_cfg { 1255 __u16 gain_red; 1256 __u16 gain_green_r; 1257 __u16 gain_blue; 1258 __u16 gain_green_b; 1259 } __attribute__ ((packed)); 1260 1261 struct isp2x_siawb_meas_cfg { 1262 struct isp2x_window awb_wnd; 1263 __u8 awb_mode; 1264 __u8 max_y; 1265 __u8 min_y; 1266 __u8 max_csum; 1267 __u8 min_c; 1268 __u8 frames; 1269 __u8 awb_ref_cr; 1270 __u8 awb_ref_cb; 1271 __u8 enable_ymax_cmp; 1272 } __attribute__ ((packed)); 1273 1274 struct isp2x_rawawb_meas_cfg { 1275 __u8 rawawb_sel; 1276 __u8 sw_rawawb_light_num; /* CTRL */ 1277 __u8 sw_rawawb_wind_size; /* CTRL */ 1278 __u8 sw_rawawb_c_range; /* CTRL */ 1279 __u8 sw_rawawb_y_range; /* CTRL */ 1280 __u8 sw_rawawb_3dyuv_ls_idx3; /* CTRL */ 1281 __u8 sw_rawawb_3dyuv_ls_idx2; /* CTRL */ 1282 __u8 sw_rawawb_3dyuv_ls_idx1; /* CTRL */ 1283 __u8 sw_rawawb_3dyuv_ls_idx0; /* CTRL */ 1284 __u8 sw_rawawb_xy_en; /* CTRL */ 1285 __u8 sw_rawawb_uv_en; /* CTRL */ 1286 __u8 sw_rawlsc_bypass_en; /* CTRL */ 1287 __u8 sw_rawawb_blk_measure_mode; /* BLK_CTRL */ 1288 __u8 sw_rawawb_store_wp_flag_ls_idx2; /* BLK_CTRL */ 1289 __u8 sw_rawawb_store_wp_flag_ls_idx1; /* BLK_CTRL */ 1290 __u8 sw_rawawb_store_wp_flag_ls_idx0; /* BLK_CTRL */ 1291 __u16 sw_rawawb_store_wp_th0; /* BLK_CTRL */ 1292 __u16 sw_rawawb_store_wp_th1; /* BLK_CTRL */ 1293 __u16 sw_rawawb_store_wp_th2; /* RAW_CTRL */ 1294 __u16 sw_rawawb_v_offs; /* WIN_OFFS */ 1295 __u16 sw_rawawb_h_offs; /* WIN_OFFS */ 1296 __u16 sw_rawawb_v_size; /* WIN_SIZE */ 1297 __u16 sw_rawawb_h_size; /* WIN_SIZE */ 1298 __u16 sw_rawawb_g_max; /* LIMIT_RG_MAX */ 1299 __u16 sw_rawawb_r_max; /* LIMIT_RG_MAX */ 1300 __u16 sw_rawawb_y_max; /* LIMIT_BY_MAX */ 1301 __u16 sw_rawawb_b_max; /* LIMIT_BY_MAX */ 1302 __u16 sw_rawawb_g_min; /* LIMIT_RG_MIN */ 1303 __u16 sw_rawawb_r_min; /* LIMIT_RG_MIN */ 1304 __u16 sw_rawawb_y_min; /* LIMIT_BY_MIN */ 1305 __u16 sw_rawawb_b_min; /* LIMIT_BY_MIN */ 1306 __u16 sw_rawawb_coeff_y_g; /* RGB2Y_0 */ 1307 __u16 sw_rawawb_coeff_y_r; /* RGB2Y_0 */ 1308 __u16 sw_rawawb_coeff_y_b; /* RGB2Y_1 */ 1309 __u16 sw_rawawb_coeff_u_g; /* RGB2U_0 */ 1310 __u16 sw_rawawb_coeff_u_r; /* RGB2U_0 */ 1311 __u16 sw_rawawb_coeff_u_b; /* RGB2U_1 */ 1312 __u16 sw_rawawb_coeff_v_g; /* RGB2V_0 */ 1313 __u16 sw_rawawb_coeff_v_r; /* RGB2V_0 */ 1314 __u16 sw_rawawb_coeff_v_b; /* RGB2V_1 */ 1315 __u16 sw_rawawb_vertex0_v_0; /* UV_DETC_VERTEX0_0 */ 1316 __u16 sw_rawawb_vertex0_u_0; /* UV_DETC_VERTEX0_0 */ 1317 __u16 sw_rawawb_vertex1_v_0; /* UV_DETC_VERTEX1_0 */ 1318 __u16 sw_rawawb_vertex1_u_0; /* UV_DETC_VERTEX1_0 */ 1319 __u16 sw_rawawb_vertex2_v_0; /* UV_DETC_VERTEX2_0 */ 1320 __u16 sw_rawawb_vertex2_u_0; /* UV_DETC_VERTEX2_0 */ 1321 __u16 sw_rawawb_vertex3_v_0; /* UV_DETC_VERTEX3_0 */ 1322 __u16 sw_rawawb_vertex3_u_0; /* UV_DETC_VERTEX3_0 */ 1323 __u32 sw_rawawb_islope01_0; /* UV_DETC_ISLOPE01_0 */ 1324 __u32 sw_rawawb_islope12_0; /* UV_DETC_ISLOPE12_0 */ 1325 __u32 sw_rawawb_islope23_0; /* UV_DETC_ISLOPE23_0 */ 1326 __u32 sw_rawawb_islope30_0; /* UV_DETC_ISLOPE30_0 */ 1327 __u16 sw_rawawb_vertex0_v_1; /* UV_DETC_VERTEX0_1 */ 1328 __u16 sw_rawawb_vertex0_u_1; /* UV_DETC_VERTEX0_1 */ 1329 __u16 sw_rawawb_vertex1_v_1; /* UV_DETC_VERTEX1_1 */ 1330 __u16 sw_rawawb_vertex1_u_1; /* UV_DETC_VERTEX1_1 */ 1331 __u16 sw_rawawb_vertex2_v_1; /* UV_DETC_VERTEX2_1 */ 1332 __u16 sw_rawawb_vertex2_u_1; /* UV_DETC_VERTEX2_1 */ 1333 __u16 sw_rawawb_vertex3_v_1; /* UV_DETC_VERTEX3_1 */ 1334 __u16 sw_rawawb_vertex3_u_1; /* UV_DETC_VERTEX3_1 */ 1335 __u32 sw_rawawb_islope01_1; /* UV_DETC_ISLOPE01_1 */ 1336 __u32 sw_rawawb_islope12_1; /* UV_DETC_ISLOPE12_1 */ 1337 __u32 sw_rawawb_islope23_1; /* UV_DETC_ISLOPE23_1 */ 1338 __u32 sw_rawawb_islope30_1; /* UV_DETC_ISLOPE30_1 */ 1339 __u16 sw_rawawb_vertex0_v_2; /* UV_DETC_VERTEX0_2 */ 1340 __u16 sw_rawawb_vertex0_u_2; /* UV_DETC_VERTEX0_2 */ 1341 __u16 sw_rawawb_vertex1_v_2; /* UV_DETC_VERTEX1_2 */ 1342 __u16 sw_rawawb_vertex1_u_2; /* UV_DETC_VERTEX1_2 */ 1343 __u16 sw_rawawb_vertex2_v_2; /* UV_DETC_VERTEX2_2 */ 1344 __u16 sw_rawawb_vertex2_u_2; /* UV_DETC_VERTEX2_2 */ 1345 __u16 sw_rawawb_vertex3_v_2; /* UV_DETC_VERTEX3_2 */ 1346 __u16 sw_rawawb_vertex3_u_2; /* UV_DETC_VERTEX3_2 */ 1347 __u32 sw_rawawb_islope01_2; /* UV_DETC_ISLOPE01_2 */ 1348 __u32 sw_rawawb_islope12_2; /* UV_DETC_ISLOPE12_2 */ 1349 __u32 sw_rawawb_islope23_2; /* UV_DETC_ISLOPE23_2 */ 1350 __u32 sw_rawawb_islope30_2; /* UV_DETC_ISLOPE30_2 */ 1351 __u16 sw_rawawb_vertex0_v_3; /* UV_DETC_VERTEX0_3 */ 1352 __u16 sw_rawawb_vertex0_u_3; /* UV_DETC_VERTEX0_3 */ 1353 __u16 sw_rawawb_vertex1_v_3; /* UV_DETC_VERTEX1_3 */ 1354 __u16 sw_rawawb_vertex1_u_3; /* UV_DETC_VERTEX1_3 */ 1355 __u16 sw_rawawb_vertex2_v_3; /* UV_DETC_VERTEX2_3 */ 1356 __u16 sw_rawawb_vertex2_u_3; /* UV_DETC_VERTEX2_3 */ 1357 __u16 sw_rawawb_vertex3_v_3; /* UV_DETC_VERTEX3_3 */ 1358 __u16 sw_rawawb_vertex3_u_3; /* UV_DETC_VERTEX3_3 */ 1359 __u32 sw_rawawb_islope01_3; /* UV_DETC_ISLOPE01_3 */ 1360 __u32 sw_rawawb_islope12_3; /* UV_DETC_ISLOPE12_3 */ 1361 __u32 sw_rawawb_islope23_3; /* UV_DETC_ISLOPE23_3 */ 1362 __u32 sw_rawawb_islope30_3; /* UV_DETC_ISLOPE30_3 */ 1363 __u16 sw_rawawb_vertex0_v_4; /* UV_DETC_VERTEX0_4 */ 1364 __u16 sw_rawawb_vertex0_u_4; /* UV_DETC_VERTEX0_4 */ 1365 __u16 sw_rawawb_vertex1_v_4; /* UV_DETC_VERTEX1_4 */ 1366 __u16 sw_rawawb_vertex1_u_4; /* UV_DETC_VERTEX1_4 */ 1367 __u16 sw_rawawb_vertex2_v_4; /* UV_DETC_VERTEX2_4 */ 1368 __u16 sw_rawawb_vertex2_u_4; /* UV_DETC_VERTEX2_4 */ 1369 __u16 sw_rawawb_vertex3_v_4; /* UV_DETC_VERTEX3_4 */ 1370 __u16 sw_rawawb_vertex3_u_4; /* UV_DETC_VERTEX3_4 */ 1371 __u32 sw_rawawb_islope01_4; /* UV_DETC_ISLOPE01_4 */ 1372 __u32 sw_rawawb_islope12_4; /* UV_DETC_ISLOPE12_4 */ 1373 __u32 sw_rawawb_islope23_4; /* UV_DETC_ISLOPE23_4 */ 1374 __u32 sw_rawawb_islope30_4; /* UV_DETC_ISLOPE30_4 */ 1375 __u16 sw_rawawb_vertex0_v_5; /* UV_DETC_VERTEX0_5 */ 1376 __u16 sw_rawawb_vertex0_u_5; /* UV_DETC_VERTEX0_5 */ 1377 __u16 sw_rawawb_vertex1_v_5; /* UV_DETC_VERTEX1_5 */ 1378 __u16 sw_rawawb_vertex1_u_5; /* UV_DETC_VERTEX1_5 */ 1379 __u16 sw_rawawb_vertex2_v_5; /* UV_DETC_VERTEX2_5 */ 1380 __u16 sw_rawawb_vertex2_u_5; /* UV_DETC_VERTEX2_5 */ 1381 __u16 sw_rawawb_vertex3_v_5; /* UV_DETC_VERTEX3_5 */ 1382 __u16 sw_rawawb_vertex3_u_5; /* UV_DETC_VERTEX3_5 */ 1383 __u32 sw_rawawb_islope01_5; /* UV_DETC_ISLOPE01_5 */ 1384 __u32 sw_rawawb_islope12_5; /* UV_DETC_ISLOPE10_5 */ 1385 __u32 sw_rawawb_islope23_5; /* UV_DETC_ISLOPE23_5 */ 1386 __u32 sw_rawawb_islope30_5; /* UV_DETC_ISLOPE30_5 */ 1387 __u16 sw_rawawb_vertex0_v_6; /* UV_DETC_VERTEX0_6 */ 1388 __u16 sw_rawawb_vertex0_u_6; /* UV_DETC_VERTEX0_6 */ 1389 __u16 sw_rawawb_vertex1_v_6; /* UV_DETC_VERTEX1_6 */ 1390 __u16 sw_rawawb_vertex1_u_6; /* UV_DETC_VERTEX1_6 */ 1391 __u16 sw_rawawb_vertex2_v_6; /* UV_DETC_VERTEX2_6 */ 1392 __u16 sw_rawawb_vertex2_u_6; /* UV_DETC_VERTEX2_6 */ 1393 __u16 sw_rawawb_vertex3_v_6; /* UV_DETC_VERTEX3_6 */ 1394 __u16 sw_rawawb_vertex3_u_6; /* UV_DETC_VERTEX3_6 */ 1395 __u32 sw_rawawb_islope01_6; /* UV_DETC_ISLOPE01_6 */ 1396 __u32 sw_rawawb_islope12_6; /* UV_DETC_ISLOPE10_6 */ 1397 __u32 sw_rawawb_islope23_6; /* UV_DETC_ISLOPE23_6 */ 1398 __u32 sw_rawawb_islope30_6; /* UV_DETC_ISLOPE30_6 */ 1399 __u32 sw_rawawb_b_uv_0; /* YUV_DETC_B_UV_0 */ 1400 __u32 sw_rawawb_slope_vtcuv_0; /* YUV_DETC_SLOPE_VTCUV_0 */ 1401 __u32 sw_rawawb_inv_dslope_0; /* YUV_DETC_INV_DSLOPE_0 */ 1402 __u32 sw_rawawb_slope_ydis_0; /* YUV_DETC_SLOPE_YDIS_0 */ 1403 __u32 sw_rawawb_b_ydis_0; /* YUV_DETC_B_YDIS_0 */ 1404 __u32 sw_rawawb_b_uv_1; /* YUV_DETC_B_UV_1 */ 1405 __u32 sw_rawawb_slope_vtcuv_1; /* YUV_DETC_SLOPE_VTCUV_1 */ 1406 __u32 sw_rawawb_inv_dslope_1; /* YUV_DETC_INV_DSLOPE_1 */ 1407 __u32 sw_rawawb_slope_ydis_1; /* YUV_DETC_SLOPE_YDIS_1 */ 1408 __u32 sw_rawawb_b_ydis_1; /* YUV_DETC_B_YDIS_1 */ 1409 __u32 sw_rawawb_b_uv_2; /* YUV_DETC_B_UV_2 */ 1410 __u32 sw_rawawb_slope_vtcuv_2; /* YUV_DETC_SLOPE_VTCUV_2 */ 1411 __u32 sw_rawawb_inv_dslope_2; /* YUV_DETC_INV_DSLOPE_2 */ 1412 __u32 sw_rawawb_slope_ydis_2; /* YUV_DETC_SLOPE_YDIS_2 */ 1413 __u32 sw_rawawb_b_ydis_2; /* YUV_DETC_B_YDIS_2 */ 1414 __u32 sw_rawawb_b_uv_3; /* YUV_DETC_B_UV_3 */ 1415 __u32 sw_rawawb_slope_vtcuv_3; /* YUV_DETC_SLOPE_VTCUV_3 */ 1416 __u32 sw_rawawb_inv_dslope_3; /* YUV_DETC_INV_DSLOPE_3 */ 1417 __u32 sw_rawawb_slope_ydis_3; /* YUV_DETC_SLOPE_YDIS_3 */ 1418 __u32 sw_rawawb_b_ydis_3; /* YUV_DETC_B_YDIS_3 */ 1419 __u32 sw_rawawb_ref_u; /* YUV_DETC_REF_U */ 1420 __u8 sw_rawawb_ref_v_3; /* YUV_DETC_REF_V_1 */ 1421 __u8 sw_rawawb_ref_v_2; /* YUV_DETC_REF_V_1 */ 1422 __u8 sw_rawawb_ref_v_1; /* YUV_DETC_REF_V_1 */ 1423 __u8 sw_rawawb_ref_v_0; /* YUV_DETC_REF_V_1 */ 1424 __u16 sw_rawawb_dis1_0; /* YUV_DETC_DIS01_0 */ 1425 __u16 sw_rawawb_dis0_0; /* YUV_DETC_DIS01_0 */ 1426 __u16 sw_rawawb_dis3_0; /* YUV_DETC_DIS23_0 */ 1427 __u16 sw_rawawb_dis2_0; /* YUV_DETC_DIS23_0 */ 1428 __u16 sw_rawawb_dis5_0; /* YUV_DETC_DIS45_0 */ 1429 __u16 sw_rawawb_dis4_0; /* YUV_DETC_DIS45_0 */ 1430 __u8 sw_rawawb_th3_0; /* YUV_DETC_TH03_0 */ 1431 __u8 sw_rawawb_th2_0; /* YUV_DETC_TH03_0 */ 1432 __u8 sw_rawawb_th1_0; /* YUV_DETC_TH03_0 */ 1433 __u8 sw_rawawb_th0_0; /* YUV_DETC_TH03_0 */ 1434 __u8 sw_rawawb_th5_0; /* YUV_DETC_TH45_0 */ 1435 __u8 sw_rawawb_th4_0; /* YUV_DETC_TH45_0 */ 1436 __u16 sw_rawawb_dis1_1; /* YUV_DETC_DIS01_1 */ 1437 __u16 sw_rawawb_dis0_1; /* YUV_DETC_DIS01_1 */ 1438 __u16 sw_rawawb_dis3_1; /* YUV_DETC_DIS23_1 */ 1439 __u16 sw_rawawb_dis2_1; /* YUV_DETC_DIS23_1 */ 1440 __u16 sw_rawawb_dis5_1; /* YUV_DETC_DIS45_1 */ 1441 __u16 sw_rawawb_dis4_1; /* YUV_DETC_DIS45_1 */ 1442 __u8 sw_rawawb_th3_1; /* YUV_DETC_TH03_1 */ 1443 __u8 sw_rawawb_th2_1; /* YUV_DETC_TH03_1 */ 1444 __u8 sw_rawawb_th1_1; /* YUV_DETC_TH03_1 */ 1445 __u8 sw_rawawb_th0_1; /* YUV_DETC_TH03_1 */ 1446 __u8 sw_rawawb_th5_1; /* YUV_DETC_TH45_1 */ 1447 __u8 sw_rawawb_th4_1; /* YUV_DETC_TH45_1 */ 1448 __u16 sw_rawawb_dis1_2; /* YUV_DETC_DIS01_2 */ 1449 __u16 sw_rawawb_dis0_2; /* YUV_DETC_DIS01_2 */ 1450 __u16 sw_rawawb_dis3_2; /* YUV_DETC_DIS23_2 */ 1451 __u16 sw_rawawb_dis2_2; /* YUV_DETC_DIS23_2 */ 1452 __u16 sw_rawawb_dis5_2; /* YUV_DETC_DIS45_2 */ 1453 __u16 sw_rawawb_dis4_2; /* YUV_DETC_DIS45_2 */ 1454 __u8 sw_rawawb_th3_2; /* YUV_DETC_TH03_2 */ 1455 __u8 sw_rawawb_th2_2; /* YUV_DETC_TH03_2 */ 1456 __u8 sw_rawawb_th1_2; /* YUV_DETC_TH03_2 */ 1457 __u8 sw_rawawb_th0_2; /* YUV_DETC_TH03_2 */ 1458 __u8 sw_rawawb_th5_2; /* YUV_DETC_TH45_2 */ 1459 __u8 sw_rawawb_th4_2; /* YUV_DETC_TH45_2 */ 1460 __u16 sw_rawawb_dis1_3; /* YUV_DETC_DIS01_3 */ 1461 __u16 sw_rawawb_dis0_3; /* YUV_DETC_DIS01_3 */ 1462 __u16 sw_rawawb_dis3_3; /* YUV_DETC_DIS23_3 */ 1463 __u16 sw_rawawb_dis2_3; /* YUV_DETC_DIS23_3 */ 1464 __u16 sw_rawawb_dis5_3; /* YUV_DETC_DIS45_3 */ 1465 __u16 sw_rawawb_dis4_3; /* YUV_DETC_DIS45_3 */ 1466 __u8 sw_rawawb_th3_3; /* YUV_DETC_TH03_3 */ 1467 __u8 sw_rawawb_th2_3; /* YUV_DETC_TH03_3 */ 1468 __u8 sw_rawawb_th1_3; /* YUV_DETC_TH03_3 */ 1469 __u8 sw_rawawb_th0_3; /* YUV_DETC_TH03_3 */ 1470 __u8 sw_rawawb_th5_3; /* YUV_DETC_TH45_3 */ 1471 __u8 sw_rawawb_th4_3; /* YUV_DETC_TH45_3 */ 1472 __u16 sw_rawawb_wt1; /* RGB2XY_WT01 */ 1473 __u16 sw_rawawb_wt0; /* RGB2XY_WT01 */ 1474 __u16 sw_rawawb_wt2; /* RGB2XY_WT2 */ 1475 __u16 sw_rawawb_mat0_y; /* RGB2XY_MAT0_XY */ 1476 __u16 sw_rawawb_mat0_x; /* RGB2XY_MAT0_XY */ 1477 __u16 sw_rawawb_mat1_y; /* RGB2XY_MAT1_XY */ 1478 __u16 sw_rawawb_mat1_x; /* RGB2XY_MAT1_XY */ 1479 __u16 sw_rawawb_mat2_y; /* RGB2XY_MAT2_XY */ 1480 __u16 sw_rawawb_mat2_x; /* RGB2XY_MAT2_XY */ 1481 __u16 sw_rawawb_nor_x1_0; /* XY_DETC_NOR_X_0 */ 1482 __u16 sw_rawawb_nor_x0_0; /* XY_DETC_NOR_X_0 */ 1483 __u16 sw_rawawb_nor_y1_0; /* XY_DETC_NOR_Y_0 */ 1484 __u16 sw_rawawb_nor_y0_0; /* XY_DETC_NOR_Y_0 */ 1485 __u16 sw_rawawb_big_x1_0; /* XY_DETC_BIG_X_0 */ 1486 __u16 sw_rawawb_big_x0_0; /* XY_DETC_BIG_X_0 */ 1487 __u16 sw_rawawb_big_y1_0; /* XY_DETC_BIG_Y_0 */ 1488 __u16 sw_rawawb_big_y0_0; /* XY_DETC_BIG_Y_0 */ 1489 __u16 sw_rawawb_sma_x1_0; /* XY_DETC_SMA_X_0 */ 1490 __u16 sw_rawawb_sma_x0_0; /* XY_DETC_SMA_X_0 */ 1491 __u16 sw_rawawb_sma_y1_0; /* XY_DETC_SMA_Y_0 */ 1492 __u16 sw_rawawb_sma_y0_0; /* XY_DETC_SMA_Y_0 */ 1493 __u16 sw_rawawb_nor_x1_1; /* XY_DETC_NOR_X_1 */ 1494 __u16 sw_rawawb_nor_x0_1; /* XY_DETC_NOR_X_1 */ 1495 __u16 sw_rawawb_nor_y1_1; /* XY_DETC_NOR_Y_1 */ 1496 __u16 sw_rawawb_nor_y0_1; /* XY_DETC_NOR_Y_1 */ 1497 __u16 sw_rawawb_big_x1_1; /* XY_DETC_BIG_X_1 */ 1498 __u16 sw_rawawb_big_x0_1; /* XY_DETC_BIG_X_1 */ 1499 __u16 sw_rawawb_big_y1_1; /* XY_DETC_BIG_Y_1 */ 1500 __u16 sw_rawawb_big_y0_1; /* XY_DETC_BIG_Y_1 */ 1501 __u16 sw_rawawb_sma_x1_1; /* XY_DETC_SMA_X_1 */ 1502 __u16 sw_rawawb_sma_x0_1; /* XY_DETC_SMA_X_1 */ 1503 __u16 sw_rawawb_sma_y1_1; /* XY_DETC_SMA_Y_1 */ 1504 __u16 sw_rawawb_sma_y0_1; /* XY_DETC_SMA_Y_1 */ 1505 __u16 sw_rawawb_nor_x1_2; /* XY_DETC_NOR_X_2 */ 1506 __u16 sw_rawawb_nor_x0_2; /* XY_DETC_NOR_X_2 */ 1507 __u16 sw_rawawb_nor_y1_2; /* XY_DETC_NOR_Y_2 */ 1508 __u16 sw_rawawb_nor_y0_2; /* XY_DETC_NOR_Y_2 */ 1509 __u16 sw_rawawb_big_x1_2; /* XY_DETC_BIG_X_2 */ 1510 __u16 sw_rawawb_big_x0_2; /* XY_DETC_BIG_X_2 */ 1511 __u16 sw_rawawb_big_y1_2; /* XY_DETC_BIG_Y_2 */ 1512 __u16 sw_rawawb_big_y0_2; /* XY_DETC_BIG_Y_2 */ 1513 __u16 sw_rawawb_sma_x1_2; /* XY_DETC_SMA_X_2 */ 1514 __u16 sw_rawawb_sma_x0_2; /* XY_DETC_SMA_X_2 */ 1515 __u16 sw_rawawb_sma_y1_2; /* XY_DETC_SMA_Y_2 */ 1516 __u16 sw_rawawb_sma_y0_2; /* XY_DETC_SMA_Y_2 */ 1517 __u16 sw_rawawb_nor_x1_3; /* XY_DETC_NOR_X_3 */ 1518 __u16 sw_rawawb_nor_x0_3; /* XY_DETC_NOR_X_3 */ 1519 __u16 sw_rawawb_nor_y1_3; /* XY_DETC_NOR_Y_3 */ 1520 __u16 sw_rawawb_nor_y0_3; /* XY_DETC_NOR_Y_3 */ 1521 __u16 sw_rawawb_big_x1_3; /* XY_DETC_BIG_X_3 */ 1522 __u16 sw_rawawb_big_x0_3; /* XY_DETC_BIG_X_3 */ 1523 __u16 sw_rawawb_big_y1_3; /* XY_DETC_BIG_Y_3 */ 1524 __u16 sw_rawawb_big_y0_3; /* XY_DETC_BIG_Y_3 */ 1525 __u16 sw_rawawb_sma_x1_3; /* XY_DETC_SMA_X_3 */ 1526 __u16 sw_rawawb_sma_x0_3; /* XY_DETC_SMA_X_3 */ 1527 __u16 sw_rawawb_sma_y1_3; /* XY_DETC_SMA_Y_3 */ 1528 __u16 sw_rawawb_sma_y0_3; /* XY_DETC_SMA_Y_3 */ 1529 __u16 sw_rawawb_nor_x1_4; /* XY_DETC_NOR_X_4 */ 1530 __u16 sw_rawawb_nor_x0_4; /* XY_DETC_NOR_X_4 */ 1531 __u16 sw_rawawb_nor_y1_4; /* XY_DETC_NOR_Y_4 */ 1532 __u16 sw_rawawb_nor_y0_4; /* XY_DETC_NOR_Y_4 */ 1533 __u16 sw_rawawb_big_x1_4; /* XY_DETC_BIG_X_4 */ 1534 __u16 sw_rawawb_big_x0_4; /* XY_DETC_BIG_X_4 */ 1535 __u16 sw_rawawb_big_y1_4; /* XY_DETC_BIG_Y_4 */ 1536 __u16 sw_rawawb_big_y0_4; /* XY_DETC_BIG_Y_4 */ 1537 __u16 sw_rawawb_sma_x1_4; /* XY_DETC_SMA_X_4 */ 1538 __u16 sw_rawawb_sma_x0_4; /* XY_DETC_SMA_X_4 */ 1539 __u16 sw_rawawb_sma_y1_4; /* XY_DETC_SMA_Y_4 */ 1540 __u16 sw_rawawb_sma_y0_4; /* XY_DETC_SMA_Y_4 */ 1541 __u16 sw_rawawb_nor_x1_5; /* XY_DETC_NOR_X_5 */ 1542 __u16 sw_rawawb_nor_x0_5; /* XY_DETC_NOR_X_5 */ 1543 __u16 sw_rawawb_nor_y1_5; /* XY_DETC_NOR_Y_5 */ 1544 __u16 sw_rawawb_nor_y0_5; /* XY_DETC_NOR_Y_5 */ 1545 __u16 sw_rawawb_big_x1_5; /* XY_DETC_BIG_X_5 */ 1546 __u16 sw_rawawb_big_x0_5; /* XY_DETC_BIG_X_5 */ 1547 __u16 sw_rawawb_big_y1_5; /* XY_DETC_BIG_Y_5 */ 1548 __u16 sw_rawawb_big_y0_5; /* XY_DETC_BIG_Y_5 */ 1549 __u16 sw_rawawb_sma_x1_5; /* XY_DETC_SMA_X_5 */ 1550 __u16 sw_rawawb_sma_x0_5; /* XY_DETC_SMA_X_5 */ 1551 __u16 sw_rawawb_sma_y1_5; /* XY_DETC_SMA_Y_5 */ 1552 __u16 sw_rawawb_sma_y0_5; /* XY_DETC_SMA_Y_5 */ 1553 __u16 sw_rawawb_nor_x1_6; /* XY_DETC_NOR_X_6 */ 1554 __u16 sw_rawawb_nor_x0_6; /* XY_DETC_NOR_X_6 */ 1555 __u16 sw_rawawb_nor_y1_6; /* XY_DETC_NOR_Y_6 */ 1556 __u16 sw_rawawb_nor_y0_6; /* XY_DETC_NOR_Y_6 */ 1557 __u16 sw_rawawb_big_x1_6; /* XY_DETC_BIG_X_6 */ 1558 __u16 sw_rawawb_big_x0_6; /* XY_DETC_BIG_X_6 */ 1559 __u16 sw_rawawb_big_y1_6; /* XY_DETC_BIG_Y_6 */ 1560 __u16 sw_rawawb_big_y0_6; /* XY_DETC_BIG_Y_6 */ 1561 __u16 sw_rawawb_sma_x1_6; /* XY_DETC_SMA_X_6 */ 1562 __u16 sw_rawawb_sma_x0_6; /* XY_DETC_SMA_X_6 */ 1563 __u16 sw_rawawb_sma_y1_6; /* XY_DETC_SMA_Y_6 */ 1564 __u16 sw_rawawb_sma_y0_6; /* XY_DETC_SMA_Y_6 */ 1565 __u8 sw_rawawb_multiwindow_en; /* MULTIWINDOW_EXC_CTRL */ 1566 __u8 sw_rawawb_exc_wp_region6_domain; /* MULTIWINDOW_EXC_CTRL */ 1567 __u8 sw_rawawb_exc_wp_region6_measen; /* MULTIWINDOW_EXC_CTRL */ 1568 __u8 sw_rawawb_exc_wp_region6_excen; /* MULTIWINDOW_EXC_CTRL */ 1569 __u8 sw_rawawb_exc_wp_region5_domain; /* MULTIWINDOW_EXC_CTRL */ 1570 __u8 sw_rawawb_exc_wp_region5_measen; /* MULTIWINDOW_EXC_CTRL */ 1571 __u8 sw_rawawb_exc_wp_region5_excen; /* MULTIWINDOW_EXC_CTRL */ 1572 __u8 sw_rawawb_exc_wp_region4_domain; /* MULTIWINDOW_EXC_CTRL */ 1573 __u8 sw_rawawb_exc_wp_region4_measen; /* MULTIWINDOW_EXC_CTRL */ 1574 __u8 sw_rawawb_exc_wp_region4_excen; /* MULTIWINDOW_EXC_CTRL */ 1575 __u8 sw_rawawb_exc_wp_region3_domain; /* MULTIWINDOW_EXC_CTRL */ 1576 __u8 sw_rawawb_exc_wp_region3_measen; /* MULTIWINDOW_EXC_CTRL */ 1577 __u8 sw_rawawb_exc_wp_region3_excen; /* MULTIWINDOW_EXC_CTRL */ 1578 __u8 sw_rawawb_exc_wp_region2_domain; /* MULTIWINDOW_EXC_CTRL */ 1579 __u8 sw_rawawb_exc_wp_region2_measen; /* MULTIWINDOW_EXC_CTRL */ 1580 __u8 sw_rawawb_exc_wp_region2_excen; /* MULTIWINDOW_EXC_CTRL */ 1581 __u8 sw_rawawb_exc_wp_region1_domain; /* MULTIWINDOW_EXC_CTRL */ 1582 __u8 sw_rawawb_exc_wp_region1_measen; /* MULTIWINDOW_EXC_CTRL */ 1583 __u8 sw_rawawb_exc_wp_region1_excen; /* MULTIWINDOW_EXC_CTRL */ 1584 __u8 sw_rawawb_exc_wp_region0_domain; /* MULTIWINDOW_EXC_CTRL */ 1585 __u8 sw_rawawb_exc_wp_region0_measen; /* MULTIWINDOW_EXC_CTRL */ 1586 __u8 sw_rawawb_exc_wp_region0_excen; /* MULTIWINDOW_EXC_CTRL */ 1587 __u16 sw_rawawb_multiwindow0_v_offs; /* MULTIWINDOW0_OFFS */ 1588 __u16 sw_rawawb_multiwindow0_h_offs; /* MULTIWINDOW0_OFFS */ 1589 __u16 sw_rawawb_multiwindow0_v_size; /* MULTIWINDOW0_SIZE */ 1590 __u16 sw_rawawb_multiwindow0_h_size; /* MULTIWINDOW0_SIZE */ 1591 __u16 sw_rawawb_multiwindow1_v_offs; /* MULTIWINDOW1_OFFS */ 1592 __u16 sw_rawawb_multiwindow1_h_offs; /* MULTIWINDOW1_OFFS */ 1593 __u16 sw_rawawb_multiwindow1_v_size; /* MULTIWINDOW1_SIZE */ 1594 __u16 sw_rawawb_multiwindow1_h_size; /* MULTIWINDOW1_SIZE */ 1595 __u16 sw_rawawb_multiwindow2_v_offs; /* MULTIWINDOW2_OFFS */ 1596 __u16 sw_rawawb_multiwindow2_h_offs; /* MULTIWINDOW2_OFFS */ 1597 __u16 sw_rawawb_multiwindow2_v_size; /* MULTIWINDOW2_SIZE */ 1598 __u16 sw_rawawb_multiwindow2_h_size; /* MULTIWINDOW2_SIZE */ 1599 __u16 sw_rawawb_multiwindow3_v_offs; /* MULTIWINDOW3_OFFS */ 1600 __u16 sw_rawawb_multiwindow3_h_offs; /* MULTIWINDOW3_OFFS */ 1601 __u16 sw_rawawb_multiwindow3_v_size; /* MULTIWINDOW3_SIZE */ 1602 __u16 sw_rawawb_multiwindow3_h_size; /* MULTIWINDOW3_SIZE */ 1603 __u16 sw_rawawb_multiwindow4_v_offs; /* MULTIWINDOW4_OFFS */ 1604 __u16 sw_rawawb_multiwindow4_h_offs; /* MULTIWINDOW4_OFFS */ 1605 __u16 sw_rawawb_multiwindow4_v_size; /* MULTIWINDOW4_SIZE */ 1606 __u16 sw_rawawb_multiwindow4_h_size; /* MULTIWINDOW4_SIZE */ 1607 __u16 sw_rawawb_multiwindow5_v_offs; /* MULTIWINDOW5_OFFS */ 1608 __u16 sw_rawawb_multiwindow5_h_offs; /* MULTIWINDOW5_OFFS */ 1609 __u16 sw_rawawb_multiwindow5_v_size; /* MULTIWINDOW5_SIZE */ 1610 __u16 sw_rawawb_multiwindow5_h_size; /* MULTIWINDOW5_SIZE */ 1611 __u16 sw_rawawb_multiwindow6_v_offs; /* MULTIWINDOW6_OFFS */ 1612 __u16 sw_rawawb_multiwindow6_h_offs; /* MULTIWINDOW6_OFFS */ 1613 __u16 sw_rawawb_multiwindow6_v_size; /* MULTIWINDOW6_SIZE */ 1614 __u16 sw_rawawb_multiwindow6_h_size; /* MULTIWINDOW6_SIZE */ 1615 __u16 sw_rawawb_multiwindow7_v_offs; /* MULTIWINDOW7_OFFS */ 1616 __u16 sw_rawawb_multiwindow7_h_offs; /* MULTIWINDOW7_OFFS */ 1617 __u16 sw_rawawb_multiwindow7_v_size; /* MULTIWINDOW7_SIZE */ 1618 __u16 sw_rawawb_multiwindow7_h_size; /* MULTIWINDOW7_SIZE */ 1619 __u16 sw_rawawb_exc_wp_region0_xu1; /* EXC_WP_REGION0_XU */ 1620 __u16 sw_rawawb_exc_wp_region0_xu0; /* EXC_WP_REGION0_XU */ 1621 __u16 sw_rawawb_exc_wp_region0_yv1; /* EXC_WP_REGION0_YV */ 1622 __u16 sw_rawawb_exc_wp_region0_yv0; /* EXC_WP_REGION0_YV */ 1623 __u16 sw_rawawb_exc_wp_region1_xu1; /* EXC_WP_REGION1_XU */ 1624 __u16 sw_rawawb_exc_wp_region1_xu0; /* EXC_WP_REGION1_XU */ 1625 __u16 sw_rawawb_exc_wp_region1_yv1; /* EXC_WP_REGION1_YV */ 1626 __u16 sw_rawawb_exc_wp_region1_yv0; /* EXC_WP_REGION1_YV */ 1627 __u16 sw_rawawb_exc_wp_region2_xu1; /* EXC_WP_REGION2_XU */ 1628 __u16 sw_rawawb_exc_wp_region2_xu0; /* EXC_WP_REGION2_XU */ 1629 __u16 sw_rawawb_exc_wp_region2_yv1; /* EXC_WP_REGION2_YV */ 1630 __u16 sw_rawawb_exc_wp_region2_yv0; /* EXC_WP_REGION2_YV */ 1631 __u16 sw_rawawb_exc_wp_region3_xu1; /* EXC_WP_REGION3_XU */ 1632 __u16 sw_rawawb_exc_wp_region3_xu0; /* EXC_WP_REGION3_XU */ 1633 __u16 sw_rawawb_exc_wp_region3_yv1; /* EXC_WP_REGION3_YV */ 1634 __u16 sw_rawawb_exc_wp_region3_yv0; /* EXC_WP_REGION3_YV */ 1635 __u16 sw_rawawb_exc_wp_region4_xu1; /* EXC_WP_REGION4_XU */ 1636 __u16 sw_rawawb_exc_wp_region4_xu0; /* EXC_WP_REGION4_XU */ 1637 __u16 sw_rawawb_exc_wp_region4_yv1; /* EXC_WP_REGION4_YV */ 1638 __u16 sw_rawawb_exc_wp_region4_yv0; /* EXC_WP_REGION4_YV */ 1639 __u16 sw_rawawb_exc_wp_region5_xu1; /* EXC_WP_REGION5_XU */ 1640 __u16 sw_rawawb_exc_wp_region5_xu0; /* EXC_WP_REGION5_XU */ 1641 __u16 sw_rawawb_exc_wp_region5_yv1; /* EXC_WP_REGION5_YV */ 1642 __u16 sw_rawawb_exc_wp_region5_yv0; /* EXC_WP_REGION5_YV */ 1643 __u16 sw_rawawb_exc_wp_region6_xu1; /* EXC_WP_REGION6_XU */ 1644 __u16 sw_rawawb_exc_wp_region6_xu0; /* EXC_WP_REGION6_XU */ 1645 __u16 sw_rawawb_exc_wp_region6_yv1; /* EXC_WP_REGION6_YV */ 1646 __u16 sw_rawawb_exc_wp_region6_yv0; /* EXC_WP_REGION6_YV */ 1647 } __attribute__ ((packed)); 1648 1649 struct isp2x_rawaebig_meas_cfg { 1650 __u8 rawae_sel; 1651 __u8 wnd_num; 1652 __u8 subwin_en[ISP2X_RAWAEBIG_SUBWIN_NUM]; 1653 struct isp2x_window win; 1654 struct isp2x_window subwin[ISP2X_RAWAEBIG_SUBWIN_NUM]; 1655 } __attribute__ ((packed)); 1656 1657 struct isp2x_rawaelite_meas_cfg { 1658 __u8 rawae_sel; 1659 __u8 wnd_num; 1660 struct isp2x_window win; 1661 } __attribute__ ((packed)); 1662 1663 struct isp2x_yuvae_meas_cfg { 1664 __u8 ysel; 1665 __u8 wnd_num; 1666 __u8 subwin_en[ISP2X_YUVAE_SUBWIN_NUM]; 1667 struct isp2x_window win; 1668 struct isp2x_window subwin[ISP2X_YUVAE_SUBWIN_NUM]; 1669 } __attribute__ ((packed)); 1670 1671 struct isp2x_rawaf_meas_cfg { 1672 __u8 rawaf_sel; 1673 __u8 num_afm_win; 1674 __u8 gaus_en; 1675 __u8 gamma_en; 1676 struct isp2x_window win[ISP2X_RAWAF_WIN_NUM]; 1677 __u8 line_en[ISP2X_RAWAF_LINE_NUM]; 1678 __u8 line_num[ISP2X_RAWAF_LINE_NUM]; 1679 __u8 gaus_coe_h2; 1680 __u8 gaus_coe_h1; 1681 __u8 gaus_coe_h0; 1682 __u16 afm_thres; 1683 __u8 lum_var_shift[ISP2X_RAWAF_WIN_NUM]; 1684 __u8 afm_var_shift[ISP2X_RAWAF_WIN_NUM]; 1685 __u16 gamma_y[ISP2X_RAWAF_GAMMA_NUM]; 1686 } __attribute__ ((packed)); 1687 1688 struct isp2x_siaf_win_cfg { 1689 __u8 sum_shift; 1690 __u8 lum_shift; 1691 struct isp2x_window win; 1692 } __attribute__ ((packed)); 1693 1694 struct isp2x_siaf_cfg { 1695 __u8 num_afm_win; 1696 __u32 thres; 1697 struct isp2x_siaf_win_cfg afm_win[ISP2X_AFM_MAX_WINDOWS]; 1698 } __attribute__ ((packed)); 1699 1700 struct isp2x_rawhistbig_cfg { 1701 __u8 wnd_num; 1702 __u8 data_sel; 1703 __u8 waterline; 1704 __u8 mode; 1705 __u8 stepsize; 1706 __u8 off; 1707 __u8 bcc; 1708 __u8 gcc; 1709 __u8 rcc; 1710 struct isp2x_window win; 1711 __u8 weight[ISP2X_RAWHISTBIG_SUBWIN_NUM]; 1712 } __attribute__ ((packed)); 1713 1714 struct isp2x_rawhistlite_cfg { 1715 __u8 data_sel; 1716 __u8 waterline; 1717 __u8 mode; 1718 __u8 stepsize; 1719 __u8 off; 1720 __u8 bcc; 1721 __u8 gcc; 1722 __u8 rcc; 1723 struct isp2x_window win; 1724 __u8 weight[ISP2X_RAWHISTLITE_SUBWIN_NUM]; 1725 } __attribute__ ((packed)); 1726 1727 struct isp2x_sihst_win_cfg { 1728 __u8 data_sel; 1729 __u8 waterline; 1730 __u8 auto_stop; 1731 __u8 mode; 1732 __u8 stepsize; 1733 struct isp2x_window win; 1734 } __attribute__ ((packed)); 1735 1736 struct isp2x_sihst_cfg { 1737 __u8 wnd_num; 1738 struct isp2x_sihst_win_cfg win_cfg[ISP2X_SIHIST_WIN_NUM]; 1739 __u8 hist_weight[ISP2X_HIST_WEIGHT_NUM]; 1740 } __attribute__ ((packed)); 1741 1742 struct isp2x_isp_other_cfg { 1743 struct isp2x_bls_cfg bls_cfg; 1744 struct isp2x_dpcc_cfg dpcc_cfg; 1745 struct isp2x_hdrmge_cfg hdrmge_cfg; 1746 struct isp2x_rawnr_cfg rawnr_cfg; 1747 struct isp2x_lsc_cfg lsc_cfg; 1748 struct isp2x_awb_gain_cfg awb_gain_cfg; 1749 /* struct isp2x_goc_cfg goc_cfg; */ 1750 struct isp2x_gic_cfg gic_cfg; 1751 struct isp2x_debayer_cfg debayer_cfg; 1752 struct isp2x_ccm_cfg ccm_cfg; 1753 struct isp2x_gammaout_cfg gammaout_cfg; 1754 struct isp2x_wdr_cfg wdr_cfg; 1755 struct isp2x_cproc_cfg cproc_cfg; 1756 struct isp2x_ie_cfg ie_cfg; 1757 struct isp2x_rkiesharp_cfg rkiesharp_cfg; 1758 struct isp2x_superimp_cfg superimp_cfg; 1759 struct isp2x_sdg_cfg sdg_cfg; 1760 struct isp2x_bdm_config bdm_cfg; 1761 struct isp2x_hdrtmo_cfg hdrtmo_cfg; 1762 struct isp2x_dhaz_cfg dhaz_cfg; 1763 struct isp2x_gain_cfg gain_cfg; 1764 struct isp2x_3dlut_cfg isp3dlut_cfg; 1765 struct isp2x_ldch_cfg ldch_cfg; 1766 } __attribute__ ((packed)); 1767 1768 struct isp2x_isp_meas_cfg { 1769 struct isp2x_siawb_meas_cfg siawb; 1770 struct isp2x_rawawb_meas_cfg rawawb; 1771 struct isp2x_rawaelite_meas_cfg rawae0; 1772 struct isp2x_rawaebig_meas_cfg rawae1; 1773 struct isp2x_rawaebig_meas_cfg rawae2; 1774 struct isp2x_rawaebig_meas_cfg rawae3; 1775 struct isp2x_yuvae_meas_cfg yuvae; 1776 struct isp2x_rawaf_meas_cfg rawaf; 1777 struct isp2x_siaf_cfg siaf; 1778 struct isp2x_rawhistlite_cfg rawhist0; 1779 struct isp2x_rawhistbig_cfg rawhist1; 1780 struct isp2x_rawhistbig_cfg rawhist2; 1781 struct isp2x_rawhistbig_cfg rawhist3; 1782 struct isp2x_sihst_cfg sihst; 1783 } __attribute__ ((packed)); 1784 1785 struct sensor_exposure_s { 1786 __u32 fine_integration_time; 1787 __u32 coarse_integration_time; 1788 __u32 analog_gain_code_global; 1789 __u32 digital_gain_global; 1790 __u32 isp_digital_gain; 1791 } __attribute__ ((packed)); 1792 1793 struct sensor_exposure_cfg { 1794 struct sensor_exposure_s linear_exp; 1795 struct sensor_exposure_s hdr_exp[3]; 1796 } __attribute__ ((packed)); 1797 1798 struct isp2x_isp_params_cfg { 1799 __u64 module_en_update; 1800 __u64 module_ens; 1801 __u64 module_cfg_update; 1802 1803 __u32 frame_id; 1804 struct isp2x_isp_meas_cfg meas; 1805 struct isp2x_isp_other_cfg others; 1806 struct sensor_exposure_cfg exposure; 1807 } __attribute__ ((packed)); 1808 1809 struct isp2x_siawb_meas { 1810 __u32 cnt; 1811 __u8 mean_y_or_g; 1812 __u8 mean_cb_or_b; 1813 __u8 mean_cr_or_r; 1814 } __attribute__ ((packed)); 1815 1816 struct isp2x_siawb_stat { 1817 struct isp2x_siawb_meas awb_mean[ISP2X_AWB_MAX_GRID]; 1818 } __attribute__ ((packed)); 1819 1820 struct isp2x_rawawb_ramdata { 1821 __u32 wp; 1822 __u32 r; 1823 __u32 g; 1824 __u32 b; 1825 }; 1826 1827 struct isp2x_rawawb_meas_stat { 1828 __u32 ro_rawawb_sum_r_nor[ISP2X_RAWAWB_SUM_NUM]; /* SUM_R_NOR_0 */ 1829 __u32 ro_rawawb_sum_g_nor[ISP2X_RAWAWB_SUM_NUM]; /* SUM_G_NOR_0 */ 1830 __u32 ro_rawawb_sum_b_nor[ISP2X_RAWAWB_SUM_NUM]; /* SUM_B_NOR_0 */ 1831 __u32 ro_rawawb_wp_num_nor[ISP2X_RAWAWB_SUM_NUM]; /* WP_NUM_NOR_0 */ 1832 __u32 ro_rawawb_sum_r_big[ISP2X_RAWAWB_SUM_NUM]; /* SUM_R_BIG_0 */ 1833 __u32 ro_rawawb_sum_g_big[ISP2X_RAWAWB_SUM_NUM]; /* SUM_G_BIG_0 */ 1834 __u32 ro_rawawb_sum_b_big[ISP2X_RAWAWB_SUM_NUM]; /* SUM_B_BIG_0 */ 1835 __u32 ro_rawawb_wp_num_big[ISP2X_RAWAWB_SUM_NUM]; /* WP_NUM_BIG_0 */ 1836 __u32 ro_rawawb_sum_r_sma[ISP2X_RAWAWB_SUM_NUM]; /* SUM_R_SMA_0 */ 1837 __u32 ro_rawawb_sum_g_sma[ISP2X_RAWAWB_SUM_NUM]; /* SUM_G_SMA_0 */ 1838 __u32 ro_rawawb_sum_b_sma[ISP2X_RAWAWB_SUM_NUM]; /* SUM_B_SMA_0 */ 1839 __u32 ro_rawawb_wp_num_sma[ISP2X_RAWAWB_SUM_NUM]; 1840 __u32 ro_sum_r_nor_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; /* SUM_R_NOR_MULTIWINDOW_0 */ 1841 __u32 ro_sum_g_nor_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; /* SUM_G_NOR_MULTIWINDOW_0 */ 1842 __u32 ro_sum_b_nor_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; /* SUM_B_NOR_MULTIWINDOW_0 */ 1843 __u32 ro_wp_nm_nor_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; /* WP_NM_NOR_MULTIWINDOW_0 */ 1844 __u32 ro_sum_r_big_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; /* SUM_R_BIG_MULTIWINDOW_0 */ 1845 __u32 ro_sum_g_big_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; /* SUM_G_BIG_MULTIWINDOW_0 */ 1846 __u32 ro_sum_b_big_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; /* SUM_B_BIG_MULTIWINDOW_0 */ 1847 __u32 ro_wp_nm_big_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; /* WP_NM_BIG_MULTIWINDOW_0 */ 1848 __u32 ro_sum_r_sma_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; /* SUM_R_SMA_MULTIWINDOW_0 */ 1849 __u32 ro_sum_g_sma_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; /* SUM_G_SMA_MULTIWINDOW_0 */ 1850 __u32 ro_sum_b_sma_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; /* SUM_B_SMA_MULTIWINDOW_0 */ 1851 __u32 ro_wp_nm_sma_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; /* WP_NM_SMA_MULTIWINDOW_0 */ 1852 __u32 ro_sum_r_exc[ISP2X_RAWAWB_SUM_NUM]; 1853 __u32 ro_sum_g_exc[ISP2X_RAWAWB_SUM_NUM]; 1854 __u32 ro_sum_b_exc[ISP2X_RAWAWB_SUM_NUM]; 1855 __u32 ro_wp_nm_exc[ISP2X_RAWAWB_SUM_NUM]; 1856 struct isp2x_rawawb_ramdata ramdata[ISP2X_RAWAWB_RAMDATA_NUM]; 1857 } __attribute__ ((packed)); 1858 1859 struct isp2x_rawae_meas_data { 1860 __u16 channelr_xy; 1861 __u16 channelb_xy; 1862 __u16 channelg_xy; 1863 }; 1864 1865 struct isp2x_rawaebig_stat { 1866 __u32 sumr[ISP2X_RAWAEBIG_SUBWIN_NUM]; 1867 __u32 sumg[ISP2X_RAWAEBIG_SUBWIN_NUM]; 1868 __u32 sumb[ISP2X_RAWAEBIG_SUBWIN_NUM]; 1869 struct isp2x_rawae_meas_data data[ISP2X_RAWAEBIG_MEAN_NUM]; 1870 } __attribute__ ((packed)); 1871 1872 struct isp2x_rawaelite_stat { 1873 struct isp2x_rawae_meas_data data[ISP2X_RAWAELITE_MEAN_NUM]; 1874 } __attribute__ ((packed)); 1875 1876 struct isp2x_yuvae_stat { 1877 __u32 ro_yuvae_sumy[ISP2X_YUVAE_SUBWIN_NUM]; 1878 __u8 mean[ISP2X_YUVAE_MEAN_NUM]; 1879 } __attribute__ ((packed)); 1880 1881 struct isp2x_rawaf_stat { 1882 __u32 int_state; 1883 __u32 afm_sum[ISP2X_RAWAF_WIN_NUM]; 1884 __u32 afm_lum[ISP2X_RAWAF_WIN_NUM]; 1885 __u32 ramdata[ISP2X_RAWAF_SUMDATA_NUM]; 1886 } __attribute__ ((packed)); 1887 1888 struct isp2x_siaf_meas_val { 1889 __u32 sum; 1890 __u32 lum; 1891 } __attribute__ ((packed)); 1892 1893 struct isp2x_siaf_stat { 1894 struct isp2x_siaf_meas_val win[ISP2X_AFM_MAX_WINDOWS]; 1895 } __attribute__ ((packed)); 1896 1897 struct isp2x_rawhistbig_stat { 1898 __u32 hist_bin[ISP2X_HIST_BIN_N_MAX]; 1899 } __attribute__ ((packed)); 1900 1901 struct isp2x_rawhistlite_stat { 1902 __u32 hist_bin[ISP2X_HIST_BIN_N_MAX]; 1903 } __attribute__ ((packed)); 1904 1905 struct isp2x_sihst_win_stat { 1906 __u32 hist_bins[ISP2X_SIHIST_BIN_N_MAX]; 1907 } __attribute__ ((packed)); 1908 1909 struct isp2x_sihst_stat { 1910 struct isp2x_sihst_win_stat win_stat[ISP2X_SIHIST_WIN_NUM]; 1911 } __attribute__ ((packed)); 1912 1913 struct isp2x_stat { 1914 struct isp2x_siawb_stat siawb; 1915 struct isp2x_rawawb_meas_stat rawawb; 1916 struct isp2x_rawaelite_stat rawae0; 1917 struct isp2x_rawaebig_stat rawae1; 1918 struct isp2x_rawaebig_stat rawae2; 1919 struct isp2x_rawaebig_stat rawae3; 1920 struct isp2x_yuvae_stat yuvae; 1921 struct isp2x_rawaf_stat rawaf; 1922 struct isp2x_siaf_stat siaf; 1923 struct isp2x_rawhistlite_stat rawhist0; 1924 struct isp2x_rawhistbig_stat rawhist1; 1925 struct isp2x_rawhistbig_stat rawhist2; 1926 struct isp2x_rawhistbig_stat rawhist3; 1927 struct isp2x_sihst_stat sihst; 1928 1929 struct isp2x_bls_stat bls; 1930 struct isp2x_hdrtmo_stat hdrtmo; 1931 struct isp2x_dhaz_stat dhaz; 1932 } __attribute__ ((packed)); 1933 1934 /** 1935 * struct rkisp_isp2x_stat_buffer - Rockchip ISP2 Statistics Meta Data 1936 * 1937 * @meas_type: measurement types (CIFISP_STAT_ definitions) 1938 * @frame_id: frame ID for sync 1939 * @params: statistics data 1940 */ 1941 struct rkisp_isp2x_stat_buffer { 1942 unsigned int meas_type; 1943 unsigned int frame_id; 1944 struct isp2x_stat params; 1945 } __attribute__ ((packed)); 1946 1947 /** 1948 * struct rkisp_mipi_luma - statistics mipi y statistic 1949 * 1950 * @exp_mean: Mean luminance value of block xx 1951 * 1952 * Image is divided into 5x5 blocks. 1953 */ 1954 struct rkisp_mipi_luma { 1955 unsigned int exp_mean[ISP2X_MIPI_LUMA_MEAN_MAX]; 1956 } __attribute__ ((packed)); 1957 1958 /** 1959 * struct rkisp_isp2x_luma_buffer - Rockchip ISP1 Statistics Mipi Luma 1960 * 1961 * @meas_type: measurement types (CIFISP_STAT_ definitions) 1962 * @frame_id: frame ID for sync 1963 * @params: statistics data 1964 */ 1965 struct rkisp_isp2x_luma_buffer { 1966 unsigned int meas_type; 1967 unsigned int frame_id; 1968 struct rkisp_mipi_luma luma[ISP2X_MIPI_RAW_MAX]; 1969 } __attribute__ ((packed)); 1970 1971 /** 1972 * struct rkisp_thunderboot_resmem_head 1973 */ 1974 struct rkisp_thunderboot_resmem_head { 1975 __u16 enable; 1976 __u16 complete; 1977 __u16 frm_total; 1978 __u16 hdr_mode; 1979 __u16 width; 1980 __u16 height; 1981 __u16 camera_num; 1982 __u16 camera_index; 1983 1984 __u32 exp_time[3]; 1985 __u32 exp_gain[3]; 1986 __u32 exp_time_reg[3]; 1987 __u32 exp_gain_reg[3]; 1988 } __attribute__ ((packed)); 1989 1990 /** 1991 * struct rkisp_thunderboot_resmem - shared buffer for thunderboot with risc-v side 1992 */ 1993 struct rkisp_thunderboot_resmem { 1994 __u32 resmem_padr; 1995 __u32 resmem_size; 1996 } __attribute__ ((packed)); 1997 1998 /** 1999 * struct rkisp_thunderboot_shmem 2000 */ 2001 struct rkisp_thunderboot_shmem { 2002 __u32 shm_start; 2003 __u32 shm_size; 2004 __s32 shm_fd; 2005 } __attribute__ ((packed)); 2006 2007 #endif /* _UAPI_RK_ISP2_CONFIG_H */ 2008