xref: /OK3568_Linux_fs/kernel/include/dt-bindings/memory/rk3328-dram.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * This file is dual-licensed: you can use it either under the terms
5*4882a593Smuzhiyun  * of the GPL or the X11 license, at your option. Note that this dual
6*4882a593Smuzhiyun  * licensing only applies to this file, and not this project as a
7*4882a593Smuzhiyun  * whole.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  *  a) This library is free software; you can redistribute it and/or
10*4882a593Smuzhiyun  *     modify it under the terms of the GNU General Public License as
11*4882a593Smuzhiyun  *     published by the Free Software Foundation; either version 2 of the
12*4882a593Smuzhiyun  *     License, or (at your option) any later version.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  *     This library is distributed in the hope that it will be useful,
15*4882a593Smuzhiyun  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16*4882a593Smuzhiyun  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17*4882a593Smuzhiyun  *     GNU General Public License for more details.
18*4882a593Smuzhiyun  *
19*4882a593Smuzhiyun  * Or, alternatively,
20*4882a593Smuzhiyun  *
21*4882a593Smuzhiyun  *  b) Permission is hereby granted, free of charge, to any person
22*4882a593Smuzhiyun  *     obtaining a copy of this software and associated documentation
23*4882a593Smuzhiyun  *     files (the "Software"), to deal in the Software without
24*4882a593Smuzhiyun  *     restriction, including without limitation the rights to use,
25*4882a593Smuzhiyun  *     copy, modify, merge, publish, distribute, sublicense, and/or
26*4882a593Smuzhiyun  *     sell copies of the Software, and to permit persons to whom the
27*4882a593Smuzhiyun  *     Software is furnished to do so, subject to the following
28*4882a593Smuzhiyun  *     conditions:
29*4882a593Smuzhiyun  *
30*4882a593Smuzhiyun  *     The above copyright notice and this permission notice shall be
31*4882a593Smuzhiyun  *     included in all copies or substantial portions of the Software.
32*4882a593Smuzhiyun  *
33*4882a593Smuzhiyun  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34*4882a593Smuzhiyun  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35*4882a593Smuzhiyun  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36*4882a593Smuzhiyun  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37*4882a593Smuzhiyun  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38*4882a593Smuzhiyun  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39*4882a593Smuzhiyun  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40*4882a593Smuzhiyun  *     OTHER DEALINGS IN THE SOFTWARE.
41*4882a593Smuzhiyun  */
42*4882a593Smuzhiyun #ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H
43*4882a593Smuzhiyun #define _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun #define DDR3_DS_34ohm			(34)
46*4882a593Smuzhiyun #define DDR3_DS_40ohm			(40)
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #define DDR3_ODT_DIS			(0)
49*4882a593Smuzhiyun #define DDR3_ODT_40ohm			(40)
50*4882a593Smuzhiyun #define DDR3_ODT_60ohm			(60)
51*4882a593Smuzhiyun #define DDR3_ODT_120ohm			(120)
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun #define LP2_DS_34ohm			(34)
54*4882a593Smuzhiyun #define LP2_DS_40ohm			(40)
55*4882a593Smuzhiyun #define LP2_DS_48ohm			(48)
56*4882a593Smuzhiyun #define LP2_DS_60ohm			(60)
57*4882a593Smuzhiyun #define LP2_DS_68_6ohm			(68)	/* optional */
58*4882a593Smuzhiyun #define LP2_DS_80ohm			(80)
59*4882a593Smuzhiyun #define LP2_DS_120ohm			(120)	/* optional */
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun #define LP3_DS_34ohm			(34)
62*4882a593Smuzhiyun #define LP3_DS_40ohm			(40)
63*4882a593Smuzhiyun #define LP3_DS_48ohm			(48)
64*4882a593Smuzhiyun #define LP3_DS_60ohm			(60)
65*4882a593Smuzhiyun #define LP3_DS_80ohm			(80)
66*4882a593Smuzhiyun #define LP3_DS_34D_40U			(3440)
67*4882a593Smuzhiyun #define LP3_DS_40D_48U			(4048)
68*4882a593Smuzhiyun #define LP3_DS_34D_48U			(3448)
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun #define LP3_ODT_DIS			(0)
71*4882a593Smuzhiyun #define LP3_ODT_60ohm			(60)
72*4882a593Smuzhiyun #define LP3_ODT_120ohm			(120)
73*4882a593Smuzhiyun #define LP3_ODT_240ohm			(240)
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun #define LP4_PDDS_40ohm			(40)
76*4882a593Smuzhiyun #define LP4_PDDS_48ohm			(48)
77*4882a593Smuzhiyun #define LP4_PDDS_60ohm			(60)
78*4882a593Smuzhiyun #define LP4_PDDS_80ohm			(80)
79*4882a593Smuzhiyun #define LP4_PDDS_120ohm			(120)
80*4882a593Smuzhiyun #define LP4_PDDS_240ohm			(240)
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun #define LP4_DQ_ODT_40ohm		(40)
83*4882a593Smuzhiyun #define LP4_DQ_ODT_48ohm		(48)
84*4882a593Smuzhiyun #define LP4_DQ_ODT_60ohm		(60)
85*4882a593Smuzhiyun #define LP4_DQ_ODT_80ohm		(80)
86*4882a593Smuzhiyun #define LP4_DQ_ODT_120ohm		(120)
87*4882a593Smuzhiyun #define LP4_DQ_ODT_240ohm		(240)
88*4882a593Smuzhiyun #define LP4_DQ_ODT_DIS			(0)
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun #define LP4_CA_ODT_40ohm		(40)
91*4882a593Smuzhiyun #define LP4_CA_ODT_48ohm		(48)
92*4882a593Smuzhiyun #define LP4_CA_ODT_60ohm		(60)
93*4882a593Smuzhiyun #define LP4_CA_ODT_80ohm		(80)
94*4882a593Smuzhiyun #define LP4_CA_ODT_120ohm		(120)
95*4882a593Smuzhiyun #define LP4_CA_ODT_240ohm		(240)
96*4882a593Smuzhiyun #define LP4_CA_ODT_DIS			(0)
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun #define DDR4_DS_34ohm			(34)
99*4882a593Smuzhiyun #define DDR4_DS_48ohm			(48)
100*4882a593Smuzhiyun #define DDR4_RTT_NOM_DIS		(0)
101*4882a593Smuzhiyun #define DDR4_RTT_NOM_60ohm		(60)
102*4882a593Smuzhiyun #define DDR4_RTT_NOM_120ohm		(120)
103*4882a593Smuzhiyun #define DDR4_RTT_NOM_40ohm		(40)
104*4882a593Smuzhiyun #define DDR4_RTT_NOM_240ohm		(240)
105*4882a593Smuzhiyun #define DDR4_RTT_NOM_48ohm		(48)
106*4882a593Smuzhiyun #define DDR4_RTT_NOM_80ohm		(80)
107*4882a593Smuzhiyun #define DDR4_RTT_NOM_34ohm		(34)
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_DISABLE	(0)
110*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_451ohm		(1)
111*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_225ohm		(2)
112*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_150ohm		(3)
113*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_112ohm		(4)
114*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_90ohm		(5)
115*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_75ohm		(6)
116*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_64ohm		(7)
117*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_56ohm		(16)
118*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_50ohm		(17)
119*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_45ohm		(18)
120*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_41ohm		(19)
121*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_37ohm		(20)
122*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_34ohm		(21)
123*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_33ohm		(22)
124*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_30ohm		(23)
125*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_28ohm		(24)
126*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_26ohm		(25)
127*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_25ohm		(26)
128*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_23ohm		(27)
129*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_22ohm		(28)
130*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_21ohm		(29)
131*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_20ohm		(30)
132*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_19ohm		(31)
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0)
135*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_480ohm	(1)
136*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_240ohm	(2)
137*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_160ohm	(3)
138*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_120ohm	(4)
139*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_96ohm	(5)
140*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_80ohm	(6)
141*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_68ohm	(7)
142*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_60ohm	(16)
143*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_53ohm	(17)
144*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_48ohm	(18)
145*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_43ohm	(19)
146*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_40ohm	(20)
147*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_37ohm	(21)
148*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_34ohm	(22)
149*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_32ohm	(23)
150*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_30ohm	(24)
151*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_28ohm	(25)
152*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_26ohm	(26)
153*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_25ohm	(27)
154*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_24ohm	(28)
155*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_22ohm	(29)
156*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_21ohm	(30)
157*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_RON_RTT_20ohm	(31)
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun #endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H*/
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