xref: /OK3568_Linux_fs/kernel/include/dt-bindings/memory/px30-dram.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_DRAM_ROCKCHIP_PX30_H
8*4882a593Smuzhiyun #define _DT_BINDINGS_DRAM_ROCKCHIP_PX30_H
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #define DDR2_DS_FULL			(0)
11*4882a593Smuzhiyun #define DDR2_DS_REDUCE			(1)
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #define DDR2_ODT_DIS			(0)
14*4882a593Smuzhiyun #define DDR2_ODT_50ohm			(50)	/* optional */
15*4882a593Smuzhiyun #define DDR2_ODT_75ohm			(75)
16*4882a593Smuzhiyun #define DDR2_ODT_150ohm			(150)
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define DDR3_DS_34ohm			(34)
19*4882a593Smuzhiyun #define DDR3_DS_40ohm			(40)
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define DDR3_ODT_DIS			(0)
22*4882a593Smuzhiyun #define DDR3_ODT_40ohm			(40)
23*4882a593Smuzhiyun #define DDR3_ODT_60ohm			(60)
24*4882a593Smuzhiyun #define DDR3_ODT_120ohm			(120)
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #define LP2_DS_34ohm			(34)
27*4882a593Smuzhiyun #define LP2_DS_40ohm			(40)
28*4882a593Smuzhiyun #define LP2_DS_48ohm			(48)
29*4882a593Smuzhiyun #define LP2_DS_60ohm			(60)
30*4882a593Smuzhiyun #define LP2_DS_68_6ohm			(68)	/* optional */
31*4882a593Smuzhiyun #define LP2_DS_80ohm			(80)
32*4882a593Smuzhiyun #define LP2_DS_120ohm			(120)	/* optional */
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #define LP3_DS_34ohm			(34)
35*4882a593Smuzhiyun #define LP3_DS_40ohm			(40)
36*4882a593Smuzhiyun #define LP3_DS_48ohm			(48)
37*4882a593Smuzhiyun #define LP3_DS_60ohm			(60)
38*4882a593Smuzhiyun #define LP3_DS_80ohm			(80)
39*4882a593Smuzhiyun #define LP3_DS_34D_40U			(3440)
40*4882a593Smuzhiyun #define LP3_DS_40D_48U			(4048)
41*4882a593Smuzhiyun #define LP3_DS_34D_48U			(3448)
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #define LP3_ODT_DIS			(0)
44*4882a593Smuzhiyun #define LP3_ODT_60ohm			(60)
45*4882a593Smuzhiyun #define LP3_ODT_120ohm			(120)
46*4882a593Smuzhiyun #define LP3_ODT_240ohm			(240)
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #define LP4_PDDS_40ohm			(40)
49*4882a593Smuzhiyun #define LP4_PDDS_48ohm			(48)
50*4882a593Smuzhiyun #define LP4_PDDS_60ohm			(60)
51*4882a593Smuzhiyun #define LP4_PDDS_80ohm			(80)
52*4882a593Smuzhiyun #define LP4_PDDS_120ohm			(120)
53*4882a593Smuzhiyun #define LP4_PDDS_240ohm			(240)
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun #define LP4_DQ_ODT_40ohm		(40)
56*4882a593Smuzhiyun #define LP4_DQ_ODT_48ohm		(48)
57*4882a593Smuzhiyun #define LP4_DQ_ODT_60ohm		(60)
58*4882a593Smuzhiyun #define LP4_DQ_ODT_80ohm		(80)
59*4882a593Smuzhiyun #define LP4_DQ_ODT_120ohm		(120)
60*4882a593Smuzhiyun #define LP4_DQ_ODT_240ohm		(240)
61*4882a593Smuzhiyun #define LP4_DQ_ODT_DIS			(0)
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun #define LP4_CA_ODT_40ohm		(40)
64*4882a593Smuzhiyun #define LP4_CA_ODT_48ohm		(48)
65*4882a593Smuzhiyun #define LP4_CA_ODT_60ohm		(60)
66*4882a593Smuzhiyun #define LP4_CA_ODT_80ohm		(80)
67*4882a593Smuzhiyun #define LP4_CA_ODT_120ohm		(120)
68*4882a593Smuzhiyun #define LP4_CA_ODT_240ohm		(240)
69*4882a593Smuzhiyun #define LP4_CA_ODT_DIS			(0)
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun #define DDR4_DS_34ohm			(34)
72*4882a593Smuzhiyun #define DDR4_DS_48ohm			(48)
73*4882a593Smuzhiyun #define DDR4_RTT_NOM_DIS		(0)
74*4882a593Smuzhiyun #define DDR4_RTT_NOM_60ohm		(60)
75*4882a593Smuzhiyun #define DDR4_RTT_NOM_120ohm		(120)
76*4882a593Smuzhiyun #define DDR4_RTT_NOM_40ohm		(40)
77*4882a593Smuzhiyun #define DDR4_RTT_NOM_240ohm		(240)
78*4882a593Smuzhiyun #define DDR4_RTT_NOM_48ohm		(48)
79*4882a593Smuzhiyun #define DDR4_RTT_NOM_80ohm		(80)
80*4882a593Smuzhiyun #define DDR4_RTT_NOM_34ohm		(34)
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_DISABLE	(0)
83*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_451ohm		(1)
84*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_225ohm		(2)
85*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_150ohm		(3)
86*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_112ohm		(4)
87*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_90ohm		(5)
88*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_75ohm		(6)
89*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_64ohm		(7)
90*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_56ohm		(16)
91*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_50ohm		(17)
92*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_45ohm		(18)
93*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_41ohm		(19)
94*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_37ohm		(20)
95*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_34ohm		(21)
96*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_33ohm		(22)
97*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_30ohm		(23)
98*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_28ohm		(24)
99*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_26ohm		(25)
100*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_25ohm		(26)
101*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_23ohm		(27)
102*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_22ohm		(28)
103*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_21ohm		(29)
104*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_20ohm		(30)
105*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_19ohm		(31)
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_DISABLE (0)
108*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_480ohm	(1)
109*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_240ohm	(2)
110*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_160ohm	(3)
111*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_120ohm	(4)
112*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_96ohm	(5)
113*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_80ohm	(6)
114*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_68ohm	(7)
115*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_60ohm	(16)
116*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_53ohm	(17)
117*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_48ohm	(18)
118*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_43ohm	(19)
119*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_40ohm	(20)
120*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_37ohm	(21)
121*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_34ohm	(22)
122*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_32ohm	(23)
123*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_30ohm	(24)
124*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_28ohm	(25)
125*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_26ohm	(26)
126*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_25ohm	(27)
127*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_24ohm	(28)
128*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_22ohm	(29)
129*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_21ohm	(30)
130*4882a593Smuzhiyun #define PHY_DDR4_LPDDR3_2_RON_RTT_20ohm	(31)
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun #define LP4_VDDQ_2_5			(0)
133*4882a593Smuzhiyun #define LP4_VDDQ_3			(1)
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun #define LP4X_VDDQ_0_6			(0)
136*4882a593Smuzhiyun #define LP4X_VDDQ_0_5			(1)
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun #define IGNORE_THIS			(0)
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun #endif /*_DT_BINDINGS_DRAM_ROCKCHIP_PX30_H*/
141