1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1106_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RV1106_H 9 10 /* pll clocks */ 11 #define PLL_APLL 1 12 #define PLL_DPLL 2 13 #define PLL_CPLL 3 14 #define PLL_GPLL 4 15 #define ARMCLK 5 16 17 /* clk (clocks) */ 18 #define PCLK_DDRPHY 11 19 #define PCLK_DDR_ROOT 12 20 #define PCLK_DDRMON 13 21 #define CLK_TIMER_DDRMON 14 22 #define PCLK_DDRC 15 23 #define PCLK_DFICTRL 16 24 #define ACLK_DDR_ROOT 17 25 #define ACLK_SYS_SHRM 18 26 #define HCLK_NPU_ROOT 19 27 #define ACLK_NPU_ROOT 20 28 #define PCLK_NPU_ROOT 21 29 #define HCLK_RKNN 22 30 #define ACLK_RKNN 23 31 #define PCLK_ACODEC 24 32 #define MCLK_ACODEC_TX 25 33 #define CLK_CORE_CRYPTO 27 34 #define CLK_PKA_CRYPTO 28 35 #define ACLK_CRYPTO 29 36 #define HCLK_CRYPTO 30 37 #define ACLK_DECOM 31 38 #define PCLK_DECOM 32 39 #define DCLK_DECOM 33 40 #define ACLK_DMAC 34 41 #define PCLK_DSM 35 42 #define MCLK_DSM 36 43 #define CCLK_SRC_EMMC 37 44 #define HCLK_EMMC 38 45 #define PCLK_GPIO4 39 46 #define DBCLK_GPIO4 40 47 #define PCLK_I2C0 41 48 #define CLK_I2C0 42 49 #define PCLK_I2C2 43 50 #define CLK_I2C2 44 51 #define PCLK_I2C3 45 52 #define CLK_I2C3 46 53 #define PCLK_I2C4 47 54 #define CLK_I2C4 48 55 #define HCLK_I2S0 49 56 #define PCLK_DFT2APB 50 57 #define HCLK_IVE 51 58 #define ACLK_IVE 52 59 #define PCLK_PWM0_PERI 53 60 #define CLK_PWM0_PERI 54 61 #define CLK_CAPTURE_PWM0_PERI 55 62 #define PCLK_PERI_ROOT 56 63 #define ACLK_PERI_ROOT 57 64 #define HCLK_PERI_ROOT 58 65 #define CLK_TIMER_ROOT 59 66 #define ACLK_BUS_ROOT 60 67 #define HCLK_SFC 61 68 #define SCLK_SFC 62 69 #define PCLK_UART0 63 70 #define CLK_PVTM_CORE 64 71 #define PCLK_UART1 65 72 #define CLK_CORE_MCU_RTC 66 73 #define PCLK_PWM1_PERI 67 74 #define CLK_PWM1_PERI 68 75 #define CLK_CAPTURE_PWM1_PERI 69 76 #define PCLK_PWM2_PERI 70 77 #define CLK_PWM2_PERI 71 78 #define CLK_CAPTURE_PWM2_PERI 72 79 #define HCLK_BOOTROM 73 80 #define HCLK_SAI 74 81 #define MCLK_SAI 75 82 #define PCLK_SARADC 76 83 #define CLK_SARADC 77 84 #define PCLK_SPI1 78 85 #define CLK_SPI1 79 86 #define PCLK_STIMER 80 87 #define CLK_STIMER0 81 88 #define CLK_STIMER1 82 89 #define PCLK_TIMER 83 90 #define CLK_TIMER0 84 91 #define CLK_TIMER1 85 92 #define CLK_TIMER2 86 93 #define CLK_TIMER3 87 94 #define CLK_TIMER4 88 95 #define CLK_TIMER5 89 96 #define HCLK_TRNG_NS 90 97 #define HCLK_TRNG_S 91 98 #define PCLK_UART2 92 99 #define HCLK_CPU 93 100 #define PCLK_UART3 94 101 #define CLK_CORE_MCU 95 102 #define PCLK_UART4 96 103 #define PCLK_DDR_HWLP 97 104 #define PCLK_UART5 98 105 #define ACLK_USBOTG 100 106 #define CLK_REF_USBOTG 101 107 #define CLK_UTMI_USBOTG 102 108 #define PCLK_USBPHY 103 109 #define CLK_REF_USBPHY 104 110 #define PCLK_WDT_NS 105 111 #define TCLK_WDT_NS 106 112 #define PCLK_WDT_S 107 113 #define TCLK_WDT_S 108 114 #define CLK_DDR_FAIL_SAFE 109 115 #define XIN_OSC0_DIV 110 116 #define CLK_DEEPSLOW 111 117 #define PCLK_PMU_GPIO0 112 118 #define DBCLK_PMU_GPIO0 113 119 #define CLK_PMU 114 120 #define PCLK_PMU 115 121 #define PCLK_PMU_HP_TIMER 116 122 #define CLK_PMU_HP_TIMER 117 123 #define CLK_PMU_32K_HP_TIMER 118 124 #define PCLK_I2C1 119 125 #define CLK_I2C1 120 126 #define PCLK_PMU_IOC 121 127 #define PCLK_PMU_MAILBOX 122 128 #define CLK_PMU_MCU 123 129 #define CLK_PMU_MCU_RTC 124 130 #define CLK_PMU_MCU_JTAG 125 131 #define CLK_PVTM_PMU 126 132 #define PCLK_PVTM_PMU 127 133 #define CLK_REFOUT 128 134 #define CLK_100M_PMU 129 135 #define PCLK_PMU_ROOT 130 136 #define HCLK_PMU_ROOT 131 137 #define HCLK_PMU_SRAM 132 138 #define PCLK_PMU_WDT 133 139 #define TCLK_PMU_WDT 134 140 #define CLK_DFICTRL 135 141 #define CLK_DDRMON 136 142 #define CLK_DDR_PHY 137 143 #define ACLK_DDRC 138 144 #define CLK_CORE_DDRC_SRC 139 145 #define CLK_CORE_DDRC 140 146 #define CLK_50M_SRC 141 147 #define CLK_100M_SRC 142 148 #define CLK_150M_SRC 143 149 #define CLK_200M_SRC 144 150 #define CLK_250M_SRC 145 151 #define CLK_300M_SRC 146 152 #define CLK_339M_SRC 147 153 #define CLK_400M_SRC 148 154 #define CLK_450M_SRC 149 155 #define CLK_500M_SRC 150 156 #define CLK_I2S0_8CH_TX_SRC 151 157 #define CLK_I2S0_8CH_TX_FRAC 152 158 #define CLK_I2S0_8CH_TX 153 159 #define CLK_I2S0_8CH_RX_SRC 154 160 #define CLK_I2S0_8CH_RX_FRAC 155 161 #define CLK_I2S0_8CH_RX 156 162 #define I2S0_8CH_MCLKOUT 157 163 #define MCLK_I2S0_8CH_RX 158 164 #define MCLK_I2S0_8CH_TX 159 165 #define CLK_REF_MIPI0_SRC 160 166 #define CLK_REF_MIPI0_FRAC 161 167 #define CLK_REF_MIPI0_OUT 162 168 #define CLK_REF_MIPI1_SRC 163 169 #define CLK_REF_MIPI1_FRAC 164 170 #define MCLK_REF_MIPI0 165 171 #define MCLK_REF_MIPI1 166 172 #define CLK_REF_MIPI0 167 173 #define CLK_REF_MIPI1 168 174 #define CLK_UART0_SRC 169 175 #define CLK_UART0_FRAC 170 176 #define CLK_UART0 171 177 #define SCLK_UART0 172 178 #define CLK_UART1_SRC 173 179 #define CLK_UART1_FRAC 174 180 #define CLK_UART1 175 181 #define SCLK_UART1 176 182 #define CLK_UART2_SRC 177 183 #define CLK_UART2_FRAC 178 184 #define CLK_UART2 179 185 #define SCLK_UART2 180 186 #define CLK_UART3_SRC 181 187 #define CLK_UART3_FRAC 182 188 #define CLK_UART3 183 189 #define SCLK_UART3 184 190 #define CLK_UART4_SRC 185 191 #define CLK_UART4_FRAC 186 192 #define CLK_UART4 187 193 #define SCLK_UART4 188 194 #define CLK_UART5_SRC 189 195 #define CLK_UART5_FRAC 190 196 #define CLK_UART5 191 197 #define SCLK_UART5 192 198 #define CLK_VICAP_M0_SRC 193 199 #define CLK_VICAP_M0_FRAC 194 200 #define CLK_VICAP_M0 195 201 #define SCLK_VICAP_M0 196 202 #define CLK_VICAP_M1_SRC 197 203 #define CLK_VICAP_M1_FRAC 198 204 #define CLK_VICAP_M1 199 205 #define SCLK_VICAP_M1 200 206 #define DCLK_VOP_SRC 201 207 #define PCLK_CRU 202 208 #define PCLK_TOP_ROOT 203 209 #define PCLK_SPI0 204 210 #define CLK_SPI0 205 211 #define SCLK_IN_SPI0 206 212 #define CLK_UART_DETN_FLT 207 213 #define HCLK_VEPU 208 214 #define ACLK_VEPU 209 215 #define CLK_CORE_VEPU 210 216 #define CLK_CORE_VEPU_DVBM 211 217 #define PCLK_GPIO1 212 218 #define DBCLK_GPIO1 213 219 #define HCLK_VEPU_PP 214 220 #define ACLK_VEPU_PP 215 221 #define HCLK_VEPU_ROOT 216 222 #define ACLK_VEPU_COM_ROOT 217 223 #define ACLK_VEPU_ROOT 218 224 #define PCLK_VEPU_ROOT 219 225 #define PCLK_VICAP_VEPU 220 226 #define PCLK_CSIHOST0 221 227 #define CLK_RXBYTECLKHS_0 222 228 #define PCLK_CSIHOST1 223 229 #define CLK_RXBYTECLKHS_1 224 230 #define PCLK_GPIO3 225 231 #define DBCLK_GPIO3 226 232 #define HCLK_ISP3P2 227 233 #define ACLK_ISP3P2 228 234 #define CLK_CORE_ISP3P2 229 235 #define PCLK_MIPICSIPHY 230 236 #define CCLK_SRC_SDMMC 231 237 #define HCLK_SDMMC 232 238 #define CLK_SDMMC_DETN_FLT 233 239 #define HCLK_VI_ROOT 234 240 #define ACLK_VI_ROOT 235 241 #define PCLK_VI_ROOT 236 242 #define PCLK_VI_RTC_ROOT 237 243 #define PCLK_VI_RTC_TEST 238 244 #define PCLK_VI_RTC_PHY 239 245 #define DCLK_VICAP 240 246 #define PCLK_VICAP 241 247 #define ACLK_VICAP 242 248 #define HCLK_VICAP 243 249 #define I0CLK_VICAP 244 250 #define I1CLK_VICAP 245 251 #define RX0PCLK_VICAP 246 252 #define RX1PCLK_VICAP 247 253 #define ISP0CLK_VICAP 248 254 #define PCLK_GPIO2 249 255 #define DBCLK_GPIO2 250 256 #define ACLK_MAC 251 257 #define PCLK_MAC 252 258 #define CLK_GMAC0_50M_O 253 259 #define CLK_GMAC0_TX_50M_O 254 260 #define CLK_GMAC0_REF_50M 255 261 #define CLK_GMAC0_TX_50M 256 262 #define CLK_GMAC0_RX_50M 257 263 #define ACLK_MAC_ROOT 258 264 #define CLK_MACPHY 259 265 #define CLK_OTPC_ARB 260 266 #define PCLK_OTPC_NS 261 267 #define CLK_SBPI_OTPC_NS 262 268 #define CLK_USER_OTPC_NS 263 269 #define PCLK_OTPC_S 264 270 #define CLK_SBPI_OTPC_S 265 271 #define CLK_USER_OTPC_S 266 272 #define PCLK_OTP_MASK 267 273 #define CLK_PMC_OTP 268 274 #define HCLK_RGA2E 269 275 #define ACLK_RGA2E 270 276 #define CLK_CORE_RGA2E 271 277 #define CCLK_SRC_SDIO 272 278 #define HCLK_SDIO 273 279 #define PCLK_TSADC 274 280 #define CLK_TSADC 275 281 #define CLK_TSADC_TSEN 276 282 #define ACLK_VO_ROOT 277 283 #define HCLK_VO_ROOT 278 284 #define PCLK_VO_ROOT 279 285 #define ACLK_VOP_ROOT 280 286 #define HCLK_VOP 281 287 #define DCLK_VOP 282 288 #define ACLK_VOP 283 289 #define CLK_RTC_32K 284 290 #define PCLK_MAILBOX 291 291 292 #define CLK_NR_CLKS (PCLK_MAILBOX + 1) 293 294 #define SCLK_EMMC_DRV 1 295 #define SCLK_EMMC_SAMPLE 2 296 #define SCLK_SDMMC_DRV 3 297 #define SCLK_SDMMC_SAMPLE 4 298 #define SCLK_SDIO_DRV 5 299 #define SCLK_SDIO_SAMPLE 6 300 301 #define CLK_NR_GRF_CLKS (SCLK_SDIO_SAMPLE + 1) 302 303 /********Name=PMUSOFTRST_CON00,Offset=0xA00********/ 304 #define SRST_P_I2C1 3 305 #define SRST_I2C1 4 306 #define SRST_H_PMU_BIU 6 307 #define SRST_P_PMU_BIU 7 308 #define SRST_H_PMU_SRAM 8 309 #define SRST_PMU_MCU 9 310 #define SRST_PMU_MCU_PWRUP 10 311 #define SRST_PMU_MCU_CPU 11 312 #define SRST_T_PMU_MCU_CPU 12 313 /********Name=PMUSOFTRST_CON01,Offset=0xA04********/ 314 #define SRST_P_PMU_GPIO0 18 315 #define SRST_PMU_GPIO0 19 316 #define SRST_PVTM_PMU 20 317 #define SRST_P_PVTM_PMU 21 318 #define SRST_DDR_FAIL_SAFE 31 319 /********Name=PMUSOFTRST_CON02,Offset=0xA08********/ 320 #define SRST_P_PMU_HP_TIMER 32 321 #define SRST_PMU_HP_TIMER 33 322 #define SRST_PMU_32K_HP_TIMER 34 323 #define SRST_P_PMU_IOC 35 324 #define SRST_P_PMU_CRU 36 325 #define SRST_P_PMU_GRF 37 326 #define SRST_P_PMU_SGRF 38 327 #define SRST_P_PMU_SGRF_REMAP 39 328 #define SRST_P_PMU_WDT 40 329 #define SRST_T_PMU_WDT 41 330 #define SRST_P_PMU_MAILBOX 42 331 #define SRST_WRITE_ENABLE 48 332 /********Name=SOFTRST_CON02,Offset=0x10A08********/ 333 #define SRST_REF_PVTPLL_0 262183 334 #define SRST_REF_PVTPLL_1 262184 335 #define SRST_P_CRU 262186 336 #define SRST_P_CRU_BIU 262187 337 /********Name=PERISOFTRST_CON00,Offset=0x12A00********/ 338 #define SRST_P_PERI_BIU 294916 339 #define SRST_A_PERI_BIU 294917 340 #define SRST_H_PERI_BIU 294918 341 #define SRST_H_BOOTROM 294919 342 #define SRST_P_TIMER 294920 343 #define SRST_TIMER0 294921 344 #define SRST_TIMER1 294922 345 #define SRST_TIMER2 294923 346 #define SRST_TIMER3 294924 347 #define SRST_TIMER4 294925 348 #define SRST_TIMER5 294926 349 #define SRST_P_STIMER 294927 350 /********Name=PERISOFTRST_CON01,Offset=0x12A04********/ 351 #define SRST_STIMER0 294928 352 #define SRST_STIMER1 294929 353 #define SRST_P_WDT_NS 294930 354 #define SRST_T_WDT_NS 294931 355 #define SRST_P_WDT_S 294932 356 #define SRST_T_WDT_S 294933 357 #define SRST_P_I2C0 294934 358 #define SRST_I2C0 294935 359 #define SRST_P_I2C2 294938 360 #define SRST_I2C2 294939 361 #define SRST_P_I2C3 294940 362 #define SRST_I2C3 294941 363 #define SRST_P_I2C4 294942 364 #define SRST_I2C4 294943 365 /********Name=PERISOFTRST_CON02,Offset=0x12A08********/ 366 #define SRST_P_GPIO4 294944 367 #define SRST_GPIO4 294945 368 #define SRST_P_PERI_IOC 294946 369 #define SRST_P_UART2 294947 370 #define SRST_S_UART2 294950 371 #define SRST_P_UART3 294951 372 #define SRST_S_UART3 294954 373 #define SRST_P_UART4 294955 374 #define SRST_S_UART4 294958 375 #define SRST_P_UART5 294959 376 /********Name=PERISOFTRST_CON03,Offset=0x12A0C********/ 377 #define SRST_S_UART5 294962 378 #define SRST_P_SARADC 294963 379 #define SRST_SARADC 294964 380 #define SRST_SARADC_PHY 294965 381 #define SRST_P_SPI1 294966 382 #define SRST_SPI1 294967 383 #define SRST_H_TRNG_NS 294969 384 #define SRST_H_TRNG_S 294970 385 #define SRST_CORE_CRYPTO 294971 386 #define SRST_PKA_CRYPTO 294972 387 #define SRST_A_CRYPTO 294973 388 #define SRST_H_CRYPTO 294974 389 #define SRST_P_PWM1_PERI 294975 390 /********Name=PERISOFTRST_CON04,Offset=0x12A10********/ 391 #define SRST_PWM1_PERI 294976 392 #define SRST_P_PWM2_PERI 294978 393 #define SRST_PWM2_PERI 294979 394 #define SRST_P_PERI_GRF 294981 395 #define SRST_P_PERI_CRU 294982 396 #define SRST_A_USBOTG 294983 397 #define SRST_A_BUS_BIU 294986 398 #define SRST_H_EMMC 294989 399 #define SRST_H_SFC 294990 400 /********Name=PERISOFTRST_CON05,Offset=0x12A14********/ 401 #define SRST_S_SFC 294992 402 #define SRST_P_USBPHY 294993 403 #define SRST_USBPHY_POR 294994 404 #define SRST_USBPHY_OTG 294995 405 #define SRST_A_DMAC 295000 406 #define SRST_A_DECOM 295001 407 #define SRST_P_DECOM 295002 408 #define SRST_D_DECOM 295003 409 #define SRST_P_PERI_SGRF 295004 410 #define SRST_H_SAI 295005 411 #define SRST_M_SAI 295006 412 #define SRST_M_I2S0_8CH_TX 295007 413 /********Name=PERISOFTRST_CON06,Offset=0x12A18********/ 414 #define SRST_H_I2S0 295008 415 #define SRST_M_DSM 295009 416 #define SRST_P_DSM 295010 417 #define SRST_P_ACODEC 295011 418 #define SRST_M_I2S0_8CH_RX 295014 419 #define SRST_P_DFT2APB 295015 420 #define SRST_H_IVE 295017 421 #define SRST_A_IVE 295018 422 #define SRST_P_UART0 295019 423 #define SRST_S_UART0 295022 424 #define SRST_P_UART1 295023 425 /********Name=PERISOFTRST_CON07,Offset=0x12A1C********/ 426 #define SRST_S_UART1 295026 427 #define SRST_P_PWM0_PERI 295027 428 #define SRST_PWM0_PERI 295028 429 /********Name=VISOFTRST_CON00,Offset=0x14A00********/ 430 #define SRST_H_VI_BIU 327684 431 #define SRST_A_VI_BIU 327685 432 #define SRST_P_VI_BIU 327686 433 #define SRST_CORE_ISP3P2 327689 434 #define SRST_D_VICAP 327690 435 #define SRST_P_VICAP 327691 436 #define SRST_A_VICAP 327692 437 #define SRST_H_VICAP 327693 438 #define SRST_VICAP_I0 327694 439 #define SRST_VICAP_I1 327695 440 /********Name=VISOFTRST_CON01,Offset=0x14A04********/ 441 #define SRST_VICAP_RX0 327696 442 #define SRST_VICAP_RX1 327697 443 #define SRST_VICAP_ISP0 327698 444 #define SRST_P_CSIHOST0 327700 445 #define SRST_P_CSIHOST1 327702 446 #define SRST_H_SDMMC 327708 447 #define SRST_SDMMC_DETN_FLT 327709 448 #define SRST_P_MIPICSIPHY 327710 449 #define SRST_P_GPIO3 327711 450 /********Name=VISOFTRST_CON02,Offset=0x14A08********/ 451 #define SRST_GPIO3 327712 452 #define SRST_P_VI_IOC 327713 453 #define SRST_P_VI_GRF 327714 454 #define SRST_P_VI_SGRF 327715 455 #define SRST_P_VI_CRU 327716 456 #define SRST_P_VI_RTC_TEST 327717 457 #define SRST_P_VI_RTC_NIU 327719 458 /********Name=NPUSOFTRST_CON00,Offset=0x16A00********/ 459 #define SRST_H_NPU_BIU 360451 460 #define SRST_A_NPU_BIU 360452 461 #define SRST_P_NPU_BIU 360453 462 #define SRST_P_NPU_CRU 360454 463 #define SRST_P_NPU_SGRF 360455 464 #define SRST_P_NPU_GRF 360456 465 #define SRST_H_RKNN 360457 466 #define SRST_A_RKNN 360458 467 /********Name=CORESOFTRST_CON00,Offset=0x18A00********/ 468 #define SRST_NCOREPORESET 393217 469 #define SRST_NCORESET 393218 470 #define SRST_NDBGRESET 393219 471 #define SRST_NL2RESET 393220 472 #define SRST_A_M_CORE_BIU 393221 473 #define SRST_P_DBG 393222 474 #define SRST_POT_DBG 393223 475 #define SRST_NT_DBG 393224 476 #define SRST_P_CORE_GRF 393227 477 #define SRST_H_CPU_BIU 393228 478 #define SRST_P_CPU_BIU 393229 479 #define SRST_PVTM_CORE 393230 480 #define SRST_P_PVTM_CORE 393231 481 /********Name=CORESOFTRST_CON01,Offset=0x18A04********/ 482 #define SRST_REF_PVTPLL_CORE 393232 483 #define SRST_CORE_MCU 393233 484 #define SRST_CORE_MCU_PWRUP 393234 485 #define SRST_CORE_MCU_CPU 393235 486 #define SRST_T_CORE_MCU_CPU 393236 487 #define SRST_MCU_BIU 393237 488 #define SRST_P_MAILBOX 393240 489 #define SRST_P_INTMUX 393241 490 #define SRST_P_CORE_CRU 393242 491 #define SRST_P_CORE_SGRF 393243 492 #define SRST_H_CACHE 393244 493 /********Name=VEPUSOFTRST_CON00,Offset=0x1AA00********/ 494 #define SRST_H_VEPU_BIU 425988 495 #define SRST_A_VEPU_BIU 425989 496 #define SRST_A_VEPU_COM_BIU 425990 497 #define SRST_P_VEPU_BIU 425991 498 #define SRST_H_VEPU 425992 499 #define SRST_A_VEPU 425993 500 #define SRST_CORE_VEPU 425994 501 #define SRST_H_VEPU_PP 425995 502 #define SRST_A_VEPU_PP 425996 503 #define SRST_CORE_VEPU_DVBM 425997 504 #define SRST_P_VICAP_VEPU 425998 505 #define SRST_P_GPIO1 425999 506 /********Name=VEPUSOFTRST_CON01,Offset=0x1AA04********/ 507 #define SRST_GPIO1 426000 508 #define SRST_P_VEPU_IOC 426001 509 #define SRST_P_SPI0 426002 510 #define SRST_SPI0 426003 511 #define SRST_P_VEPU_CRU 426005 512 #define SRST_P_VEPU_SGRF 426006 513 #define SRST_P_VEPU_GRF 426007 514 #define SRST_UART_DETN_FLT 426008 515 /********Name=VOSOFTRST_CON00,Offset=0x1CA00********/ 516 #define SRST_A_VO_BIU 458755 517 #define SRST_H_VO_BIU 458756 518 #define SRST_H_RGA2E 458759 519 #define SRST_A_RGA2E 458760 520 #define SRST_CORE_RGA2E 458761 521 #define SRST_P_VO_GRF 458762 522 #define SRST_A_VOP_BIU 458764 523 #define SRST_H_VOP 458765 524 #define SRST_D_VOP 458766 525 #define SRST_A_VOP 458767 526 /********Name=VOSOFTRST_CON01,Offset=0x1CA04********/ 527 #define SRST_P_MAC_BIU 458774 528 #define SRST_A_MAC_BIU 458775 529 #define SRST_A_MAC 458776 530 #define SRST_P_VO_SGRF 458780 531 #define SRST_P_VO_CRU 458781 532 #define SRST_H_SDIO 458783 533 /********Name=VOSOFTRST_CON02,Offset=0x1CA08********/ 534 #define SRST_P_TSADC 458784 535 #define SRST_TSADC 458785 536 #define SRST_P_OTPC_NS 458787 537 #define SRST_SBPI_OTPC_NS 458789 538 #define SRST_USER_OTPC_NS 458790 539 #define SRST_P_OTPC_S 458791 540 #define SRST_SBPI_OTPC_S 458793 541 #define SRST_USER_OTPC_S 458794 542 #define SRST_OTPC_ARB 458795 543 #define SRST_MACPHY 458797 544 #define SRST_P_OTP_MASK 458798 545 #define SRST_PMC_OTP 458799 546 /********Name=VOSOFTRST_CON03,Offset=0x1CA0C********/ 547 #define SRST_P_GPIO2 458800 548 #define SRST_GPIO2 458801 549 #define SRST_P_VO_IOC 458802 550 /********Name=DDRSOFTRST_CON00,Offset=0x1EA00********/ 551 #define SRST_P_DDR_BIU 491522 552 #define SRST_P_DDRC 491525 553 #define SRST_P_DDRMON 491527 554 #define SRST_TIMER_DDRMON 491528 555 #define SRST_P_DFICTRL 491531 556 #define SRST_A_SYS_SHRM 491533 557 #define SRST_A_SHRM_NIU 491534 558 #define SRST_P_DDR_GRF 491535 559 /********Name=DDRSOFTRST_CON01,Offset=0x1EA04********/ 560 #define SRST_P_DDR_CRU 491536 561 #define SRST_P_DDR_HWLP 491538 562 #define SRST_P_DDRPHY 491539 563 /********Name=SUBDDRSOFTRST_CON00,Offset=0x1FA00********/ 564 #define SRST_MSCH_BIU 507904 565 #define SRST_A_DDRC 507905 566 #define SRST_CORE_DDRC 507907 567 #define SRST_DDRMON 507908 568 #define SRST_DFICTRL 507909 569 #define SRST_DDR_PHY 507910 570 571 #endif 572