1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 4 * Author: Joseph Chen <chenjh@rock-chips.com> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H 9 10 /* cru-clocks indices */ 11 12 /* core clocks */ 13 #define PLL_APLL 1 14 #define PLL_CPLL 2 15 #define PLL_GPLL 3 16 #define PLL_PPLL 4 17 #define PLL_DPLL 5 18 #define ARMCLK 6 19 20 #define XIN_OSC0_HALF 8 21 #define CLK_MATRIX_50M_SRC 9 22 #define CLK_MATRIX_100M_SRC 10 23 #define CLK_MATRIX_150M_SRC 11 24 #define CLK_MATRIX_200M_SRC 12 25 #define CLK_MATRIX_250M_SRC 13 26 #define CLK_MATRIX_300M_SRC 14 27 #define CLK_MATRIX_339M_SRC 15 28 #define CLK_MATRIX_400M_SRC 16 29 #define CLK_MATRIX_500M_SRC 17 30 #define CLK_MATRIX_600M_SRC 18 31 #define CLK_UART0_SRC 19 32 #define CLK_UART0_FRAC 20 33 #define SCLK_UART0 21 34 #define CLK_UART1_SRC 22 35 #define CLK_UART1_FRAC 23 36 #define SCLK_UART1 24 37 #define CLK_UART2_SRC 25 38 #define CLK_UART2_FRAC 26 39 #define SCLK_UART2 27 40 #define CLK_UART3_SRC 28 41 #define CLK_UART3_FRAC 29 42 #define SCLK_UART3 30 43 #define CLK_UART4_SRC 31 44 #define CLK_UART4_FRAC 32 45 #define SCLK_UART4 33 46 #define CLK_UART5_SRC 34 47 #define CLK_UART5_FRAC 35 48 #define SCLK_UART5 36 49 #define CLK_UART6_SRC 37 50 #define CLK_UART6_FRAC 38 51 #define SCLK_UART6 39 52 #define CLK_UART7_SRC 40 53 #define CLK_UART7_FRAC 41 54 #define SCLK_UART7 42 55 #define CLK_I2S0_2CH_SRC 43 56 #define CLK_I2S0_2CH_FRAC 44 57 #define MCLK_I2S0_2CH_SAI_SRC 45 58 #define CLK_I2S3_8CH_SRC 46 59 #define CLK_I2S3_8CH_FRAC 47 60 #define MCLK_I2S3_8CH_SAI_SRC 48 61 #define CLK_I2S1_8CH_SRC 49 62 #define CLK_I2S1_8CH_FRAC 50 63 #define MCLK_I2S1_8CH_SAI_SRC 51 64 #define CLK_I2S2_2CH_SRC 52 65 #define CLK_I2S2_2CH_FRAC 53 66 #define MCLK_I2S2_2CH_SAI_SRC 54 67 #define CLK_SPDIF_SRC 55 68 #define CLK_SPDIF_FRAC 56 69 #define MCLK_SPDIF_SRC 57 70 #define DCLK_VOP_SRC0 58 71 #define DCLK_VOP_SRC1 59 72 #define CLK_HSM 60 73 #define CLK_CORE_SRC_ACS 63 74 #define CLK_CORE_SRC_PVTMUX 65 75 #define CLK_CORE_SRC 66 76 #define CLK_CORE 67 77 #define ACLK_M_CORE_BIU 68 78 #define CLK_CORE_PVTPLL_SRC 69 79 #define PCLK_DBG 70 80 #define SWCLKTCK 71 81 #define CLK_SCANHS_CORE 72 82 #define CLK_SCANHS_ACLKM_CORE 73 83 #define CLK_SCANHS_PCLK_DBG 74 84 #define CLK_SCANHS_PCLK_CPU_BIU 76 85 #define PCLK_CPU_ROOT 77 86 #define PCLK_CORE_GRF 78 87 #define PCLK_DAPLITE_BIU 79 88 #define PCLK_CPU_BIU 80 89 #define CLK_REF_PVTPLL_CORE 81 90 #define ACLK_BUS_VOPGL_ROOT 85 91 #define ACLK_BUS_VOPGL_BIU 86 92 #define ACLK_BUS_H_ROOT 87 93 #define ACLK_BUS_H_BIU 88 94 #define ACLK_BUS_ROOT 89 95 #define HCLK_BUS_ROOT 90 96 #define PCLK_BUS_ROOT 91 97 #define ACLK_BUS_M_ROOT 92 98 #define ACLK_SYSMEM_BIU 93 99 #define CLK_TIMER_ROOT 95 100 #define ACLK_BUS_BIU 96 101 #define HCLK_BUS_BIU 97 102 #define PCLK_BUS_BIU 98 103 #define PCLK_DFT2APB 99 104 #define PCLK_BUS_GRF 100 105 #define ACLK_BUS_M_BIU 101 106 #define ACLK_GIC 102 107 #define ACLK_SPINLOCK 103 108 #define ACLK_DMAC 104 109 #define PCLK_TIMER 105 110 #define CLK_TIMER0 106 111 #define CLK_TIMER1 107 112 #define CLK_TIMER2 108 113 #define CLK_TIMER3 109 114 #define CLK_TIMER4 110 115 #define CLK_TIMER5 111 116 #define PCLK_JDBCK_DAP 112 117 #define CLK_JDBCK_DAP 113 118 #define PCLK_WDT_NS 114 119 #define TCLK_WDT_NS 115 120 #define HCLK_TRNG_NS 116 121 #define PCLK_UART0 117 122 #define PCLK_DMA2DDR 123 123 #define ACLK_DMA2DDR 124 124 #define PCLK_PWM0 126 125 #define CLK_PWM0 127 126 #define CLK_CAPTURE_PWM0 128 127 #define PCLK_PWM1 129 128 #define CLK_PWM1 130 129 #define CLK_CAPTURE_PWM1 131 130 #define PCLK_SCR 134 131 #define ACLK_DCF 135 132 #define PCLK_INTMUX 138 133 #define CLK_PPLL_I 141 134 #define CLK_PPLL_MUX 142 135 #define CLK_PPLL_100M_MATRIX 143 136 #define CLK_PPLL_50M_MATRIX 144 137 #define CLK_REF_PCIE_INNER_PHY 145 138 #define CLK_REF_PCIE_100M_PHY 146 139 #define ACLK_VPU_L_ROOT 147 140 #define CLK_GMAC1_VPU_25M 148 141 #define CLK_PPLL_125M_MATRIX 149 142 #define ACLK_VPU_ROOT 150 143 #define HCLK_VPU_ROOT 151 144 #define PCLK_VPU_ROOT 152 145 #define ACLK_VPU_BIU 153 146 #define HCLK_VPU_BIU 154 147 #define PCLK_VPU_BIU 155 148 #define ACLK_VPU 156 149 #define HCLK_VPU 157 150 #define PCLK_CRU_PCIE 158 151 #define PCLK_VPU_GRF 159 152 #define HCLK_SFC 160 153 #define SCLK_SFC 161 154 #define CCLK_SRC_EMMC 163 155 #define HCLK_EMMC 164 156 #define ACLK_EMMC 165 157 #define BCLK_EMMC 166 158 #define TCLK_EMMC 167 159 #define PCLK_GPIO1 168 160 #define DBCLK_GPIO1 169 161 #define ACLK_VPU_L_BIU 172 162 #define PCLK_VPU_IOC 173 163 #define HCLK_SAI_I2S0 174 164 #define MCLK_SAI_I2S0 175 165 #define HCLK_SAI_I2S2 176 166 #define MCLK_SAI_I2S2 177 167 #define PCLK_ACODEC 178 168 #define MCLK_ACODEC_TX 179 169 #define PCLK_GPIO3 186 170 #define DBCLK_GPIO3 187 171 #define PCLK_SPI1 189 172 #define CLK_SPI1 190 173 #define SCLK_IN_SPI1 191 174 #define PCLK_UART2 192 175 #define PCLK_UART5 194 176 #define PCLK_UART6 196 177 #define PCLK_UART7 198 178 #define PCLK_I2C3 200 179 #define CLK_I2C3 201 180 #define PCLK_I2C5 202 181 #define CLK_I2C5 203 182 #define PCLK_I2C6 204 183 #define CLK_I2C6 205 184 #define ACLK_MAC_VPU 206 185 #define PCLK_MAC_VPU 207 186 #define CLK_GMAC1_RMII_VPU 209 187 #define CLK_GMAC1_SRC_VPU 210 188 #define PCLK_PCIE 215 189 #define CLK_PCIE_AUX 216 190 #define ACLK_PCIE 217 191 #define HCLK_PCIE_SLV 218 192 #define HCLK_PCIE_DBI 219 193 #define PCLK_PCIE_PHY 220 194 #define PCLK_PIPE_GRF 221 195 #define CLK_PIPE_USB3OTG_COMBO 230 196 #define CLK_UTMI_USB3OTG 232 197 #define CLK_PCIE_PIPE_PHY 235 198 #define CCLK_SRC_SDIO0 240 199 #define HCLK_SDIO0 241 200 #define CCLK_SRC_SDIO1 244 201 #define HCLK_SDIO1 245 202 #define CLK_TS_0 246 203 #define CLK_TS_1 247 204 #define PCLK_CAN2 250 205 #define CLK_CAN2 251 206 #define PCLK_CAN3 252 207 #define CLK_CAN3 253 208 #define PCLK_SARADC 256 209 #define CLK_SARADC 257 210 #define PCLK_TSADC 258 211 #define CLK_TSADC 259 212 #define CLK_TSADC_TSEN 260 213 #define ACLK_USB3OTG 261 214 #define CLK_REF_USB3OTG 262 215 #define CLK_SUSPEND_USB3OTG 263 216 #define ACLK_GPU_ROOT 269 217 #define PCLK_GPU_ROOT 270 218 #define ACLK_GPU_BIU 271 219 #define PCLK_GPU_BIU 272 220 #define ACLK_GPU 273 221 #define CLK_GPU_PVTPLL_SRC 274 222 #define ACLK_GPU_MALI 275 223 #define HCLK_RKVENC_ROOT 281 224 #define ACLK_RKVENC_ROOT 282 225 #define PCLK_RKVENC_ROOT 283 226 #define HCLK_RKVENC_BIU 284 227 #define ACLK_RKVENC_BIU 285 228 #define PCLK_RKVENC_BIU 286 229 #define HCLK_RKVENC 287 230 #define ACLK_RKVENC 288 231 #define CLK_CORE_RKVENC 289 232 #define HCLK_SAI_I2S1 290 233 #define MCLK_SAI_I2S1 291 234 #define PCLK_I2C1 292 235 #define CLK_I2C1 293 236 #define PCLK_I2C0 294 237 #define CLK_I2C0 295 238 #define CLK_UART_JTAG 296 239 #define PCLK_SPI0 297 240 #define CLK_SPI0 298 241 #define SCLK_IN_SPI0 299 242 #define PCLK_GPIO4 300 243 #define DBCLK_GPIO4 301 244 #define PCLK_RKVENC_IOC 302 245 #define HCLK_SPDIF 308 246 #define MCLK_SPDIF 309 247 #define HCLK_PDM 310 248 #define MCLK_PDM 311 249 #define PCLK_UART1 315 250 #define PCLK_UART3 317 251 #define PCLK_RKVENC_GRF 319 252 #define PCLK_CAN0 320 253 #define CLK_CAN0 321 254 #define PCLK_CAN1 322 255 #define CLK_CAN1 323 256 #define ACLK_VO_ROOT 324 257 #define HCLK_VO_ROOT 325 258 #define PCLK_VO_ROOT 326 259 #define ACLK_VO_BIU 327 260 #define HCLK_VO_BIU 328 261 #define PCLK_VO_BIU 329 262 #define HCLK_RGA2E 330 263 #define ACLK_RGA2E 331 264 #define CLK_CORE_RGA2E 332 265 #define HCLK_VDPP 333 266 #define ACLK_VDPP 334 267 #define CLK_CORE_VDPP 335 268 #define PCLK_VO_GRF 336 269 #define PCLK_CRU 337 270 #define ACLK_VOP_ROOT 338 271 #define ACLK_VOP_BIU 339 272 #define HCLK_VOP 340 273 #define DCLK_VOP0 341 274 #define DCLK_VOP1 342 275 #define ACLK_VOP 343 276 #define PCLK_HDMI 344 277 #define CLK_SFR_HDMI 345 278 #define CLK_CEC_HDMI 346 279 #define CLK_SPDIF_HDMI 347 280 #define CLK_HDMIPHY_TMDSSRC 348 281 #define CLK_HDMIPHY_PREP 349 282 #define PCLK_HDMIPHY 352 283 #define HCLK_HDCP_KEY 354 284 #define ACLK_HDCP 355 285 #define HCLK_HDCP 356 286 #define PCLK_HDCP 357 287 #define HCLK_CVBS 358 288 #define DCLK_CVBS 359 289 #define DCLK_4X_CVBS 360 290 #define ACLK_JPEG_DECODER 361 291 #define HCLK_JPEG_DECODER 362 292 #define ACLK_VO_L_ROOT 375 293 #define ACLK_VO_L_BIU 376 294 #define ACLK_MAC_VO 377 295 #define PCLK_MAC_VO 378 296 #define CLK_GMAC0_SRC 379 297 #define CLK_GMAC0_RMII_50M 380 298 #define CLK_GMAC0_TX 381 299 #define CLK_GMAC0_RX 382 300 #define ACLK_JPEG_ROOT 385 301 #define ACLK_JPEG_BIU 386 302 #define HCLK_SAI_I2S3 387 303 #define MCLK_SAI_I2S3 388 304 #define CLK_MACPHY 398 305 #define PCLK_VCDCPHY 399 306 #define PCLK_GPIO2 404 307 #define DBCLK_GPIO2 405 308 #define PCLK_VO_IOC 406 309 #define CCLK_SRC_SDMMC0 407 310 #define HCLK_SDMMC0 408 311 #define PCLK_OTPC_NS 411 312 #define CLK_SBPI_OTPC_NS 412 313 #define CLK_USER_OTPC_NS 413 314 #define CLK_HDMIHDP0 415 315 #define HCLK_USBHOST 416 316 #define HCLK_USBHOST_ARB 417 317 #define CLK_USBHOST_OHCI 418 318 #define CLK_USBHOST_UTMI 419 319 #define PCLK_UART4 420 320 #define PCLK_I2C4 422 321 #define CLK_I2C4 423 322 #define PCLK_I2C7 424 323 #define CLK_I2C7 425 324 #define PCLK_USBPHY 426 325 #define CLK_REF_USBPHY 427 326 #define HCLK_RKVDEC_ROOT 433 327 #define ACLK_RKVDEC_ROOT_NDFT 434 328 #define PCLK_DDRPHY_CRU 435 329 #define HCLK_RKVDEC_BIU 436 330 #define ACLK_RKVDEC_BIU 437 331 #define ACLK_RKVDEC 439 332 #define HCLK_RKVDEC 440 333 #define CLK_HEVC_CA_RKVDEC 441 334 #define ACLK_RKVDEC_PVTMUX_ROOT 442 335 #define CLK_RKVDEC_PVTPLL_SRC 443 336 #define PCLK_DDR_ROOT 449 337 #define PCLK_DDR_BIU 450 338 #define PCLK_DDRC 451 339 #define PCLK_DDRMON 452 340 #define CLK_TIMER_DDRMON 453 341 #define PCLK_MSCH_BIU 454 342 #define PCLK_DDR_GRF 455 343 #define PCLK_DDR_HWLP 456 344 #define PCLK_DDRPHY 457 345 #define CLK_MSCH_BIU 463 346 #define ACLK_DDR_UPCTL 464 347 #define CLK_DDR_UPCTL 465 348 #define CLK_DDRMON 466 349 #define ACLK_DDR_SCRAMBLE 467 350 #define ACLK_SPLIT 468 351 #define CLK_DDRC_SRC 470 352 #define CLK_DDR_PHY 471 353 #define PCLK_OTPC_S 472 354 #define CLK_SBPI_OTPC_S 473 355 #define CLK_USER_OTPC_S 474 356 #define PCLK_KEYREADER 475 357 #define PCLK_BUS_SGRF 476 358 #define PCLK_STIMER 477 359 #define CLK_STIMER0 478 360 #define CLK_STIMER1 479 361 #define PCLK_WDT_S 480 362 #define TCLK_WDT_S 481 363 #define HCLK_TRNG_S 482 364 #define HCLK_BOOTROM 486 365 #define PCLK_DCF 487 366 #define ACLK_SYSMEM 488 367 #define HCLK_TSP 489 368 #define ACLK_TSP 490 369 #define CLK_CORE_TSP 491 370 #define CLK_OTPC_ARB 492 371 #define PCLK_OTP_MASK 493 372 #define CLK_PMC_OTP 494 373 #define PCLK_PMU_ROOT 495 374 #define HCLK_PMU_ROOT 496 375 #define PCLK_I2C2 497 376 #define CLK_I2C2 498 377 #define HCLK_PMU_BIU 500 378 #define PCLK_PMU_BIU 501 379 #define FCLK_MCU 502 380 #define RTC_CLK_MCU 504 381 #define PCLK_OSCCHK 505 382 #define CLK_PMU_MCU_JTAG 506 383 #define PCLK_PMU 508 384 #define PCLK_GPIO0 509 385 #define DBCLK_GPIO0 510 386 #define XIN_OSC0_DIV 511 387 #define CLK_DEEPSLOW 512 388 #define CLK_DDR_FAIL_SAFE 513 389 #define PCLK_PMU_HP_TIMER 514 390 #define CLK_PMU_HP_TIMER 515 391 #define CLK_PMU_32K_HP_TIMER 516 392 #define PCLK_PMU_IOC 517 393 #define PCLK_PMU_CRU 518 394 #define PCLK_PMU_GRF 519 395 #define PCLK_PMU_WDT 520 396 #define TCLK_PMU_WDT 521 397 #define PCLK_PMU_MAILBOX 522 398 #define PCLK_SCRKEYGEN 524 399 #define CLK_SCRKEYGEN 525 400 #define CLK_PVTM_OSCCHK 526 401 #define CLK_REFOUT 530 402 #define CLK_PVTM_PMU 532 403 #define PCLK_PVTM_PMU 533 404 #define PCLK_PMU_SGRF 534 405 #define HCLK_PMU_SRAM 535 406 #define CLK_UART0 536 407 #define CLK_UART1 537 408 #define CLK_UART2 538 409 #define CLK_UART3 539 410 #define CLK_UART4 540 411 #define CLK_UART5 541 412 #define CLK_UART6 542 413 #define CLK_UART7 543 414 #define MCLK_I2S0_2CH_SAI_SRC_PRE 544 415 #define MCLK_I2S1_8CH_SAI_SRC_PRE 545 416 #define MCLK_I2S2_2CH_SAI_SRC_PRE 546 417 #define MCLK_I2S3_8CH_SAI_SRC_PRE 547 418 #define MCLK_SDPDIF_SRC_PRE 548 419 #define CLK_NR_CLKS (MCLK_SDPDIF_SRC_PRE + 1) 420 421 /* grf-clocks indices */ 422 #define SCLK_SDMMC_DRV 1 423 #define SCLK_SDMMC_SAMPLE 2 424 #define SCLK_SDIO0_DRV 3 425 #define SCLK_SDIO0_SAMPLE 4 426 #define SCLK_SDIO1_DRV 5 427 #define SCLK_SDIO1_SAMPLE 6 428 #define CLK_NR_GRF_CLKS (SCLK_SDIO1_SAMPLE + 1) 429 430 /* scmi-clocks indices */ 431 #define SCMI_PCLK_KEYREADER 0 432 #define SCMI_HCLK_KLAD 1 433 #define SCMI_PCLK_KLAD 2 434 #define SCMI_HCLK_TRNG_S 3 435 #define SCMI_HCLK_CRYPTO_S 4 436 #define SCMI_PCLK_WDT_S 5 437 #define SCMI_TCLK_WDT_S 6 438 #define SCMI_PCLK_STIMER 7 439 #define SCMI_CLK_STIMER0 8 440 #define SCMI_CLK_STIMER1 9 441 #define SCMI_PCLK_OTP_MASK 10 442 #define SCMI_PCLK_OTPC_S 11 443 #define SCMI_CLK_SBPI_OTPC_S 12 444 #define SCMI_CLK_USER_OTPC_S 13 445 #define SCMI_CLK_PMC_OTP 14 446 #define SCMI_CLK_OTPC_ARB 15 447 #define SCMI_CLK_CORE_TSP 16 448 #define SCMI_ACLK_TSP 17 449 #define SCMI_HCLK_TSP 18 450 #define SCMI_PCLK_DCF 19 451 #define SCMI_CLK_DDR 20 452 #define SCMI_CLK_CPU 21 453 #define SCMI_CLK_GPU 22 454 #define SCMI_CORE_CRYPTO 23 455 #define SCMI_ACLK_CRYPTO 24 456 #define SCMI_PKA_CRYPTO 25 457 #define SCMI_HCLK_CRYPTO 26 458 #define SCMI_CORE_CRYPTO_S 27 459 #define SCMI_ACLK_CRYPTO_S 28 460 #define SCMI_PKA_CRYPTO_S 29 461 #define SCMI_CORE_KLAD 30 462 #define SCMI_ACLK_KLAD 31 463 #define SCMI_HCLK_TRNG 32 464 465 // CRU_SOFTRST_CON03(Offset:0xA0C) 466 #define SRST_NCOREPORESET0 0x00000030 467 #define SRST_NCOREPORESET1 0x00000031 468 #define SRST_NCOREPORESET2 0x00000032 469 #define SRST_NCOREPORESET3 0x00000033 470 #define SRST_NCORESET0 0x00000034 471 #define SRST_NCORESET1 0x00000035 472 #define SRST_NCORESET2 0x00000036 473 #define SRST_NCORESET3 0x00000037 474 #define SRST_NL2RESET 0x00000038 475 #define SRST_ARESETN_M_CORE_BIU 0x00000039 476 #define SRST_RESETN_CORE_CRYPTO 0x0000003A 477 478 // CRU_SOFTRST_CON05(Offset:0xA14) 479 #define SRST_PRESETN_DBG 0x0000005D 480 #define SRST_POTRESETN_DBG 0x0000005E 481 #define SRST_NTRESETN_DBG 0x0000005F 482 483 // CRU_SOFTRST_CON06(Offset:0xA18) 484 #define SRST_PRESETN_CORE_GRF 0x00000062 485 #define SRST_PRESETN_DAPLITE_BIU 0x00000063 486 #define SRST_PRESETN_CPU_BIU 0x00000064 487 #define SRST_RESETN_REF_PVTPLL_CORE 0x00000067 488 489 // CRU_SOFTRST_CON08(Offset:0xA20) 490 #define SRST_ARESETN_BUS_VOPGL_BIU 0x00000081 491 #define SRST_ARESETN_BUS_H_BIU 0x00000083 492 #define SRST_ARESETN_SYSMEM_BIU 0x00000088 493 #define SRST_ARESETN_BUS_BIU 0x0000008A 494 #define SRST_HRESETN_BUS_BIU 0x0000008B 495 #define SRST_PRESETN_BUS_BIU 0x0000008C 496 #define SRST_PRESETN_DFT2APB 0x0000008D 497 #define SRST_PRESETN_BUS_GRF 0x0000008F 498 499 // CRU_SOFTRST_CON09(Offset:0xA24) 500 #define SRST_ARESETN_BUS_M_BIU 0x00000090 501 #define SRST_ARESETN_GIC 0x00000091 502 #define SRST_ARESETN_SPINLOCK 0x00000092 503 #define SRST_ARESETN_DMAC 0x00000094 504 #define SRST_PRESETN_TIMER 0x00000095 505 #define SRST_RESETN_TIMER0 0x00000096 506 #define SRST_RESETN_TIMER1 0x00000097 507 #define SRST_RESETN_TIMER2 0x00000098 508 #define SRST_RESETN_TIMER3 0x00000099 509 #define SRST_RESETN_TIMER4 0x0000009A 510 #define SRST_RESETN_TIMER5 0x0000009B 511 #define SRST_PRESETN_JDBCK_DAP 0x0000009C 512 #define SRST_RESETN_JDBCK_DAP 0x0000009D 513 #define SRST_PRESETN_WDT_NS 0x0000009F 514 515 // CRU_SOFTRST_CON10(Offset:0xA28) 516 #define SRST_TRESETN_WDT_NS 0x000000A0 517 #define SRST_HRESETN_TRNG_NS 0x000000A3 518 #define SRST_PRESETN_UART0 0x000000A7 519 #define SRST_SRESETN_UART0 0x000000A8 520 #define SRST_RESETN_PKA_CRYPTO 0x000000AA 521 #define SRST_ARESETN_CRYPTO 0x000000AB 522 #define SRST_HRESETN_CRYPTO 0x000000AC 523 #define SRST_PRESETN_DMA2DDR 0x000000AD 524 #define SRST_ARESETN_DMA2DDR 0x000000AE 525 526 // CRU_SOFTRST_CON11(Offset:0xA2C) 527 #define SRST_PRESETN_PWM0 0x000000B4 528 #define SRST_RESETN_PWM0 0x000000B5 529 #define SRST_PRESETN_PWM1 0x000000B7 530 #define SRST_RESETN_PWM1 0x000000B8 531 #define SRST_PRESETN_SCR 0x000000BA 532 #define SRST_ARESETN_DCF 0x000000BB 533 #define SRST_PRESETN_INTMUX 0x000000BC 534 535 // CRU_SOFTRST_CON25(Offset:0xA64) 536 #define SRST_ARESETN_VPU_BIU 0x00000196 537 #define SRST_HRESETN_VPU_BIU 0x00000197 538 #define SRST_PRESETN_VPU_BIU 0x00000198 539 #define SRST_ARESETN_VPU 0x00000199 540 #define SRST_HRESETN_VPU 0x0000019A 541 #define SRST_PRESETN_CRU_PCIE 0x0000019B 542 #define SRST_PRESETN_VPU_GRF 0x0000019C 543 #define SRST_HRESETN_SFC 0x0000019D 544 #define SRST_SRESETN_SFC 0x0000019E 545 #define SRST_CRESETN_EMMC 0x0000019F 546 547 // CRU_SOFTRST_CON26(Offset:0xA68) 548 #define SRST_HRESETN_EMMC 0x000001A0 549 #define SRST_ARESETN_EMMC 0x000001A1 550 #define SRST_BRESETN_EMMC 0x000001A2 551 #define SRST_TRESETN_EMMC 0x000001A3 552 #define SRST_PRESETN_GPIO1 0x000001A4 553 #define SRST_DBRESETN_GPIO1 0x000001A5 554 #define SRST_ARESETN_VPU_L_BIU 0x000001A6 555 #define SRST_PRESETN_VPU_IOC 0x000001A8 556 #define SRST_HRESETN_SAI_I2S0 0x000001A9 557 #define SRST_MRESETN_SAI_I2S0 0x000001AA 558 #define SRST_HRESETN_SAI_I2S2 0x000001AB 559 #define SRST_MRESETN_SAI_I2S2 0x000001AC 560 #define SRST_PRESETN_ACODEC 0x000001AD 561 562 // CRU_SOFTRST_CON27(Offset:0xA6C) 563 #define SRST_PRESETN_GPIO3 0x000001B0 564 #define SRST_DBRESETN_GPIO3 0x000001B1 565 #define SRST_PRESETN_SPI1 0x000001B4 566 #define SRST_RESETN_SPI1 0x000001B5 567 #define SRST_PRESETN_UART2 0x000001B7 568 #define SRST_SRESETN_UART2 0x000001B8 569 #define SRST_PRESETN_UART5 0x000001B9 570 #define SRST_SRESETN_UART5 0x000001BA 571 #define SRST_PRESETN_UART6 0x000001BB 572 #define SRST_SRESETN_UART6 0x000001BC 573 #define SRST_PRESETN_UART7 0x000001BD 574 #define SRST_SRESETN_UART7 0x000001BE 575 #define SRST_PRESETN_I2C3 0x000001BF 576 577 // CRU_SOFTRST_CON28(Offset:0xA70) 578 #define SRST_RESETN_I2C3 0x000001C0 579 #define SRST_PRESETN_I2C5 0x000001C1 580 #define SRST_RESETN_I2C5 0x000001C2 581 #define SRST_PRESETN_I2C6 0x000001C3 582 #define SRST_RESETN_I2C6 0x000001C4 583 #define SRST_ARESETN_MAC 0x000001C5 584 585 // CRU_SOFTRST_CON30(Offset:0xA78) 586 #define SRST_PRESETN_PCIE 0x000001E1 587 #define SRST_RESETN_PCIE_PIPE_PHY 0x000001E2 588 #define SRST_RESETN_PCIE_POWER_UP 0x000001E3 589 #define SRST_PRESETN_PCIE_PHY 0x000001E6 590 #define SRST_PRESETN_PIPE_GRF 0x000001E7 591 592 // CRU_SOFTRST_CON32(Offset:0xA80) 593 #define SRST_HRESETN_SDIO0 0x00000202 594 #define SRST_HRESETN_SDIO1 0x00000204 595 #define SRST_RESETN_TS_0 0x00000205 596 #define SRST_RESETN_TS_1 0x00000206 597 #define SRST_PRESETN_CAN2 0x00000207 598 #define SRST_RESETN_CAN2 0x00000208 599 #define SRST_PRESETN_CAN3 0x00000209 600 #define SRST_RESETN_CAN3 0x0000020A 601 #define SRST_PRESETN_SARADC 0x0000020B 602 #define SRST_RESETN_SARADC 0x0000020C 603 #define SRST_RESETN_SARADC_PHY 0x0000020D 604 #define SRST_PRESETN_TSADC 0x0000020E 605 #define SRST_RESETN_TSADC 0x0000020F 606 607 // CRU_SOFTRST_CON33(Offset:0xA84) 608 #define SRST_ARESETN_USB3OTG 0x00000211 609 610 // CRU_SOFTRST_CON34(Offset:0xA88) 611 #define SRST_ARESETN_GPU_BIU 0x00000223 612 #define SRST_PRESETN_GPU_BIU 0x00000225 613 #define SRST_ARESETN_GPU 0x00000228 614 #define SRST_RESETN_REF_PVTPLL_GPU 0x00000229 615 616 // CRU_SOFTRST_CON36(Offset:0xA90) 617 #define SRST_HRESETN_RKVENC_BIU 0x00000243 618 #define SRST_ARESETN_RKVENC_BIU 0x00000244 619 #define SRST_PRESETN_RKVENC_BIU 0x00000245 620 #define SRST_HRESETN_RKVENC 0x00000246 621 #define SRST_ARESETN_RKVENC 0x00000247 622 #define SRST_RESETN_CORE_RKVENC 0x00000248 623 #define SRST_HRESETN_SAI_I2S1 0x00000249 624 #define SRST_MRESETN_SAI_I2S1 0x0000024A 625 #define SRST_PRESETN_I2C1 0x0000024B 626 #define SRST_RESETN_I2C1 0x0000024C 627 #define SRST_PRESETN_I2C0 0x0000024D 628 #define SRST_RESETN_I2C0 0x0000024E 629 630 // CRU_SOFTRST_CON37(Offset:0xA94) 631 #define SRST_PRESETN_SPI0 0x00000252 632 #define SRST_RESETN_SPI0 0x00000253 633 #define SRST_PRESETN_GPIO4 0x00000258 634 #define SRST_DBRESETN_GPIO4 0x00000259 635 #define SRST_PRESETN_RKVENC_IOC 0x0000025A 636 #define SRST_HRESETN_SPDIF 0x0000025E 637 #define SRST_MRESETN_SPDIF 0x0000025F 638 639 // CRU_SOFTRST_CON38(Offset:0xA98) 640 #define SRST_HRESETN_PDM 0x00000260 641 #define SRST_MRESETN_PDM 0x00000261 642 #define SRST_PRESETN_UART1 0x00000262 643 #define SRST_SRESETN_UART1 0x00000263 644 #define SRST_PRESETN_UART3 0x00000264 645 #define SRST_SRESETN_UART3 0x00000265 646 #define SRST_PRESETN_RKVENC_GRF 0x00000266 647 #define SRST_PRESETN_CAN0 0x00000267 648 #define SRST_RESETN_CAN0 0x00000268 649 #define SRST_PRESETN_CAN1 0x00000269 650 #define SRST_RESETN_CAN1 0x0000026A 651 652 // CRU_SOFTRST_CON39(Offset:0xA9C) 653 #define SRST_ARESETN_VO_BIU 0x00000273 654 #define SRST_HRESETN_VO_BIU 0x00000274 655 #define SRST_PRESETN_VO_BIU 0x00000275 656 #define SRST_HRESETN_RGA2E 0x00000277 657 #define SRST_ARESETN_RGA2E 0x00000278 658 #define SRST_RESETN_CORE_RGA2E 0x00000279 659 #define SRST_HRESETN_VDPP 0x0000027A 660 #define SRST_ARESETN_VDPP 0x0000027B 661 #define SRST_RESETN_CORE_VDPP 0x0000027C 662 #define SRST_PRESETN_VO_GRF 0x0000027D 663 #define SRST_PRESETN_CRU 0x0000027F 664 665 // CRU_SOFTRST_CON40(Offset:0xAA0) 666 #define SRST_ARESETN_VOP_BIU 0x00000281 667 #define SRST_HRESETN_VOP 0x00000282 668 #define SRST_DRESETN_VOP0 0x00000283 669 #define SRST_DRESETN_VOP1 0x00000284 670 #define SRST_ARESETN_VOP 0x00000285 671 #define SRST_PRESETN_HDMI 0x00000286 672 #define SRST_HDMI_RESETN 0x00000287 673 #define SRST_PRESETN_HDMIPHY 0x0000028E 674 #define SRST_HRESETN_HDCP_KEY 0x0000028F 675 676 // CRU_SOFTRST_CON41(Offset:0xAA4) 677 #define SRST_ARESETN_HDCP 0x00000290 678 #define SRST_HRESETN_HDCP 0x00000291 679 #define SRST_PRESETN_HDCP 0x00000292 680 #define SRST_HRESETN_CVBS 0x00000293 681 #define SRST_DRESETN_CVBS_VOP 0x00000294 682 #define SRST_DRESETN_4X_CVBS_VOP 0x00000295 683 #define SRST_ARESETN_JPEG_DECODER 0x00000296 684 #define SRST_HRESETN_JPEG_DECODER 0x00000297 685 #define SRST_ARESETN_VO_L_BIU 0x00000299 686 #define SRST_ARESETN_MAC_VO 0x0000029A 687 688 // CRU_SOFTRST_CON42(Offset:0xAA8) 689 #define SRST_ARESETN_JPEG_BIU 0x000002A0 690 #define SRST_HRESETN_SAI_I2S3 0x000002A1 691 #define SRST_MRESETN_SAI_I2S3 0x000002A2 692 #define SRST_RESETN_MACPHY 0x000002A3 693 #define SRST_PRESETN_VCDCPHY 0x000002A4 694 #define SRST_PRESETN_GPIO2 0x000002A5 695 #define SRST_DBRESETN_GPIO2 0x000002A6 696 #define SRST_PRESETN_VO_IOC 0x000002A7 697 #define SRST_HRESETN_SDMMC0 0x000002A9 698 #define SRST_PRESETN_OTPC_NS 0x000002AB 699 #define SRST_RESETN_SBPI_OTPC_NS 0x000002AC 700 #define SRST_RESETN_USER_OTPC_NS 0x000002AD 701 702 // CRU_SOFTRST_CON43(Offset:0xAAC) 703 #define SRST_RESETN_HDMIHDP0 0x000002B2 704 #define SRST_HRESETN_USBHOST 0x000002B3 705 #define SRST_HRESETN_USBHOST_ARB 0x000002B4 706 #define SRST_RESETN_HOST_UTMI 0x000002B6 707 #define SRST_PRESETN_UART4 0x000002B7 708 #define SRST_SRESETN_UART4 0x000002B8 709 #define SRST_PRESETN_I2C4 0x000002B9 710 #define SRST_RESETN_I2C4 0x000002BA 711 #define SRST_PRESETN_I2C7 0x000002BB 712 #define SRST_RESETN_I2C7 0x000002BC 713 #define SRST_PRESETN_USBPHY 0x000002BD 714 #define SRST_RESETN_USBPHY_POR 0x000002BE 715 #define SRST_RESETN_USBPHY_OTG 0x000002BF 716 717 // CRU_SOFTRST_CON44(Offset:0xAB0) 718 #define SRST_RESETN_USBPHY_HOST 0x000002C0 719 #define SRST_PRESETN_DDRPHY_CRU 0x000002C4 720 #define SRST_HRESETN_RKVDEC_BIU 0x000002C6 721 #define SRST_ARESETN_RKVDEC_BIU 0x000002C7 722 #define SRST_ARESETN_RKVDEC 0x000002C8 723 #define SRST_HRESETN_RKVDEC 0x000002C9 724 #define SRST_RESETN_HEVC_CA_RKVDEC 0x000002CB 725 #define SRST_RESETN_REF_PVTPLL_RKVDEC 0x000002CC 726 727 // CRU_SOFTRST_CON45(Offset:0xAB4) 728 #define SRST_PRESETN_DDR_BIU 0x000002D1 729 #define SRST_PRESETN_DDRC 0x000002D2 730 #define SRST_PRESETN_DDRMON 0x000002D3 731 #define SRST_RESETN_TIMER_DDRMON 0x000002D4 732 #define SRST_PRESETN_MSCH_BIU 0x000002D5 733 #define SRST_PRESETN_DDR_GRF 0x000002D6 734 #define SRST_PRESETN_DDR_HWLP 0x000002D8 735 #define SRST_PRESETN_DDRPHY 0x000002D9 736 #define SRST_RESETN_MSCH_BIU 0x000002DA 737 #define SRST_ARESETN_DDR_UPCTL 0x000002DB 738 #define SRST_RESETN_DDR_UPCTL 0x000002DC 739 #define SRST_RESETN_DDRMON 0x000002DD 740 #define SRST_ARESETN_DDR_SCRAMBLE 0x000002DE 741 #define SRST_ARESETN_SPLIT 0x000002DF 742 743 // CRU_SOFTRST_CON46(Offset:0xAB8) 744 #define SRST_RESETN_DDR_PHY 0x000002E0 745 746 #endif 747 748