1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 */
5 #include <linux/kernel.h>
6 #include <linux/serial_reg.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/pci.h>
10 #include <linux/console.h>
11 #include <linux/serial_core.h>
12 #include <linux/tty.h>
13 #include <linux/tty_flip.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/dmi.h>
17 #include <linux/nmi.h>
18 #include <linux/delay.h>
19 #include <linux/of.h>
20
21 #include <linux/debugfs.h>
22 #include <linux/dmaengine.h>
23 #include <linux/pch_dma.h>
24
25 enum {
26 PCH_UART_HANDLED_RX_INT_SHIFT,
27 PCH_UART_HANDLED_TX_INT_SHIFT,
28 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
29 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
30 PCH_UART_HANDLED_MS_INT_SHIFT,
31 PCH_UART_HANDLED_LS_INT_SHIFT,
32 };
33
34 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
35
36 /* Set the max number of UART port
37 * Intel EG20T PCH: 4 port
38 * LAPIS Semiconductor ML7213 IOH: 3 port
39 * LAPIS Semiconductor ML7223 IOH: 2 port
40 */
41 #define PCH_UART_NR 4
42
43 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
44 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
45 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
46 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
47 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
48 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
49 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
50
51 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
52
53 #define PCH_UART_RBR 0x00
54 #define PCH_UART_THR 0x00
55
56 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
57 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
58 #define PCH_UART_IER_ERBFI 0x00000001
59 #define PCH_UART_IER_ETBEI 0x00000002
60 #define PCH_UART_IER_ELSI 0x00000004
61 #define PCH_UART_IER_EDSSI 0x00000008
62
63 #define PCH_UART_IIR_IP 0x00000001
64 #define PCH_UART_IIR_IID 0x00000006
65 #define PCH_UART_IIR_MSI 0x00000000
66 #define PCH_UART_IIR_TRI 0x00000002
67 #define PCH_UART_IIR_RRI 0x00000004
68 #define PCH_UART_IIR_REI 0x00000006
69 #define PCH_UART_IIR_TOI 0x00000008
70 #define PCH_UART_IIR_FIFO256 0x00000020
71 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
72 #define PCH_UART_IIR_FE 0x000000C0
73
74 #define PCH_UART_FCR_FIFOE 0x00000001
75 #define PCH_UART_FCR_RFR 0x00000002
76 #define PCH_UART_FCR_TFR 0x00000004
77 #define PCH_UART_FCR_DMS 0x00000008
78 #define PCH_UART_FCR_FIFO256 0x00000020
79 #define PCH_UART_FCR_RFTL 0x000000C0
80
81 #define PCH_UART_FCR_RFTL1 0x00000000
82 #define PCH_UART_FCR_RFTL64 0x00000040
83 #define PCH_UART_FCR_RFTL128 0x00000080
84 #define PCH_UART_FCR_RFTL224 0x000000C0
85 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
86 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
87 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
88 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
89 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
90 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
91 #define PCH_UART_FCR_RFTL_SHIFT 6
92
93 #define PCH_UART_LCR_WLS 0x00000003
94 #define PCH_UART_LCR_STB 0x00000004
95 #define PCH_UART_LCR_PEN 0x00000008
96 #define PCH_UART_LCR_EPS 0x00000010
97 #define PCH_UART_LCR_SP 0x00000020
98 #define PCH_UART_LCR_SB 0x00000040
99 #define PCH_UART_LCR_DLAB 0x00000080
100 #define PCH_UART_LCR_NP 0x00000000
101 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN
102 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
103 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
104 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
105 PCH_UART_LCR_SP)
106
107 #define PCH_UART_LCR_5BIT 0x00000000
108 #define PCH_UART_LCR_6BIT 0x00000001
109 #define PCH_UART_LCR_7BIT 0x00000002
110 #define PCH_UART_LCR_8BIT 0x00000003
111
112 #define PCH_UART_MCR_DTR 0x00000001
113 #define PCH_UART_MCR_RTS 0x00000002
114 #define PCH_UART_MCR_OUT 0x0000000C
115 #define PCH_UART_MCR_LOOP 0x00000010
116 #define PCH_UART_MCR_AFE 0x00000020
117
118 #define PCH_UART_LSR_DR 0x00000001
119 #define PCH_UART_LSR_ERR (1<<7)
120
121 #define PCH_UART_MSR_DCTS 0x00000001
122 #define PCH_UART_MSR_DDSR 0x00000002
123 #define PCH_UART_MSR_TERI 0x00000004
124 #define PCH_UART_MSR_DDCD 0x00000008
125 #define PCH_UART_MSR_CTS 0x00000010
126 #define PCH_UART_MSR_DSR 0x00000020
127 #define PCH_UART_MSR_RI 0x00000040
128 #define PCH_UART_MSR_DCD 0x00000080
129 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
130 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
131
132 #define PCH_UART_DLL 0x00
133 #define PCH_UART_DLM 0x01
134
135 #define PCH_UART_BRCSR 0x0E
136
137 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
138 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
139 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
140 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
141 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
142
143 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
144 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
145 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
146 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
147 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
148 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
149 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
150 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
151 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
152 #define PCH_UART_HAL_STB1 0
153 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
154
155 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
156 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
157 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
158 PCH_UART_HAL_CLR_RX_FIFO)
159
160 #define PCH_UART_HAL_DMA_MODE0 0
161 #define PCH_UART_HAL_FIFO_DIS 0
162 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
163 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
164 PCH_UART_FCR_FIFO256)
165 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
166 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
167 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
168 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
169 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
170 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
171 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
172 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
173 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
174 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
175 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
176 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
177 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
178 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
179
180 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
181 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
182 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
183 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
184 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
185
186 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
187 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
188 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
189 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
190 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
191
192 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
193
194 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */
195 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */
196 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */
197 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */
198 #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */
199 #define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */
200
201 struct pch_uart_buffer {
202 unsigned char *buf;
203 int size;
204 };
205
206 struct eg20t_port {
207 struct uart_port port;
208 int port_type;
209 void __iomem *membase;
210 resource_size_t mapbase;
211 unsigned int iobase;
212 struct pci_dev *pdev;
213 int fifo_size;
214 unsigned int uartclk;
215 int start_tx;
216 int start_rx;
217 int tx_empty;
218 int trigger;
219 int trigger_level;
220 struct pch_uart_buffer rxbuf;
221 unsigned int dmsr;
222 unsigned int fcr;
223 unsigned int mcr;
224 unsigned int use_dma;
225 struct dma_async_tx_descriptor *desc_tx;
226 struct dma_async_tx_descriptor *desc_rx;
227 struct pch_dma_slave param_tx;
228 struct pch_dma_slave param_rx;
229 struct dma_chan *chan_tx;
230 struct dma_chan *chan_rx;
231 struct scatterlist *sg_tx_p;
232 int nent;
233 int orig_nent;
234 struct scatterlist sg_rx;
235 int tx_dma_use;
236 void *rx_buf_virt;
237 dma_addr_t rx_buf_dma;
238
239 struct dentry *debugfs;
240 #define IRQ_NAME_SIZE 17
241 char irq_name[IRQ_NAME_SIZE];
242
243 /* protect the eg20t_port private structure and io access to membase */
244 spinlock_t lock;
245 };
246
247 /**
248 * struct pch_uart_driver_data - private data structure for UART-DMA
249 * @port_type: The type of UART port
250 * @line_no: UART port line number (0, 1, 2...)
251 */
252 struct pch_uart_driver_data {
253 int port_type;
254 int line_no;
255 };
256
257 enum pch_uart_num_t {
258 pch_et20t_uart0 = 0,
259 pch_et20t_uart1,
260 pch_et20t_uart2,
261 pch_et20t_uart3,
262 pch_ml7213_uart0,
263 pch_ml7213_uart1,
264 pch_ml7213_uart2,
265 pch_ml7223_uart0,
266 pch_ml7223_uart1,
267 pch_ml7831_uart0,
268 pch_ml7831_uart1,
269 };
270
271 static struct pch_uart_driver_data drv_dat[] = {
272 [pch_et20t_uart0] = {PORT_PCH_8LINE, 0},
273 [pch_et20t_uart1] = {PORT_PCH_2LINE, 1},
274 [pch_et20t_uart2] = {PORT_PCH_2LINE, 2},
275 [pch_et20t_uart3] = {PORT_PCH_2LINE, 3},
276 [pch_ml7213_uart0] = {PORT_PCH_8LINE, 0},
277 [pch_ml7213_uart1] = {PORT_PCH_2LINE, 1},
278 [pch_ml7213_uart2] = {PORT_PCH_2LINE, 2},
279 [pch_ml7223_uart0] = {PORT_PCH_8LINE, 0},
280 [pch_ml7223_uart1] = {PORT_PCH_2LINE, 1},
281 [pch_ml7831_uart0] = {PORT_PCH_8LINE, 0},
282 [pch_ml7831_uart1] = {PORT_PCH_2LINE, 1},
283 };
284
285 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
286 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
287 #endif
288 static unsigned int default_baud = 9600;
289 static unsigned int user_uartclk = 0;
290 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
291 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
292 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
293 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
294
295 #ifdef CONFIG_DEBUG_FS
296
297 #define PCH_REGS_BUFSIZE 1024
298
299
port_show_regs(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)300 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
301 size_t count, loff_t *ppos)
302 {
303 struct eg20t_port *priv = file->private_data;
304 char *buf;
305 u32 len = 0;
306 ssize_t ret;
307 unsigned char lcr;
308
309 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
310 if (!buf)
311 return 0;
312
313 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
314 "PCH EG20T port[%d] regs:\n", priv->port.line);
315
316 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
317 "=================================\n");
318 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
319 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
320 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
321 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
322 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
323 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
324 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
325 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
326 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
327 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
328 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
329 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
330 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
331 "BRCSR: \t0x%02x\n",
332 ioread8(priv->membase + PCH_UART_BRCSR));
333
334 lcr = ioread8(priv->membase + UART_LCR);
335 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
336 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
337 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
338 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
339 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
340 iowrite8(lcr, priv->membase + UART_LCR);
341
342 if (len > PCH_REGS_BUFSIZE)
343 len = PCH_REGS_BUFSIZE;
344
345 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
346 kfree(buf);
347 return ret;
348 }
349
350 static const struct file_operations port_regs_ops = {
351 .owner = THIS_MODULE,
352 .open = simple_open,
353 .read = port_show_regs,
354 .llseek = default_llseek,
355 };
356 #endif /* CONFIG_DEBUG_FS */
357
358 static const struct dmi_system_id pch_uart_dmi_table[] = {
359 {
360 .ident = "CM-iTC",
361 {
362 DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
363 },
364 (void *)CMITC_UARTCLK,
365 },
366 {
367 .ident = "FRI2",
368 {
369 DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
370 },
371 (void *)FRI2_64_UARTCLK,
372 },
373 {
374 .ident = "Fish River Island II",
375 {
376 DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
377 },
378 (void *)FRI2_48_UARTCLK,
379 },
380 {
381 .ident = "COMe-mTT",
382 {
383 DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
384 },
385 (void *)NTC1_UARTCLK,
386 },
387 {
388 .ident = "nanoETXexpress-TT",
389 {
390 DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
391 },
392 (void *)NTC1_UARTCLK,
393 },
394 {
395 .ident = "MinnowBoard",
396 {
397 DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
398 },
399 (void *)MINNOW_UARTCLK,
400 },
401 { }
402 };
403
404 /* Return UART clock, checking for board specific clocks. */
pch_uart_get_uartclk(void)405 static unsigned int pch_uart_get_uartclk(void)
406 {
407 const struct dmi_system_id *d;
408
409 if (user_uartclk)
410 return user_uartclk;
411
412 d = dmi_first_match(pch_uart_dmi_table);
413 if (d)
414 return (unsigned long)d->driver_data;
415
416 return DEFAULT_UARTCLK;
417 }
418
pch_uart_hal_enable_interrupt(struct eg20t_port * priv,unsigned int flag)419 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
420 unsigned int flag)
421 {
422 u8 ier = ioread8(priv->membase + UART_IER);
423 ier |= flag & PCH_UART_IER_MASK;
424 iowrite8(ier, priv->membase + UART_IER);
425 }
426
pch_uart_hal_disable_interrupt(struct eg20t_port * priv,unsigned int flag)427 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
428 unsigned int flag)
429 {
430 u8 ier = ioread8(priv->membase + UART_IER);
431 ier &= ~(flag & PCH_UART_IER_MASK);
432 iowrite8(ier, priv->membase + UART_IER);
433 }
434
pch_uart_hal_set_line(struct eg20t_port * priv,unsigned int baud,unsigned int parity,unsigned int bits,unsigned int stb)435 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
436 unsigned int parity, unsigned int bits,
437 unsigned int stb)
438 {
439 unsigned int dll, dlm, lcr;
440 int div;
441
442 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
443 if (div < 0 || USHRT_MAX <= div) {
444 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
445 return -EINVAL;
446 }
447
448 dll = (unsigned int)div & 0x00FFU;
449 dlm = ((unsigned int)div >> 8) & 0x00FFU;
450
451 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
452 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
453 return -EINVAL;
454 }
455
456 if (bits & ~PCH_UART_LCR_WLS) {
457 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
458 return -EINVAL;
459 }
460
461 if (stb & ~PCH_UART_LCR_STB) {
462 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
463 return -EINVAL;
464 }
465
466 lcr = parity;
467 lcr |= bits;
468 lcr |= stb;
469
470 dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
471 __func__, baud, div, lcr, jiffies);
472 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
473 iowrite8(dll, priv->membase + PCH_UART_DLL);
474 iowrite8(dlm, priv->membase + PCH_UART_DLM);
475 iowrite8(lcr, priv->membase + UART_LCR);
476
477 return 0;
478 }
479
pch_uart_hal_fifo_reset(struct eg20t_port * priv,unsigned int flag)480 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
481 unsigned int flag)
482 {
483 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
484 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
485 __func__, flag);
486 return -EINVAL;
487 }
488
489 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
490 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
491 priv->membase + UART_FCR);
492 iowrite8(priv->fcr, priv->membase + UART_FCR);
493
494 return 0;
495 }
496
pch_uart_hal_set_fifo(struct eg20t_port * priv,unsigned int dmamode,unsigned int fifo_size,unsigned int trigger)497 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
498 unsigned int dmamode,
499 unsigned int fifo_size, unsigned int trigger)
500 {
501 u8 fcr;
502
503 if (dmamode & ~PCH_UART_FCR_DMS) {
504 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
505 __func__, dmamode);
506 return -EINVAL;
507 }
508
509 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
510 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
511 __func__, fifo_size);
512 return -EINVAL;
513 }
514
515 if (trigger & ~PCH_UART_FCR_RFTL) {
516 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
517 __func__, trigger);
518 return -EINVAL;
519 }
520
521 switch (priv->fifo_size) {
522 case 256:
523 priv->trigger_level =
524 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
525 break;
526 case 64:
527 priv->trigger_level =
528 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
529 break;
530 case 16:
531 priv->trigger_level =
532 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
533 break;
534 default:
535 priv->trigger_level =
536 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
537 break;
538 }
539 fcr =
540 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
541 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
542 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
543 priv->membase + UART_FCR);
544 iowrite8(fcr, priv->membase + UART_FCR);
545 priv->fcr = fcr;
546
547 return 0;
548 }
549
pch_uart_hal_get_modem(struct eg20t_port * priv)550 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
551 {
552 unsigned int msr = ioread8(priv->membase + UART_MSR);
553 priv->dmsr = msr & PCH_UART_MSR_DELTA;
554 return (u8)msr;
555 }
556
pch_uart_hal_write(struct eg20t_port * priv,const unsigned char * buf,int tx_size)557 static void pch_uart_hal_write(struct eg20t_port *priv,
558 const unsigned char *buf, int tx_size)
559 {
560 int i;
561 unsigned int thr;
562
563 for (i = 0; i < tx_size;) {
564 thr = buf[i++];
565 iowrite8(thr, priv->membase + PCH_UART_THR);
566 }
567 }
568
pch_uart_hal_read(struct eg20t_port * priv,unsigned char * buf,int rx_size)569 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
570 int rx_size)
571 {
572 int i;
573 u8 rbr, lsr;
574 struct uart_port *port = &priv->port;
575
576 lsr = ioread8(priv->membase + UART_LSR);
577 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
578 i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
579 lsr = ioread8(priv->membase + UART_LSR)) {
580 rbr = ioread8(priv->membase + PCH_UART_RBR);
581
582 if (lsr & UART_LSR_BI) {
583 port->icount.brk++;
584 if (uart_handle_break(port))
585 continue;
586 }
587 if (uart_handle_sysrq_char(port, rbr))
588 continue;
589
590 buf[i++] = rbr;
591 }
592 return i;
593 }
594
pch_uart_hal_get_iid(struct eg20t_port * priv)595 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
596 {
597 return ioread8(priv->membase + UART_IIR) &\
598 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
599 }
600
pch_uart_hal_get_line_status(struct eg20t_port * priv)601 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
602 {
603 return ioread8(priv->membase + UART_LSR);
604 }
605
pch_uart_hal_set_break(struct eg20t_port * priv,int on)606 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
607 {
608 unsigned int lcr;
609
610 lcr = ioread8(priv->membase + UART_LCR);
611 if (on)
612 lcr |= PCH_UART_LCR_SB;
613 else
614 lcr &= ~PCH_UART_LCR_SB;
615
616 iowrite8(lcr, priv->membase + UART_LCR);
617 }
618
push_rx(struct eg20t_port * priv,const unsigned char * buf,int size)619 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
620 int size)
621 {
622 struct uart_port *port = &priv->port;
623 struct tty_port *tport = &port->state->port;
624
625 tty_insert_flip_string(tport, buf, size);
626 tty_flip_buffer_push(tport);
627
628 return 0;
629 }
630
dma_push_rx(struct eg20t_port * priv,int size)631 static int dma_push_rx(struct eg20t_port *priv, int size)
632 {
633 int room;
634 struct uart_port *port = &priv->port;
635 struct tty_port *tport = &port->state->port;
636
637 room = tty_buffer_request_room(tport, size);
638
639 if (room < size)
640 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
641 size - room);
642 if (!room)
643 return 0;
644
645 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
646
647 port->icount.rx += room;
648
649 return room;
650 }
651
pch_free_dma(struct uart_port * port)652 static void pch_free_dma(struct uart_port *port)
653 {
654 struct eg20t_port *priv;
655 priv = container_of(port, struct eg20t_port, port);
656
657 if (priv->chan_tx) {
658 dma_release_channel(priv->chan_tx);
659 priv->chan_tx = NULL;
660 }
661 if (priv->chan_rx) {
662 dma_release_channel(priv->chan_rx);
663 priv->chan_rx = NULL;
664 }
665
666 if (priv->rx_buf_dma) {
667 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
668 priv->rx_buf_dma);
669 priv->rx_buf_virt = NULL;
670 priv->rx_buf_dma = 0;
671 }
672
673 return;
674 }
675
filter(struct dma_chan * chan,void * slave)676 static bool filter(struct dma_chan *chan, void *slave)
677 {
678 struct pch_dma_slave *param = slave;
679
680 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
681 chan->device->dev)) {
682 chan->private = param;
683 return true;
684 } else {
685 return false;
686 }
687 }
688
pch_request_dma(struct uart_port * port)689 static void pch_request_dma(struct uart_port *port)
690 {
691 dma_cap_mask_t mask;
692 struct dma_chan *chan;
693 struct pci_dev *dma_dev;
694 struct pch_dma_slave *param;
695 struct eg20t_port *priv =
696 container_of(port, struct eg20t_port, port);
697 dma_cap_zero(mask);
698 dma_cap_set(DMA_SLAVE, mask);
699
700 /* Get DMA's dev information */
701 dma_dev = pci_get_slot(priv->pdev->bus,
702 PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
703
704 /* Set Tx DMA */
705 param = &priv->param_tx;
706 param->dma_dev = &dma_dev->dev;
707 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
708
709 param->tx_reg = port->mapbase + UART_TX;
710 chan = dma_request_channel(mask, filter, param);
711 if (!chan) {
712 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
713 __func__);
714 return;
715 }
716 priv->chan_tx = chan;
717
718 /* Set Rx DMA */
719 param = &priv->param_rx;
720 param->dma_dev = &dma_dev->dev;
721 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
722
723 param->rx_reg = port->mapbase + UART_RX;
724 chan = dma_request_channel(mask, filter, param);
725 if (!chan) {
726 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
727 __func__);
728 dma_release_channel(priv->chan_tx);
729 priv->chan_tx = NULL;
730 return;
731 }
732
733 /* Get Consistent memory for DMA */
734 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
735 &priv->rx_buf_dma, GFP_KERNEL);
736 priv->chan_rx = chan;
737 }
738
pch_dma_rx_complete(void * arg)739 static void pch_dma_rx_complete(void *arg)
740 {
741 struct eg20t_port *priv = arg;
742 struct uart_port *port = &priv->port;
743 int count;
744
745 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
746 count = dma_push_rx(priv, priv->trigger_level);
747 if (count)
748 tty_flip_buffer_push(&port->state->port);
749 async_tx_ack(priv->desc_rx);
750 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
751 PCH_UART_HAL_RX_ERR_INT);
752 }
753
pch_dma_tx_complete(void * arg)754 static void pch_dma_tx_complete(void *arg)
755 {
756 struct eg20t_port *priv = arg;
757 struct uart_port *port = &priv->port;
758 struct circ_buf *xmit = &port->state->xmit;
759 struct scatterlist *sg = priv->sg_tx_p;
760 int i;
761
762 for (i = 0; i < priv->nent; i++, sg++) {
763 xmit->tail += sg_dma_len(sg);
764 port->icount.tx += sg_dma_len(sg);
765 }
766 xmit->tail &= UART_XMIT_SIZE - 1;
767 async_tx_ack(priv->desc_tx);
768 dma_unmap_sg(port->dev, sg, priv->orig_nent, DMA_TO_DEVICE);
769 priv->tx_dma_use = 0;
770 priv->nent = 0;
771 priv->orig_nent = 0;
772 kfree(priv->sg_tx_p);
773 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
774 }
775
pop_tx(struct eg20t_port * priv,int size)776 static int pop_tx(struct eg20t_port *priv, int size)
777 {
778 int count = 0;
779 struct uart_port *port = &priv->port;
780 struct circ_buf *xmit = &port->state->xmit;
781
782 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
783 goto pop_tx_end;
784
785 do {
786 int cnt_to_end =
787 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
788 int sz = min(size - count, cnt_to_end);
789 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
790 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
791 count += sz;
792 } while (!uart_circ_empty(xmit) && count < size);
793
794 pop_tx_end:
795 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
796 count, size - count, jiffies);
797
798 return count;
799 }
800
handle_rx_to(struct eg20t_port * priv)801 static int handle_rx_to(struct eg20t_port *priv)
802 {
803 struct pch_uart_buffer *buf;
804 int rx_size;
805 int ret;
806 if (!priv->start_rx) {
807 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
808 PCH_UART_HAL_RX_ERR_INT);
809 return 0;
810 }
811 buf = &priv->rxbuf;
812 do {
813 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
814 ret = push_rx(priv, buf->buf, rx_size);
815 if (ret)
816 return 0;
817 } while (rx_size == buf->size);
818
819 return PCH_UART_HANDLED_RX_INT;
820 }
821
handle_rx(struct eg20t_port * priv)822 static int handle_rx(struct eg20t_port *priv)
823 {
824 return handle_rx_to(priv);
825 }
826
dma_handle_rx(struct eg20t_port * priv)827 static int dma_handle_rx(struct eg20t_port *priv)
828 {
829 struct uart_port *port = &priv->port;
830 struct dma_async_tx_descriptor *desc;
831 struct scatterlist *sg;
832
833 priv = container_of(port, struct eg20t_port, port);
834 sg = &priv->sg_rx;
835
836 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
837
838 sg_dma_len(sg) = priv->trigger_level;
839
840 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
841 sg_dma_len(sg), offset_in_page(priv->rx_buf_virt));
842
843 sg_dma_address(sg) = priv->rx_buf_dma;
844
845 desc = dmaengine_prep_slave_sg(priv->chan_rx,
846 sg, 1, DMA_DEV_TO_MEM,
847 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
848
849 if (!desc)
850 return 0;
851
852 priv->desc_rx = desc;
853 desc->callback = pch_dma_rx_complete;
854 desc->callback_param = priv;
855 desc->tx_submit(desc);
856 dma_async_issue_pending(priv->chan_rx);
857
858 return PCH_UART_HANDLED_RX_INT;
859 }
860
handle_tx(struct eg20t_port * priv)861 static unsigned int handle_tx(struct eg20t_port *priv)
862 {
863 struct uart_port *port = &priv->port;
864 struct circ_buf *xmit = &port->state->xmit;
865 int fifo_size;
866 int tx_size;
867 int size;
868 int tx_empty;
869
870 if (!priv->start_tx) {
871 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
872 __func__, jiffies);
873 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
874 priv->tx_empty = 1;
875 return 0;
876 }
877
878 fifo_size = max(priv->fifo_size, 1);
879 tx_empty = 1;
880 if (port->x_char) {
881 pch_uart_hal_write(priv, &port->x_char, 1);
882 port->icount.tx++;
883 port->x_char = 0;
884 tx_empty = 0;
885 fifo_size--;
886 }
887 size = min(xmit->head - xmit->tail, fifo_size);
888 if (size < 0)
889 size = fifo_size;
890
891 tx_size = pop_tx(priv, size);
892 if (tx_size > 0) {
893 port->icount.tx += tx_size;
894 tx_empty = 0;
895 }
896
897 priv->tx_empty = tx_empty;
898
899 if (tx_empty) {
900 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
901 uart_write_wakeup(port);
902 }
903
904 return PCH_UART_HANDLED_TX_INT;
905 }
906
dma_handle_tx(struct eg20t_port * priv)907 static unsigned int dma_handle_tx(struct eg20t_port *priv)
908 {
909 struct uart_port *port = &priv->port;
910 struct circ_buf *xmit = &port->state->xmit;
911 struct scatterlist *sg;
912 int nent;
913 int fifo_size;
914 struct dma_async_tx_descriptor *desc;
915 int num;
916 int i;
917 int bytes;
918 int size;
919 int rem;
920
921 if (!priv->start_tx) {
922 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
923 __func__, jiffies);
924 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
925 priv->tx_empty = 1;
926 return 0;
927 }
928
929 if (priv->tx_dma_use) {
930 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
931 __func__, jiffies);
932 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
933 priv->tx_empty = 1;
934 return 0;
935 }
936
937 fifo_size = max(priv->fifo_size, 1);
938
939 if (port->x_char) {
940 pch_uart_hal_write(priv, &port->x_char, 1);
941 port->icount.tx++;
942 port->x_char = 0;
943 fifo_size--;
944 }
945
946 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
947 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
948 xmit->tail, UART_XMIT_SIZE));
949 if (!bytes) {
950 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
951 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
952 uart_write_wakeup(port);
953 return 0;
954 }
955
956 if (bytes > fifo_size) {
957 num = bytes / fifo_size + 1;
958 size = fifo_size;
959 rem = bytes % fifo_size;
960 } else {
961 num = 1;
962 size = bytes;
963 rem = bytes;
964 }
965
966 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
967 __func__, num, size, rem);
968
969 priv->tx_dma_use = 1;
970
971 priv->sg_tx_p = kmalloc_array(num, sizeof(struct scatterlist), GFP_ATOMIC);
972 if (!priv->sg_tx_p) {
973 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
974 return 0;
975 }
976
977 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
978 sg = priv->sg_tx_p;
979
980 for (i = 0; i < num; i++, sg++) {
981 if (i == (num - 1))
982 sg_set_page(sg, virt_to_page(xmit->buf),
983 rem, fifo_size * i);
984 else
985 sg_set_page(sg, virt_to_page(xmit->buf),
986 size, fifo_size * i);
987 }
988
989 sg = priv->sg_tx_p;
990 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
991 if (!nent) {
992 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
993 return 0;
994 }
995 priv->orig_nent = num;
996 priv->nent = nent;
997
998 for (i = 0; i < nent; i++, sg++) {
999 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1000 fifo_size * i;
1001 sg_dma_address(sg) = (sg_dma_address(sg) &
1002 ~(UART_XMIT_SIZE - 1)) + sg->offset;
1003 if (i == (nent - 1))
1004 sg_dma_len(sg) = rem;
1005 else
1006 sg_dma_len(sg) = size;
1007 }
1008
1009 desc = dmaengine_prep_slave_sg(priv->chan_tx,
1010 priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1011 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1012 if (!desc) {
1013 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
1014 __func__);
1015 return 0;
1016 }
1017 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1018 priv->desc_tx = desc;
1019 desc->callback = pch_dma_tx_complete;
1020 desc->callback_param = priv;
1021
1022 desc->tx_submit(desc);
1023
1024 dma_async_issue_pending(priv->chan_tx);
1025
1026 return PCH_UART_HANDLED_TX_INT;
1027 }
1028
pch_uart_err_ir(struct eg20t_port * priv,unsigned int lsr)1029 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1030 {
1031 struct uart_port *port = &priv->port;
1032 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1033 char *error_msg[5] = {};
1034 int i = 0;
1035
1036 if (lsr & PCH_UART_LSR_ERR)
1037 error_msg[i++] = "Error data in FIFO\n";
1038
1039 if (lsr & UART_LSR_FE) {
1040 port->icount.frame++;
1041 error_msg[i++] = " Framing Error\n";
1042 }
1043
1044 if (lsr & UART_LSR_PE) {
1045 port->icount.parity++;
1046 error_msg[i++] = " Parity Error\n";
1047 }
1048
1049 if (lsr & UART_LSR_OE) {
1050 port->icount.overrun++;
1051 error_msg[i++] = " Overrun Error\n";
1052 }
1053
1054 if (tty == NULL) {
1055 for (i = 0; error_msg[i] != NULL; i++)
1056 dev_err(&priv->pdev->dev, error_msg[i]);
1057 } else {
1058 tty_kref_put(tty);
1059 }
1060 }
1061
pch_uart_interrupt(int irq,void * dev_id)1062 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1063 {
1064 struct eg20t_port *priv = dev_id;
1065 unsigned int handled;
1066 u8 lsr;
1067 int ret = 0;
1068 unsigned char iid;
1069 unsigned long flags;
1070 int next = 1;
1071 u8 msr;
1072
1073 spin_lock_irqsave(&priv->lock, flags);
1074 handled = 0;
1075 while (next) {
1076 iid = pch_uart_hal_get_iid(priv);
1077 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1078 break;
1079 switch (iid) {
1080 case PCH_UART_IID_RLS: /* Receiver Line Status */
1081 lsr = pch_uart_hal_get_line_status(priv);
1082 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1083 UART_LSR_PE | UART_LSR_OE)) {
1084 pch_uart_err_ir(priv, lsr);
1085 ret = PCH_UART_HANDLED_RX_ERR_INT;
1086 } else {
1087 ret = PCH_UART_HANDLED_LS_INT;
1088 }
1089 break;
1090 case PCH_UART_IID_RDR: /* Received Data Ready */
1091 if (priv->use_dma) {
1092 pch_uart_hal_disable_interrupt(priv,
1093 PCH_UART_HAL_RX_INT |
1094 PCH_UART_HAL_RX_ERR_INT);
1095 ret = dma_handle_rx(priv);
1096 if (!ret)
1097 pch_uart_hal_enable_interrupt(priv,
1098 PCH_UART_HAL_RX_INT |
1099 PCH_UART_HAL_RX_ERR_INT);
1100 } else {
1101 ret = handle_rx(priv);
1102 }
1103 break;
1104 case PCH_UART_IID_RDR_TO: /* Received Data Ready
1105 (FIFO Timeout) */
1106 ret = handle_rx_to(priv);
1107 break;
1108 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1109 Empty */
1110 if (priv->use_dma)
1111 ret = dma_handle_tx(priv);
1112 else
1113 ret = handle_tx(priv);
1114 break;
1115 case PCH_UART_IID_MS: /* Modem Status */
1116 msr = pch_uart_hal_get_modem(priv);
1117 next = 0; /* MS ir prioirty is the lowest. So, MS ir
1118 means final interrupt */
1119 if ((msr & UART_MSR_ANY_DELTA) == 0)
1120 break;
1121 ret |= PCH_UART_HANDLED_MS_INT;
1122 break;
1123 default: /* Never junp to this label */
1124 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1125 iid, jiffies);
1126 ret = -1;
1127 next = 0;
1128 break;
1129 }
1130 handled |= (unsigned int)ret;
1131 }
1132
1133 spin_unlock_irqrestore(&priv->lock, flags);
1134 return IRQ_RETVAL(handled);
1135 }
1136
1137 /* This function tests whether the transmitter fifo and shifter for the port
1138 described by 'port' is empty. */
pch_uart_tx_empty(struct uart_port * port)1139 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1140 {
1141 struct eg20t_port *priv;
1142
1143 priv = container_of(port, struct eg20t_port, port);
1144 if (priv->tx_empty)
1145 return TIOCSER_TEMT;
1146 else
1147 return 0;
1148 }
1149
1150 /* Returns the current state of modem control inputs. */
pch_uart_get_mctrl(struct uart_port * port)1151 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1152 {
1153 struct eg20t_port *priv;
1154 u8 modem;
1155 unsigned int ret = 0;
1156
1157 priv = container_of(port, struct eg20t_port, port);
1158 modem = pch_uart_hal_get_modem(priv);
1159
1160 if (modem & UART_MSR_DCD)
1161 ret |= TIOCM_CAR;
1162
1163 if (modem & UART_MSR_RI)
1164 ret |= TIOCM_RNG;
1165
1166 if (modem & UART_MSR_DSR)
1167 ret |= TIOCM_DSR;
1168
1169 if (modem & UART_MSR_CTS)
1170 ret |= TIOCM_CTS;
1171
1172 return ret;
1173 }
1174
pch_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)1175 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1176 {
1177 u32 mcr = 0;
1178 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1179
1180 if (mctrl & TIOCM_DTR)
1181 mcr |= UART_MCR_DTR;
1182 if (mctrl & TIOCM_RTS)
1183 mcr |= UART_MCR_RTS;
1184 if (mctrl & TIOCM_LOOP)
1185 mcr |= UART_MCR_LOOP;
1186
1187 if (priv->mcr & UART_MCR_AFE)
1188 mcr |= UART_MCR_AFE;
1189
1190 if (mctrl)
1191 iowrite8(mcr, priv->membase + UART_MCR);
1192 }
1193
pch_uart_stop_tx(struct uart_port * port)1194 static void pch_uart_stop_tx(struct uart_port *port)
1195 {
1196 struct eg20t_port *priv;
1197 priv = container_of(port, struct eg20t_port, port);
1198 priv->start_tx = 0;
1199 priv->tx_dma_use = 0;
1200 }
1201
pch_uart_start_tx(struct uart_port * port)1202 static void pch_uart_start_tx(struct uart_port *port)
1203 {
1204 struct eg20t_port *priv;
1205
1206 priv = container_of(port, struct eg20t_port, port);
1207
1208 if (priv->use_dma) {
1209 if (priv->tx_dma_use) {
1210 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1211 __func__);
1212 return;
1213 }
1214 }
1215
1216 priv->start_tx = 1;
1217 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1218 }
1219
pch_uart_stop_rx(struct uart_port * port)1220 static void pch_uart_stop_rx(struct uart_port *port)
1221 {
1222 struct eg20t_port *priv;
1223 priv = container_of(port, struct eg20t_port, port);
1224 priv->start_rx = 0;
1225 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1226 PCH_UART_HAL_RX_ERR_INT);
1227 }
1228
1229 /* Enable the modem status interrupts. */
pch_uart_enable_ms(struct uart_port * port)1230 static void pch_uart_enable_ms(struct uart_port *port)
1231 {
1232 struct eg20t_port *priv;
1233 priv = container_of(port, struct eg20t_port, port);
1234 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1235 }
1236
1237 /* Control the transmission of a break signal. */
pch_uart_break_ctl(struct uart_port * port,int ctl)1238 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1239 {
1240 struct eg20t_port *priv;
1241 unsigned long flags;
1242
1243 priv = container_of(port, struct eg20t_port, port);
1244 spin_lock_irqsave(&priv->lock, flags);
1245 pch_uart_hal_set_break(priv, ctl);
1246 spin_unlock_irqrestore(&priv->lock, flags);
1247 }
1248
1249 /* Grab any interrupt resources and initialise any low level driver state. */
pch_uart_startup(struct uart_port * port)1250 static int pch_uart_startup(struct uart_port *port)
1251 {
1252 struct eg20t_port *priv;
1253 int ret;
1254 int fifo_size;
1255 int trigger_level;
1256
1257 priv = container_of(port, struct eg20t_port, port);
1258 priv->tx_empty = 1;
1259
1260 if (port->uartclk)
1261 priv->uartclk = port->uartclk;
1262 else
1263 port->uartclk = priv->uartclk;
1264
1265 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1266 ret = pch_uart_hal_set_line(priv, default_baud,
1267 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1268 PCH_UART_HAL_STB1);
1269 if (ret)
1270 return ret;
1271
1272 switch (priv->fifo_size) {
1273 case 256:
1274 fifo_size = PCH_UART_HAL_FIFO256;
1275 break;
1276 case 64:
1277 fifo_size = PCH_UART_HAL_FIFO64;
1278 break;
1279 case 16:
1280 fifo_size = PCH_UART_HAL_FIFO16;
1281 break;
1282 case 1:
1283 default:
1284 fifo_size = PCH_UART_HAL_FIFO_DIS;
1285 break;
1286 }
1287
1288 switch (priv->trigger) {
1289 case PCH_UART_HAL_TRIGGER1:
1290 trigger_level = 1;
1291 break;
1292 case PCH_UART_HAL_TRIGGER_L:
1293 trigger_level = priv->fifo_size / 4;
1294 break;
1295 case PCH_UART_HAL_TRIGGER_M:
1296 trigger_level = priv->fifo_size / 2;
1297 break;
1298 case PCH_UART_HAL_TRIGGER_H:
1299 default:
1300 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1301 break;
1302 }
1303
1304 priv->trigger_level = trigger_level;
1305 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1306 fifo_size, priv->trigger);
1307 if (ret < 0)
1308 return ret;
1309
1310 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1311 priv->irq_name, priv);
1312 if (ret < 0)
1313 return ret;
1314
1315 if (priv->use_dma)
1316 pch_request_dma(port);
1317
1318 priv->start_rx = 1;
1319 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1320 PCH_UART_HAL_RX_ERR_INT);
1321 uart_update_timeout(port, CS8, default_baud);
1322
1323 return 0;
1324 }
1325
pch_uart_shutdown(struct uart_port * port)1326 static void pch_uart_shutdown(struct uart_port *port)
1327 {
1328 struct eg20t_port *priv;
1329 int ret;
1330
1331 priv = container_of(port, struct eg20t_port, port);
1332 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1333 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1334 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1335 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1336 if (ret)
1337 dev_err(priv->port.dev,
1338 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1339
1340 pch_free_dma(port);
1341
1342 free_irq(priv->port.irq, priv);
1343 }
1344
1345 /* Change the port parameters, including word length, parity, stop
1346 *bits. Update read_status_mask and ignore_status_mask to indicate
1347 *the types of events we are interested in receiving. */
pch_uart_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)1348 static void pch_uart_set_termios(struct uart_port *port,
1349 struct ktermios *termios, struct ktermios *old)
1350 {
1351 int rtn;
1352 unsigned int baud, parity, bits, stb;
1353 struct eg20t_port *priv;
1354 unsigned long flags;
1355
1356 priv = container_of(port, struct eg20t_port, port);
1357 switch (termios->c_cflag & CSIZE) {
1358 case CS5:
1359 bits = PCH_UART_HAL_5BIT;
1360 break;
1361 case CS6:
1362 bits = PCH_UART_HAL_6BIT;
1363 break;
1364 case CS7:
1365 bits = PCH_UART_HAL_7BIT;
1366 break;
1367 default: /* CS8 */
1368 bits = PCH_UART_HAL_8BIT;
1369 break;
1370 }
1371 if (termios->c_cflag & CSTOPB)
1372 stb = PCH_UART_HAL_STB2;
1373 else
1374 stb = PCH_UART_HAL_STB1;
1375
1376 if (termios->c_cflag & PARENB) {
1377 if (termios->c_cflag & PARODD)
1378 parity = PCH_UART_HAL_PARITY_ODD;
1379 else
1380 parity = PCH_UART_HAL_PARITY_EVEN;
1381
1382 } else
1383 parity = PCH_UART_HAL_PARITY_NONE;
1384
1385 /* Only UART0 has auto hardware flow function */
1386 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1387 priv->mcr |= UART_MCR_AFE;
1388 else
1389 priv->mcr &= ~UART_MCR_AFE;
1390
1391 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1392
1393 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1394
1395 spin_lock_irqsave(&priv->lock, flags);
1396 spin_lock(&port->lock);
1397
1398 uart_update_timeout(port, termios->c_cflag, baud);
1399 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1400 if (rtn)
1401 goto out;
1402
1403 pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1404 /* Don't rewrite B0 */
1405 if (tty_termios_baud_rate(termios))
1406 tty_termios_encode_baud_rate(termios, baud, baud);
1407
1408 out:
1409 spin_unlock(&port->lock);
1410 spin_unlock_irqrestore(&priv->lock, flags);
1411 }
1412
pch_uart_type(struct uart_port * port)1413 static const char *pch_uart_type(struct uart_port *port)
1414 {
1415 return KBUILD_MODNAME;
1416 }
1417
pch_uart_release_port(struct uart_port * port)1418 static void pch_uart_release_port(struct uart_port *port)
1419 {
1420 struct eg20t_port *priv;
1421
1422 priv = container_of(port, struct eg20t_port, port);
1423 pci_iounmap(priv->pdev, priv->membase);
1424 pci_release_regions(priv->pdev);
1425 }
1426
pch_uart_request_port(struct uart_port * port)1427 static int pch_uart_request_port(struct uart_port *port)
1428 {
1429 struct eg20t_port *priv;
1430 int ret;
1431 void __iomem *membase;
1432
1433 priv = container_of(port, struct eg20t_port, port);
1434 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1435 if (ret < 0)
1436 return -EBUSY;
1437
1438 membase = pci_iomap(priv->pdev, 1, 0);
1439 if (!membase) {
1440 pci_release_regions(priv->pdev);
1441 return -EBUSY;
1442 }
1443 priv->membase = port->membase = membase;
1444
1445 return 0;
1446 }
1447
pch_uart_config_port(struct uart_port * port,int type)1448 static void pch_uart_config_port(struct uart_port *port, int type)
1449 {
1450 struct eg20t_port *priv;
1451
1452 priv = container_of(port, struct eg20t_port, port);
1453 if (type & UART_CONFIG_TYPE) {
1454 port->type = priv->port_type;
1455 pch_uart_request_port(port);
1456 }
1457 }
1458
pch_uart_verify_port(struct uart_port * port,struct serial_struct * serinfo)1459 static int pch_uart_verify_port(struct uart_port *port,
1460 struct serial_struct *serinfo)
1461 {
1462 struct eg20t_port *priv;
1463
1464 priv = container_of(port, struct eg20t_port, port);
1465 if (serinfo->flags & UPF_LOW_LATENCY) {
1466 dev_info(priv->port.dev,
1467 "PCH UART : Use PIO Mode (without DMA)\n");
1468 priv->use_dma = 0;
1469 serinfo->flags &= ~UPF_LOW_LATENCY;
1470 } else {
1471 #ifndef CONFIG_PCH_DMA
1472 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1473 __func__);
1474 return -EOPNOTSUPP;
1475 #endif
1476 if (!priv->use_dma) {
1477 pch_request_dma(port);
1478 if (priv->chan_rx)
1479 priv->use_dma = 1;
1480 }
1481 dev_info(priv->port.dev, "PCH UART: %s\n",
1482 priv->use_dma ?
1483 "Use DMA Mode" : "No DMA");
1484 }
1485
1486 return 0;
1487 }
1488
1489 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1490 /*
1491 * Wait for transmitter & holding register to empty
1492 */
wait_for_xmitr(struct eg20t_port * up,int bits)1493 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1494 {
1495 unsigned int status, tmout = 10000;
1496
1497 /* Wait up to 10ms for the character(s) to be sent. */
1498 for (;;) {
1499 status = ioread8(up->membase + UART_LSR);
1500
1501 if ((status & bits) == bits)
1502 break;
1503 if (--tmout == 0)
1504 break;
1505 udelay(1);
1506 }
1507
1508 /* Wait up to 1s for flow control if necessary */
1509 if (up->port.flags & UPF_CONS_FLOW) {
1510 unsigned int tmout;
1511 for (tmout = 1000000; tmout; tmout--) {
1512 unsigned int msr = ioread8(up->membase + UART_MSR);
1513 if (msr & UART_MSR_CTS)
1514 break;
1515 udelay(1);
1516 touch_nmi_watchdog();
1517 }
1518 }
1519 }
1520 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1521
1522 #ifdef CONFIG_CONSOLE_POLL
1523 /*
1524 * Console polling routines for communicate via uart while
1525 * in an interrupt or debug context.
1526 */
pch_uart_get_poll_char(struct uart_port * port)1527 static int pch_uart_get_poll_char(struct uart_port *port)
1528 {
1529 struct eg20t_port *priv =
1530 container_of(port, struct eg20t_port, port);
1531 u8 lsr = ioread8(priv->membase + UART_LSR);
1532
1533 if (!(lsr & UART_LSR_DR))
1534 return NO_POLL_CHAR;
1535
1536 return ioread8(priv->membase + PCH_UART_RBR);
1537 }
1538
1539
pch_uart_put_poll_char(struct uart_port * port,unsigned char c)1540 static void pch_uart_put_poll_char(struct uart_port *port,
1541 unsigned char c)
1542 {
1543 unsigned int ier;
1544 struct eg20t_port *priv =
1545 container_of(port, struct eg20t_port, port);
1546
1547 /*
1548 * First save the IER then disable the interrupts
1549 */
1550 ier = ioread8(priv->membase + UART_IER);
1551 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1552
1553 wait_for_xmitr(priv, UART_LSR_THRE);
1554 /*
1555 * Send the character out.
1556 */
1557 iowrite8(c, priv->membase + PCH_UART_THR);
1558
1559 /*
1560 * Finally, wait for transmitter to become empty
1561 * and restore the IER
1562 */
1563 wait_for_xmitr(priv, BOTH_EMPTY);
1564 iowrite8(ier, priv->membase + UART_IER);
1565 }
1566 #endif /* CONFIG_CONSOLE_POLL */
1567
1568 static const struct uart_ops pch_uart_ops = {
1569 .tx_empty = pch_uart_tx_empty,
1570 .set_mctrl = pch_uart_set_mctrl,
1571 .get_mctrl = pch_uart_get_mctrl,
1572 .stop_tx = pch_uart_stop_tx,
1573 .start_tx = pch_uart_start_tx,
1574 .stop_rx = pch_uart_stop_rx,
1575 .enable_ms = pch_uart_enable_ms,
1576 .break_ctl = pch_uart_break_ctl,
1577 .startup = pch_uart_startup,
1578 .shutdown = pch_uart_shutdown,
1579 .set_termios = pch_uart_set_termios,
1580 /* .pm = pch_uart_pm, Not supported yet */
1581 .type = pch_uart_type,
1582 .release_port = pch_uart_release_port,
1583 .request_port = pch_uart_request_port,
1584 .config_port = pch_uart_config_port,
1585 .verify_port = pch_uart_verify_port,
1586 #ifdef CONFIG_CONSOLE_POLL
1587 .poll_get_char = pch_uart_get_poll_char,
1588 .poll_put_char = pch_uart_put_poll_char,
1589 #endif
1590 };
1591
1592 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1593
pch_console_putchar(struct uart_port * port,int ch)1594 static void pch_console_putchar(struct uart_port *port, int ch)
1595 {
1596 struct eg20t_port *priv =
1597 container_of(port, struct eg20t_port, port);
1598
1599 wait_for_xmitr(priv, UART_LSR_THRE);
1600 iowrite8(ch, priv->membase + PCH_UART_THR);
1601 }
1602
1603 /*
1604 * Print a string to the serial port trying not to disturb
1605 * any possible real use of the port...
1606 *
1607 * The console_lock must be held when we get here.
1608 */
1609 static void
pch_console_write(struct console * co,const char * s,unsigned int count)1610 pch_console_write(struct console *co, const char *s, unsigned int count)
1611 {
1612 struct eg20t_port *priv;
1613 unsigned long flags;
1614 int priv_locked = 1;
1615 int port_locked = 1;
1616 u8 ier;
1617
1618 priv = pch_uart_ports[co->index];
1619
1620 touch_nmi_watchdog();
1621
1622 local_irq_save(flags);
1623 if (priv->port.sysrq) {
1624 /* call to uart_handle_sysrq_char already took the priv lock */
1625 priv_locked = 0;
1626 /* serial8250_handle_port() already took the port lock */
1627 port_locked = 0;
1628 } else if (oops_in_progress) {
1629 priv_locked = spin_trylock(&priv->lock);
1630 port_locked = spin_trylock(&priv->port.lock);
1631 } else {
1632 spin_lock(&priv->lock);
1633 spin_lock(&priv->port.lock);
1634 }
1635
1636 /*
1637 * First save the IER then disable the interrupts
1638 */
1639 ier = ioread8(priv->membase + UART_IER);
1640
1641 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1642
1643 uart_console_write(&priv->port, s, count, pch_console_putchar);
1644
1645 /*
1646 * Finally, wait for transmitter to become empty
1647 * and restore the IER
1648 */
1649 wait_for_xmitr(priv, BOTH_EMPTY);
1650 iowrite8(ier, priv->membase + UART_IER);
1651
1652 if (port_locked)
1653 spin_unlock(&priv->port.lock);
1654 if (priv_locked)
1655 spin_unlock(&priv->lock);
1656 local_irq_restore(flags);
1657 }
1658
pch_console_setup(struct console * co,char * options)1659 static int __init pch_console_setup(struct console *co, char *options)
1660 {
1661 struct uart_port *port;
1662 int baud = default_baud;
1663 int bits = 8;
1664 int parity = 'n';
1665 int flow = 'n';
1666
1667 /*
1668 * Check whether an invalid uart number has been specified, and
1669 * if so, search for the first available port that does have
1670 * console support.
1671 */
1672 if (co->index >= PCH_UART_NR)
1673 co->index = 0;
1674 port = &pch_uart_ports[co->index]->port;
1675
1676 if (!port || (!port->iobase && !port->membase))
1677 return -ENODEV;
1678
1679 port->uartclk = pch_uart_get_uartclk();
1680
1681 if (options)
1682 uart_parse_options(options, &baud, &parity, &bits, &flow);
1683
1684 return uart_set_options(port, co, baud, parity, bits, flow);
1685 }
1686
1687 static struct uart_driver pch_uart_driver;
1688
1689 static struct console pch_console = {
1690 .name = PCH_UART_DRIVER_DEVICE,
1691 .write = pch_console_write,
1692 .device = uart_console_device,
1693 .setup = pch_console_setup,
1694 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1695 .index = -1,
1696 .data = &pch_uart_driver,
1697 };
1698
1699 #define PCH_CONSOLE (&pch_console)
1700 #else
1701 #define PCH_CONSOLE NULL
1702 #endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1703
1704 static struct uart_driver pch_uart_driver = {
1705 .owner = THIS_MODULE,
1706 .driver_name = KBUILD_MODNAME,
1707 .dev_name = PCH_UART_DRIVER_DEVICE,
1708 .major = 0,
1709 .minor = 0,
1710 .nr = PCH_UART_NR,
1711 .cons = PCH_CONSOLE,
1712 };
1713
pch_uart_init_port(struct pci_dev * pdev,const struct pci_device_id * id)1714 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1715 const struct pci_device_id *id)
1716 {
1717 struct eg20t_port *priv;
1718 int ret;
1719 unsigned int iobase;
1720 unsigned int mapbase;
1721 unsigned char *rxbuf;
1722 int fifosize;
1723 int port_type;
1724 struct pch_uart_driver_data *board;
1725 #ifdef CONFIG_DEBUG_FS
1726 char name[32]; /* for debugfs file name */
1727 #endif
1728
1729 board = &drv_dat[id->driver_data];
1730 port_type = board->port_type;
1731
1732 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1733 if (priv == NULL)
1734 goto init_port_alloc_err;
1735
1736 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1737 if (!rxbuf)
1738 goto init_port_free_txbuf;
1739
1740 switch (port_type) {
1741 case PORT_PCH_8LINE:
1742 fifosize = 256; /* EG20T/ML7213: UART0 */
1743 break;
1744 case PORT_PCH_2LINE:
1745 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1746 break;
1747 default:
1748 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1749 goto init_port_hal_free;
1750 }
1751
1752 pci_enable_msi(pdev);
1753 pci_set_master(pdev);
1754
1755 spin_lock_init(&priv->lock);
1756
1757 iobase = pci_resource_start(pdev, 0);
1758 mapbase = pci_resource_start(pdev, 1);
1759 priv->mapbase = mapbase;
1760 priv->iobase = iobase;
1761 priv->pdev = pdev;
1762 priv->tx_empty = 1;
1763 priv->rxbuf.buf = rxbuf;
1764 priv->rxbuf.size = PAGE_SIZE;
1765
1766 priv->fifo_size = fifosize;
1767 priv->uartclk = pch_uart_get_uartclk();
1768 priv->port_type = port_type;
1769 priv->port.dev = &pdev->dev;
1770 priv->port.iobase = iobase;
1771 priv->port.membase = NULL;
1772 priv->port.mapbase = mapbase;
1773 priv->port.irq = pdev->irq;
1774 priv->port.iotype = UPIO_PORT;
1775 priv->port.ops = &pch_uart_ops;
1776 priv->port.flags = UPF_BOOT_AUTOCONF;
1777 priv->port.fifosize = fifosize;
1778 priv->port.line = board->line_no;
1779 priv->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PCH_UART_CONSOLE);
1780 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1781
1782 snprintf(priv->irq_name, IRQ_NAME_SIZE,
1783 KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1784 priv->port.line);
1785
1786 spin_lock_init(&priv->port.lock);
1787
1788 pci_set_drvdata(pdev, priv);
1789 priv->trigger_level = 1;
1790 priv->fcr = 0;
1791
1792 if (pdev->dev.of_node)
1793 of_property_read_u32(pdev->dev.of_node, "clock-frequency"
1794 , &user_uartclk);
1795
1796 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1797 pch_uart_ports[board->line_no] = priv;
1798 #endif
1799 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1800 if (ret < 0)
1801 goto init_port_hal_free;
1802
1803 #ifdef CONFIG_DEBUG_FS
1804 snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1805 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1806 NULL, priv, &port_regs_ops);
1807 #endif
1808
1809 return priv;
1810
1811 init_port_hal_free:
1812 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1813 pch_uart_ports[board->line_no] = NULL;
1814 #endif
1815 free_page((unsigned long)rxbuf);
1816 init_port_free_txbuf:
1817 kfree(priv);
1818 init_port_alloc_err:
1819
1820 return NULL;
1821 }
1822
pch_uart_exit_port(struct eg20t_port * priv)1823 static void pch_uart_exit_port(struct eg20t_port *priv)
1824 {
1825
1826 #ifdef CONFIG_DEBUG_FS
1827 debugfs_remove(priv->debugfs);
1828 #endif
1829 uart_remove_one_port(&pch_uart_driver, &priv->port);
1830 free_page((unsigned long)priv->rxbuf.buf);
1831 }
1832
pch_uart_pci_remove(struct pci_dev * pdev)1833 static void pch_uart_pci_remove(struct pci_dev *pdev)
1834 {
1835 struct eg20t_port *priv = pci_get_drvdata(pdev);
1836
1837 pci_disable_msi(pdev);
1838
1839 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1840 pch_uart_ports[priv->port.line] = NULL;
1841 #endif
1842 pch_uart_exit_port(priv);
1843 pci_disable_device(pdev);
1844 kfree(priv);
1845 return;
1846 }
1847
pch_uart_pci_suspend(struct device * dev)1848 static int __maybe_unused pch_uart_pci_suspend(struct device *dev)
1849 {
1850 struct eg20t_port *priv = dev_get_drvdata(dev);
1851
1852 uart_suspend_port(&pch_uart_driver, &priv->port);
1853
1854 return 0;
1855 }
1856
pch_uart_pci_resume(struct device * dev)1857 static int __maybe_unused pch_uart_pci_resume(struct device *dev)
1858 {
1859 struct eg20t_port *priv = dev_get_drvdata(dev);
1860
1861 uart_resume_port(&pch_uart_driver, &priv->port);
1862
1863 return 0;
1864 }
1865
1866 static const struct pci_device_id pch_uart_pci_id[] = {
1867 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1868 .driver_data = pch_et20t_uart0},
1869 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1870 .driver_data = pch_et20t_uart1},
1871 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1872 .driver_data = pch_et20t_uart2},
1873 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1874 .driver_data = pch_et20t_uart3},
1875 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1876 .driver_data = pch_ml7213_uart0},
1877 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1878 .driver_data = pch_ml7213_uart1},
1879 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1880 .driver_data = pch_ml7213_uart2},
1881 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1882 .driver_data = pch_ml7223_uart0},
1883 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1884 .driver_data = pch_ml7223_uart1},
1885 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1886 .driver_data = pch_ml7831_uart0},
1887 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1888 .driver_data = pch_ml7831_uart1},
1889 {0,},
1890 };
1891
pch_uart_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)1892 static int pch_uart_pci_probe(struct pci_dev *pdev,
1893 const struct pci_device_id *id)
1894 {
1895 int ret;
1896 struct eg20t_port *priv;
1897
1898 ret = pci_enable_device(pdev);
1899 if (ret < 0)
1900 goto probe_error;
1901
1902 priv = pch_uart_init_port(pdev, id);
1903 if (!priv) {
1904 ret = -EBUSY;
1905 goto probe_disable_device;
1906 }
1907 pci_set_drvdata(pdev, priv);
1908
1909 return ret;
1910
1911 probe_disable_device:
1912 pci_disable_msi(pdev);
1913 pci_disable_device(pdev);
1914 probe_error:
1915 return ret;
1916 }
1917
1918 static SIMPLE_DEV_PM_OPS(pch_uart_pci_pm_ops,
1919 pch_uart_pci_suspend,
1920 pch_uart_pci_resume);
1921
1922 static struct pci_driver pch_uart_pci_driver = {
1923 .name = "pch_uart",
1924 .id_table = pch_uart_pci_id,
1925 .probe = pch_uart_pci_probe,
1926 .remove = pch_uart_pci_remove,
1927 .driver.pm = &pch_uart_pci_pm_ops,
1928 };
1929
pch_uart_module_init(void)1930 static int __init pch_uart_module_init(void)
1931 {
1932 int ret;
1933
1934 /* register as UART driver */
1935 ret = uart_register_driver(&pch_uart_driver);
1936 if (ret < 0)
1937 return ret;
1938
1939 /* register as PCI driver */
1940 ret = pci_register_driver(&pch_uart_pci_driver);
1941 if (ret < 0)
1942 uart_unregister_driver(&pch_uart_driver);
1943
1944 return ret;
1945 }
1946 module_init(pch_uart_module_init);
1947
pch_uart_module_exit(void)1948 static void __exit pch_uart_module_exit(void)
1949 {
1950 pci_unregister_driver(&pch_uart_pci_driver);
1951 uart_unregister_driver(&pch_uart_driver);
1952 }
1953 module_exit(pch_uart_module_exit);
1954
1955 MODULE_LICENSE("GPL v2");
1956 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1957 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
1958
1959 module_param(default_baud, uint, S_IRUGO);
1960 MODULE_PARM_DESC(default_baud,
1961 "Default BAUD for initial driver state and console (default 9600)");
1962 module_param(user_uartclk, uint, S_IRUGO);
1963 MODULE_PARM_DESC(user_uartclk,
1964 "Override UART default or board specific UART clock");
1965