1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd
4 * Caesar Wang <wxt@rock-chips.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14 #include <linux/of_irq.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
17 #include <linux/reset.h>
18 #include <linux/rockchip/cpu.h>
19 #include <linux/thermal.h>
20 #include <linux/mfd/syscon.h>
21 #include <linux/pinctrl/consumer.h>
22 #include <linux/nvmem-consumer.h>
23
24 /*
25 * If the temperature over a period of time High,
26 * the resulting TSHUT gave CRU module,let it reset the entire chip,
27 * or via GPIO give PMIC.
28 */
29 enum tshut_mode {
30 TSHUT_MODE_CRU = 0,
31 TSHUT_MODE_OTP,
32 };
33
34 /*
35 * The system Temperature Sensors tshut(tshut) polarity
36 * the bit 8 is tshut polarity.
37 * 0: low active, 1: high active
38 */
39 enum tshut_polarity {
40 TSHUT_LOW_ACTIVE = 0,
41 TSHUT_HIGH_ACTIVE,
42 };
43
44 /*
45 * The system has two Temperature Sensors.
46 * sensor0 is for CPU, and sensor1 is for GPU.
47 */
48 enum sensor_id {
49 SENSOR_CPU = 0,
50 SENSOR_GPU,
51 };
52
53 /*
54 * The conversion table has the adc value and temperature.
55 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
56 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table)
57 */
58 enum adc_sort_mode {
59 ADC_DECREMENT = 0,
60 ADC_INCREMENT,
61 };
62
63 #include "thermal_hwmon.h"
64
65 /**
66 * The max sensors is seven in rockchip SoCs.
67 */
68 #define SOC_MAX_SENSORS 7
69
70 /**
71 * struct chip_tsadc_table - hold information about chip-specific differences
72 * @id: conversion table
73 * @length: size of conversion table
74 * @data_mask: mask to apply on data inputs
75 * @kNum: linear parameter k
76 * @bNum: linear parameter b
77 * @mode: sort mode of this adc variant (incrementing or decrementing)
78 */
79 struct chip_tsadc_table {
80 const struct tsadc_table *id;
81 unsigned int length;
82 u32 data_mask;
83 /* Tsadc is linear, using linear parameters */
84 int kNum;
85 int bNum;
86 enum adc_sort_mode mode;
87 };
88
89 /**
90 * struct rockchip_tsadc_chip - hold the private data of tsadc chip
91 * @chn_id: array of sensor ids of chip corresponding to the channel
92 * @chn_num: the channel number of tsadc chip
93 * @conversion_time: the conversion time of tsadc
94 * @trim_slope: use to conversion trim code to trim temp
95 * @tshut_temp: the hardware-controlled shutdown temperature value
96 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
97 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
98 * @initialize: SoC special initialize tsadc controller method
99 * @irq_ack: clear the interrupt
100 * @control: enable/disable method for the tsadc controller
101 * @get_temp: get the temperature
102 * @set_alarm_temp: set the high temperature interrupt
103 * @set_tshut_temp: set the hardware-controlled shutdown temperature
104 * @set_tshut_mode: set the hardware-controlled shutdown mode
105 * @get_trim_code: get the trim code by otp value
106 * @set_clk_rate: set clock rate
107 * @table: the chip-specific conversion table
108 */
109 struct rockchip_tsadc_chip {
110 /* The sensor id of chip correspond to the ADC channel */
111 int chn_id[SOC_MAX_SENSORS];
112 int chn_num;
113
114 /* The sensor electrical characteristics */
115 int conversion_time;
116
117 /* Use to conversion trim code to trim temp */
118 int trim_slope;
119
120 /* The hardware-controlled tshut property */
121 int tshut_temp;
122 enum tshut_mode tshut_mode;
123 enum tshut_polarity tshut_polarity;
124
125 /* Chip-wide methods */
126 void (*initialize)(struct regmap *grf,
127 void __iomem *reg, enum tshut_polarity p);
128 void (*irq_ack)(void __iomem *reg);
129 void (*control)(void __iomem *reg, bool on);
130
131 /* Per-sensor methods */
132 int (*get_temp)(const struct chip_tsadc_table *table,
133 int chn, void __iomem *reg, int *temp);
134 int (*set_alarm_temp)(const struct chip_tsadc_table *table,
135 int chn, void __iomem *reg, int temp);
136 int (*set_tshut_temp)(const struct chip_tsadc_table *table,
137 int chn, void __iomem *reg, int temp);
138 void (*set_tshut_mode)(struct regmap *grf, int chn,
139 void __iomem *reg, enum tshut_mode m);
140 int (*get_trim_code)(const struct chip_tsadc_table *table,
141 int code, int trim_base, int trim_base_frac);
142 int (*set_clk_rate)(struct platform_device *pdev);
143
144 /* Per-table methods */
145 struct chip_tsadc_table table;
146 };
147
148 /**
149 * struct rockchip_thermal_sensor - hold the information of thermal sensor
150 * @thermal: pointer to the platform/configuration data
151 * @tzd: pointer to a thermal zone
152 * @id: identifier of the thermal sensor
153 * @trim_temp: the trim temp of the thermal sensor
154 * @tshut_temp: the hardware-controlled shutdown temperature value
155 */
156 struct rockchip_thermal_sensor {
157 struct rockchip_thermal_data *thermal;
158 struct thermal_zone_device *tzd;
159 int id;
160 int trim_temp;
161 int tshut_temp;
162 };
163
164 /**
165 * struct rockchip_thermal_data - hold the private data of thermal driver
166 * @chip: pointer to the platform/configuration data
167 * @pdev: platform device of thermal
168 * @reset: the reset controller of tsadc
169 * @sensors: array of thermal sensors
170 * @clk: the bulk clk of tsadc, include controller clock and peripherals bus clock
171 * @num_clks: the number of tsadc clks
172 * @grf: the general register file will be used to do static set by software
173 * @regs: the base address of tsadc controller
174 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
175 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
176 * @pinctrl: the pinctrl of tsadc
177 * @gpio_state: pinctrl select gpio function
178 * @otp_state: pinctrl select otp out function
179 * @panic_nb: panic notifier block
180 */
181 struct rockchip_thermal_data {
182 const struct rockchip_tsadc_chip *chip;
183 struct platform_device *pdev;
184 struct reset_control *reset;
185
186 struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS];
187
188 struct clk_bulk_data *clks;
189 int num_clks;
190
191 struct regmap *grf;
192 void __iomem *regs;
193
194 enum tshut_mode tshut_mode;
195 enum tshut_polarity tshut_polarity;
196 struct pinctrl *pinctrl;
197 struct pinctrl_state *gpio_state;
198 struct pinctrl_state *otp_state;
199
200 struct notifier_block panic_nb;
201 };
202
203 /**
204 * TSADC Sensor Register description:
205 *
206 * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it.
207 * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399)
208 *
209 */
210 #define TSADCV2_USER_CON 0x00
211 #define TSADCV2_AUTO_CON 0x04
212 #define TSADCV2_INT_EN 0x08
213 #define TSADCV2_INT_PD 0x0c
214 #define TSADCV3_AUTO_SRC_CON 0x0c
215 #define TSADCV3_HT_INT_EN 0x14
216 #define TSADCV3_HSHUT_GPIO_INT_EN 0x18
217 #define TSADCV3_HSHUT_CRU_INT_EN 0x1c
218 #define TSADCV3_INT_PD 0x24
219 #define TSADCV3_HSHUT_PD 0x28
220 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04)
221 #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04)
222 #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04)
223 #define TSADCV3_DATA(chn) (0x2c + (chn) * 0x04)
224 #define TSADCV3_COMP_INT(chn) (0x6c + (chn) * 0x04)
225 #define TSADCV3_COMP_SHUT(chn) (0x10c + (chn) * 0x04)
226 #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60
227 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64
228 #define TSADCV3_HIGHT_INT_DEBOUNCE 0x14c
229 #define TSADCV3_HIGHT_TSHUT_DEBOUNCE 0x150
230 #define TSADCV2_AUTO_PERIOD 0x68
231 #define TSADCV2_AUTO_PERIOD_HT 0x6c
232 #define TSADCV3_AUTO_PERIOD 0x154
233 #define TSADCV3_AUTO_PERIOD_HT 0x158
234 #define TSADCV9_Q_MAX 0x210
235 #define TSADCV9_FLOW_CON 0x218
236
237 #define TSADCV2_AUTO_EN BIT(0)
238 #define TSADCV2_AUTO_EN_MASK BIT(16)
239 #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
240 #define TSADCV3_AUTO_SRC_EN(chn) BIT(chn)
241 #define TSADCV3_AUTO_SRC_EN_MASK(chn) BIT(16 + chn)
242 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
243 #define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24)
244
245 #define TSADCV3_AUTO_Q_SEL_EN BIT(1)
246 #define TSADCV3_AUTO_Q_SEL_EN_MASK BIT(17)
247
248 #define TSADCV2_INT_SRC_EN(chn) BIT(chn)
249 #define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn))
250 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
251 #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
252
253 #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
254 #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16)
255 #define TSADCV4_INT_PD_CLEAR_MASK 0xffffffff
256
257 #define TSADCV2_DATA_MASK 0xfff
258 #define TSADCV3_DATA_MASK 0x3ff
259 #define TSADCV4_DATA_MASK 0x1ff
260 #define TSADCV5_DATA_MASK 0x7ff
261
262 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
263 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
264 #define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */
265 #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */
266 #define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */
267 #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 /* 2.5ms */
268 #define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */
269 #define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */
270 #define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */
271 #define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */
272 #define TSADCV7_AUTO_PERIOD_TIME 3000 /* 2.5ms */
273 #define TSADCV7_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */
274 #define TSADCV12_AUTO_PERIOD_TIME 3000 /* 2.5ms */
275 #define TSADCV12_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */
276 #define TSADCV3_Q_MAX_VAL 0x7ff /* 11bit 2047 */
277 #define TSADCV12_Q_MAX_VAL 0xfff /* 12bit 4095 */
278
279 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
280 #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */
281
282 #define TSADCV9_AUTO_SRC (0x10001 << 0)
283 #define TSADCV9_PD_MODE (0x10001 << 4)
284 #define TSADCV9_Q_MAX_VAL (0xffff0400 << 0)
285
286 #define GRF_SARADC_TESTBIT 0x0e644
287 #define GRF_TSADC_TESTBIT_L 0x0e648
288 #define GRF_TSADC_TESTBIT_H 0x0e64c
289
290 #define PX30_GRF_SOC_CON0 0x0400
291 #define PX30_GRF_SOC_CON2 0x0408
292
293 #define RK1808_BUS_GRF_SOC_CON0 0x0400
294
295 #define RK3528_GRF_TSADC_CON 0x40030
296
297 #define RK3562_GRF_TSADC_CON 0x0580
298
299 #define RK3568_GRF_TSADC_CON 0x0600
300 #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0)
301 #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1)
302 #define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2)
303 #define RK3568_GRF_TSADC_TSEN (0x10001 << 8)
304
305 #define RV1106_VOGRF_TSADC_CON 0x6000C
306 #define RV1106_VOGRF_TSADC_TSEN (0x10001 << 8)
307 #define RV1106_VOGRF_TSADC_ANA (0xff0007 << 0)
308
309 #define RV1126_GRF0_TSADC_CON 0x0100
310
311 #define RV1126_GRF0_TSADC_TRM (0xff0077 << 0)
312 #define RV1126_GRF0_TSADC_SHUT_2CRU (0x30003 << 10)
313 #define RV1126_GRF0_TSADC_SHUT_2GPIO (0x70007 << 12)
314
315 #define GRF_SARADC_TESTBIT_ON (0x10001 << 2)
316 #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2)
317 #define GRF_TSADC_BANDGAP_CHOPPER_EN (0x10001 << 2)
318 #define GRF_TSADC_VCM_EN_L (0x10001 << 7)
319 #define GRF_TSADC_VCM_EN_H (0x10001 << 7)
320
321 #define GRF_CON_TSADC_CH_INV (0x10001 << 1)
322 #define PX30S_TSADC_TDC_MODE (0x10001 << 4)
323 #define PX30S_TSADC_TRIM (0xf0007 << 0)
324
325
326 /* -40 to 125 is reliable, outside the range existed unreliability */
327 #define MIN_TEMP (-60000)
328 #define MAX_TEMP (180000)
329
330 /**
331 * struct tsadc_table - code to temperature conversion table
332 * @code: the value of adc channel
333 * @temp: the temperature
334 * Note:
335 * code to temperature mapping of the temperature sensor is a piece wise linear
336 * curve.Any temperature, code faling between to 2 give temperatures can be
337 * linearly interpolated.
338 * Code to Temperature mapping should be updated based on manufacturer results.
339 */
340 struct tsadc_table {
341 u32 code;
342 int temp;
343 };
344
345 static const struct tsadc_table rv1106_code_table[] = {
346 {0, MIN_TEMP},
347 {363, MIN_TEMP},
348 {396, -40000},
349 {504, 25000},
350 {605, 85000},
351 {673, 125000},
352 {758, MAX_TEMP},
353 {TSADCV2_DATA_MASK, MAX_TEMP},
354 };
355
356 static const struct tsadc_table rv1108_table[] = {
357 {0, MIN_TEMP},
358 {342, MIN_TEMP},
359 {374, -40000},
360 {382, -35000},
361 {389, -30000},
362 {397, -25000},
363 {405, -20000},
364 {413, -15000},
365 {421, -10000},
366 {429, -5000},
367 {436, 0},
368 {444, 5000},
369 {452, 10000},
370 {460, 15000},
371 {468, 20000},
372 {476, 25000},
373 {483, 30000},
374 {491, 35000},
375 {499, 40000},
376 {507, 45000},
377 {515, 50000},
378 {523, 55000},
379 {531, 60000},
380 {539, 65000},
381 {547, 70000},
382 {555, 75000},
383 {562, 80000},
384 {570, 85000},
385 {578, 90000},
386 {586, 95000},
387 {594, 100000},
388 {602, 105000},
389 {610, 110000},
390 {618, 115000},
391 {626, 120000},
392 {634, 125000},
393 {722, MAX_TEMP},
394 {TSADCV2_DATA_MASK, MAX_TEMP},
395 };
396
397 static const struct tsadc_table rk1808_code_table[] = {
398 {0, MIN_TEMP},
399 {3423, MIN_TEMP},
400 {3455, -40000},
401 {3463, -35000},
402 {3471, -30000},
403 {3479, -25000},
404 {3487, -20000},
405 {3495, -15000},
406 {3503, -10000},
407 {3511, -5000},
408 {3519, 0},
409 {3527, 5000},
410 {3535, 10000},
411 {3543, 15000},
412 {3551, 20000},
413 {3559, 25000},
414 {3567, 30000},
415 {3576, 35000},
416 {3584, 40000},
417 {3592, 45000},
418 {3600, 50000},
419 {3609, 55000},
420 {3617, 60000},
421 {3625, 65000},
422 {3633, 70000},
423 {3642, 75000},
424 {3650, 80000},
425 {3659, 85000},
426 {3667, 90000},
427 {3675, 95000},
428 {3684, 100000},
429 {3692, 105000},
430 {3701, 110000},
431 {3709, 115000},
432 {3718, 120000},
433 {3726, 125000},
434 {3820, MAX_TEMP},
435 {TSADCV2_DATA_MASK, MAX_TEMP},
436 };
437
438 static const struct tsadc_table rk3228_code_table[] = {
439 {0, MIN_TEMP},
440 {568, MIN_TEMP},
441 {588, -40000},
442 {593, -35000},
443 {598, -30000},
444 {603, -25000},
445 {608, -20000},
446 {613, -15000},
447 {618, -10000},
448 {623, -5000},
449 {629, 0},
450 {634, 5000},
451 {639, 10000},
452 {644, 15000},
453 {649, 20000},
454 {654, 25000},
455 {660, 30000},
456 {665, 35000},
457 {670, 40000},
458 {675, 45000},
459 {681, 50000},
460 {686, 55000},
461 {691, 60000},
462 {696, 65000},
463 {702, 70000},
464 {707, 75000},
465 {712, 80000},
466 {717, 85000},
467 {723, 90000},
468 {728, 95000},
469 {733, 100000},
470 {738, 105000},
471 {744, 110000},
472 {749, 115000},
473 {754, 120000},
474 {760, 125000},
475 {821, MAX_TEMP},
476 {TSADCV2_DATA_MASK, MAX_TEMP},
477 };
478
479 static const struct tsadc_table rk3288_code_table[] = {
480 {TSADCV2_DATA_MASK, MIN_TEMP},
481 {3833, MIN_TEMP},
482 {3800, -40000},
483 {3792, -35000},
484 {3783, -30000},
485 {3774, -25000},
486 {3765, -20000},
487 {3756, -15000},
488 {3747, -10000},
489 {3737, -5000},
490 {3728, 0},
491 {3718, 5000},
492 {3708, 10000},
493 {3698, 15000},
494 {3688, 20000},
495 {3678, 25000},
496 {3667, 30000},
497 {3656, 35000},
498 {3645, 40000},
499 {3634, 45000},
500 {3623, 50000},
501 {3611, 55000},
502 {3600, 60000},
503 {3588, 65000},
504 {3575, 70000},
505 {3563, 75000},
506 {3550, 80000},
507 {3537, 85000},
508 {3524, 90000},
509 {3510, 95000},
510 {3496, 100000},
511 {3482, 105000},
512 {3467, 110000},
513 {3452, 115000},
514 {3437, 120000},
515 {3421, 125000},
516 {3350, 145000},
517 {3270, 165000},
518 {3195, MAX_TEMP},
519 {0, MAX_TEMP},
520 };
521
522 static const struct tsadc_table rk3328_code_table[] = {
523 {0, MIN_TEMP},
524 {261, MIN_TEMP},
525 {296, -40000},
526 {304, -35000},
527 {313, -30000},
528 {331, -20000},
529 {340, -15000},
530 {349, -10000},
531 {359, -5000},
532 {368, 0},
533 {378, 5000},
534 {388, 10000},
535 {398, 15000},
536 {408, 20000},
537 {418, 25000},
538 {429, 30000},
539 {440, 35000},
540 {451, 40000},
541 {462, 45000},
542 {473, 50000},
543 {485, 55000},
544 {496, 60000},
545 {508, 65000},
546 {521, 70000},
547 {533, 75000},
548 {546, 80000},
549 {559, 85000},
550 {572, 90000},
551 {586, 95000},
552 {600, 100000},
553 {614, 105000},
554 {629, 110000},
555 {644, 115000},
556 {659, 120000},
557 {675, 125000},
558 {745, 145000},
559 {825, 165000},
560 {900, MAX_TEMP},
561 {TSADCV2_DATA_MASK, MAX_TEMP},
562 };
563
564 static const struct tsadc_table rk3368_code_table[] = {
565 {0, MIN_TEMP},
566 {98, MIN_TEMP},
567 {106, -40000},
568 {108, -35000},
569 {110, -30000},
570 {112, -25000},
571 {114, -20000},
572 {116, -15000},
573 {118, -10000},
574 {120, -5000},
575 {122, 0},
576 {124, 5000},
577 {126, 10000},
578 {128, 15000},
579 {130, 20000},
580 {132, 25000},
581 {134, 30000},
582 {136, 35000},
583 {138, 40000},
584 {140, 45000},
585 {142, 50000},
586 {144, 55000},
587 {146, 60000},
588 {148, 65000},
589 {150, 70000},
590 {152, 75000},
591 {154, 80000},
592 {156, 85000},
593 {158, 90000},
594 {160, 95000},
595 {162, 100000},
596 {163, 105000},
597 {165, 110000},
598 {167, 115000},
599 {169, 120000},
600 {171, 125000},
601 {193, MAX_TEMP},
602 {TSADCV3_DATA_MASK, MAX_TEMP},
603 };
604
605 static const struct tsadc_table rk3399_code_table[] = {
606 {0, MIN_TEMP},
607 {368, MIN_TEMP},
608 {402, -40000},
609 {410, -35000},
610 {419, -30000},
611 {427, -25000},
612 {436, -20000},
613 {444, -15000},
614 {453, -10000},
615 {461, -5000},
616 {470, 0},
617 {478, 5000},
618 {487, 10000},
619 {496, 15000},
620 {504, 20000},
621 {513, 25000},
622 {521, 30000},
623 {530, 35000},
624 {538, 40000},
625 {547, 45000},
626 {555, 50000},
627 {564, 55000},
628 {573, 60000},
629 {581, 65000},
630 {590, 70000},
631 {599, 75000},
632 {607, 80000},
633 {616, 85000},
634 {624, 90000},
635 {633, 95000},
636 {642, 100000},
637 {650, 105000},
638 {659, 110000},
639 {668, 115000},
640 {677, 120000},
641 {685, 125000},
642 {782, MAX_TEMP},
643 {TSADCV3_DATA_MASK, MAX_TEMP},
644 };
645
646 static const struct tsadc_table rk3528_code_table[] = {
647 {0, MIN_TEMP},
648 {1386, MIN_TEMP},
649 {1419, -40000},
650 {1427, -35000},
651 {1435, -30000},
652 {1443, -25000},
653 {1452, -20000},
654 {1460, -15000},
655 {1468, -10000},
656 {1477, -5000},
657 {1486, 0},
658 {1494, 5000},
659 {1502, 10000},
660 {1510, 15000},
661 {1519, 20000},
662 {1527, 25000},
663 {1535, 30000},
664 {1544, 35000},
665 {1552, 40000},
666 {1561, 45000},
667 {1569, 50000},
668 {1578, 55000},
669 {1586, 60000},
670 {1594, 65000},
671 {1603, 70000},
672 {1612, 75000},
673 {1620, 80000},
674 {1628, 85000},
675 {1637, 90000},
676 {1646, 95000},
677 {1654, 100000},
678 {1662, 105000},
679 {1671, 110000},
680 {1679, 115000},
681 {1688, 120000},
682 {1696, 125000},
683 {1790, MAX_TEMP},
684 {TSADCV5_DATA_MASK, MAX_TEMP},
685 };
686
687 static const struct tsadc_table rk3562_code_table[] = {
688 {0, MIN_TEMP},
689 {1385, MIN_TEMP},
690 {1419, -40000},
691 {1428, -35000},
692 {1436, -30000},
693 {1445, -25000},
694 {1453, -20000},
695 {1462, -15000},
696 {1470, -10000},
697 {1479, -5000},
698 {1487, 0},
699 {1496, 5000},
700 {1504, 10000},
701 {1512, 15000},
702 {1521, 20000},
703 {1529, 25000},
704 {1538, 30000},
705 {1546, 35000},
706 {1555, 40000},
707 {1563, 45000},
708 {1572, 50000},
709 {1580, 55000},
710 {1589, 60000},
711 {1598, 65000},
712 {1606, 70000},
713 {1615, 75000},
714 {1623, 80000},
715 {1632, 85000},
716 {1640, 90000},
717 {1648, 95000},
718 {1657, 100000},
719 {1666, 105000},
720 {1674, 110000},
721 {1682, 115000},
722 {1691, 120000},
723 {1699, 125000},
724 {1793, MAX_TEMP},
725 {TSADCV2_DATA_MASK, MAX_TEMP},
726 };
727
728 static const struct tsadc_table rk3568_code_table[] = {
729 {0, MIN_TEMP},
730 {1448, MIN_TEMP},
731 {1584, -40000},
732 {1620, -35000},
733 {1652, -30000},
734 {1688, -25000},
735 {1720, -20000},
736 {1756, -15000},
737 {1788, -10000},
738 {1824, -5000},
739 {1856, 0},
740 {1892, 5000},
741 {1924, 10000},
742 {1956, 15000},
743 {1992, 20000},
744 {2024, 25000},
745 {2060, 30000},
746 {2092, 35000},
747 {2128, 40000},
748 {2160, 45000},
749 {2196, 50000},
750 {2228, 55000},
751 {2264, 60000},
752 {2300, 65000},
753 {2332, 70000},
754 {2368, 75000},
755 {2400, 80000},
756 {2436, 85000},
757 {2468, 90000},
758 {2500, 95000},
759 {2536, 100000},
760 {2572, 105000},
761 {2604, 110000},
762 {2636, 115000},
763 {2672, 120000},
764 {2704, 125000},
765 {3076, MAX_TEMP},
766 {TSADCV2_DATA_MASK, MAX_TEMP},
767 };
768
769 static const struct tsadc_table rk3588_code_table[] = {
770 {0, MIN_TEMP},
771 {194, MIN_TEMP},
772 {215, -40000},
773 {285, 25000},
774 {350, 85000},
775 {395, 125000},
776 {455, MAX_TEMP},
777 {TSADCV4_DATA_MASK, MAX_TEMP},
778 };
779
rk_tsadcv2_temp_to_code(const struct chip_tsadc_table * table,int temp)780 static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table,
781 int temp)
782 {
783 int high, low, mid;
784 unsigned long num;
785 unsigned int denom;
786 u32 error = table->data_mask;
787
788 if (table->kNum)
789 return (((temp / 1000) * table->kNum) / 1000 + table->bNum);
790
791 low = 0;
792 high = (table->length - 1) - 1; /* ignore the last check for table */
793 mid = (high + low) / 2;
794
795 /* Return mask code data when the temp is over table range */
796 if (temp < table->id[low].temp || temp > table->id[high].temp)
797 goto exit;
798
799 while (low <= high) {
800 if (temp == table->id[mid].temp)
801 return table->id[mid].code;
802 else if (temp < table->id[mid].temp)
803 high = mid - 1;
804 else
805 low = mid + 1;
806 mid = (low + high) / 2;
807 }
808
809 /*
810 * The conversion code granularity provided by the table. Let's
811 * assume that the relationship between temperature and
812 * analog value between 2 table entries is linear and interpolate
813 * to produce less granular result.
814 */
815 num = abs(table->id[mid + 1].code - table->id[mid].code);
816 num *= temp - table->id[mid].temp;
817 denom = table->id[mid + 1].temp - table->id[mid].temp;
818
819 switch (table->mode) {
820 case ADC_DECREMENT:
821 return table->id[mid].code - (num / denom);
822 case ADC_INCREMENT:
823 return table->id[mid].code + (num / denom);
824 default:
825 pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
826 return error;
827 }
828
829 exit:
830 pr_err("%s: invalid temperature, temp=%d error=%d\n",
831 __func__, temp, error);
832 return error;
833 }
834
rk_tsadcv2_code_to_temp(const struct chip_tsadc_table * table,u32 code,int * temp)835 static int rk_tsadcv2_code_to_temp(const struct chip_tsadc_table *table,
836 u32 code, int *temp)
837 {
838 unsigned int low = 1;
839 unsigned int high = table->length - 1;
840 unsigned int mid = (low + high) / 2;
841 unsigned int num;
842 unsigned long denom;
843
844 if (table->kNum) {
845 *temp = (((int)code - table->bNum) * 10000 / table->kNum) * 100;
846 if (*temp < MIN_TEMP || *temp > MAX_TEMP)
847 return -EAGAIN;
848 return 0;
849 }
850
851 WARN_ON(table->length < 2);
852
853 switch (table->mode) {
854 case ADC_DECREMENT:
855 code &= table->data_mask;
856 if (code <= table->id[high].code)
857 return -EAGAIN; /* Incorrect reading */
858
859 while (low <= high) {
860 if (code >= table->id[mid].code &&
861 code < table->id[mid - 1].code)
862 break;
863 else if (code < table->id[mid].code)
864 low = mid + 1;
865 else
866 high = mid - 1;
867
868 mid = (low + high) / 2;
869 }
870 break;
871 case ADC_INCREMENT:
872 code &= table->data_mask;
873 if (code < table->id[low].code)
874 return -EAGAIN; /* Incorrect reading */
875
876 while (low <= high) {
877 if (code <= table->id[mid].code &&
878 code > table->id[mid - 1].code)
879 break;
880 else if (code > table->id[mid].code)
881 low = mid + 1;
882 else
883 high = mid - 1;
884
885 mid = (low + high) / 2;
886 }
887 break;
888 default:
889 pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
890 return -EINVAL;
891 }
892
893 /*
894 * The 5C granularity provided by the table is too much. Let's
895 * assume that the relationship between sensor readings and
896 * temperature between 2 table entries is linear and interpolate
897 * to produce less granular result.
898 */
899 num = table->id[mid].temp - table->id[mid - 1].temp;
900 num *= abs(table->id[mid - 1].code - code);
901 denom = abs(table->id[mid - 1].code - table->id[mid].code);
902 *temp = table->id[mid - 1].temp + (num / denom);
903
904 return 0;
905 }
906
907 /**
908 * rk_tsadcv2_initialize - initialize TASDC Controller.
909 * @grf: the general register file will be used to do static set by software
910 * @regs: the base address of tsadc controller
911 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
912 *
913 * (1) Set TSADC_V2_AUTO_PERIOD:
914 * Configure the interleave between every two accessing of
915 * TSADC in normal operation.
916 *
917 * (2) Set TSADCV2_AUTO_PERIOD_HT:
918 * Configure the interleave between every two accessing of
919 * TSADC after the temperature is higher than COM_SHUT or COM_INT.
920 *
921 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
922 * If the temperature is higher than COMP_INT or COMP_SHUT for
923 * "debounce" times, TSADC controller will generate interrupt or TSHUT.
924 */
rk_tsadcv2_initialize(struct regmap * grf,void __iomem * regs,enum tshut_polarity tshut_polarity)925 static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs,
926 enum tshut_polarity tshut_polarity)
927 {
928 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
929 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
930 regs + TSADCV2_AUTO_CON);
931 else
932 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
933 regs + TSADCV2_AUTO_CON);
934
935 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
936 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
937 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
938 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
939 regs + TSADCV2_AUTO_PERIOD_HT);
940 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
941 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
942 }
943
944 /**
945 * rk_tsadcv3_initialize - initialize TASDC Controller.
946 * @grf: the general register file will be used to do static set by software
947 * @regs: the base address of tsadc controller
948 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
949 *
950 * (1) The tsadc control power sequence.
951 *
952 * (2) Set TSADC_V2_AUTO_PERIOD:
953 * Configure the interleave between every two accessing of
954 * TSADC in normal operation.
955 *
956 * (2) Set TSADCV2_AUTO_PERIOD_HT:
957 * Configure the interleave between every two accessing of
958 * TSADC after the temperature is higher than COM_SHUT or COM_INT.
959 *
960 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
961 * If the temperature is higher than COMP_INT or COMP_SHUT for
962 * "debounce" times, TSADC controller will generate interrupt or TSHUT.
963 */
rk_tsadcv3_initialize(struct regmap * grf,void __iomem * regs,enum tshut_polarity tshut_polarity)964 static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs,
965 enum tshut_polarity tshut_polarity)
966 {
967 /* The tsadc control power sequence */
968 if (IS_ERR(grf)) {
969 /* Set interleave value to workround ic time sync issue */
970 writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs +
971 TSADCV2_USER_CON);
972
973 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME,
974 regs + TSADCV2_AUTO_PERIOD);
975 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
976 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
977 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
978 regs + TSADCV2_AUTO_PERIOD_HT);
979 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
980 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
981
982 } else {
983 /* Enable the voltage common mode feature */
984 regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L);
985 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H);
986
987 usleep_range(15, 100); /* The spec note says at least 15 us */
988 regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON);
989 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON);
990 usleep_range(90, 200); /* The spec note says at least 90 us */
991
992 writel_relaxed(TSADCV3_AUTO_PERIOD_TIME,
993 regs + TSADCV2_AUTO_PERIOD);
994 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
995 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
996 writel_relaxed(TSADCV3_AUTO_PERIOD_HT_TIME,
997 regs + TSADCV2_AUTO_PERIOD_HT);
998 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
999 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
1000 }
1001
1002 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
1003 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
1004 regs + TSADCV2_AUTO_CON);
1005 else
1006 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
1007 regs + TSADCV2_AUTO_CON);
1008 }
1009
rk_tsadcv4_initialize(struct regmap * grf,void __iomem * regs,enum tshut_polarity tshut_polarity)1010 static void rk_tsadcv4_initialize(struct regmap *grf, void __iomem *regs,
1011 enum tshut_polarity tshut_polarity)
1012 {
1013 rk_tsadcv2_initialize(grf, regs, tshut_polarity);
1014 regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV);
1015 }
1016
rk_tsadcv5_initialize(struct regmap * grf,void __iomem * regs,enum tshut_polarity tshut_polarity)1017 static void rk_tsadcv5_initialize(struct regmap *grf, void __iomem *regs,
1018 enum tshut_polarity tshut_polarity)
1019 {
1020 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
1021 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
1022 regs + TSADCV2_AUTO_CON);
1023 else
1024 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
1025 regs + TSADCV2_AUTO_CON);
1026
1027 writel_relaxed(TSADCV5_USER_INTER_PD_SOC, regs + TSADCV2_USER_CON);
1028
1029 writel_relaxed(TSADCV5_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
1030 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
1031 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
1032 writel_relaxed(TSADCV5_AUTO_PERIOD_HT_TIME,
1033 regs + TSADCV2_AUTO_PERIOD_HT);
1034 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
1035 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
1036
1037 if (!IS_ERR(grf))
1038 regmap_write(grf, RK1808_BUS_GRF_SOC_CON0,
1039 GRF_TSADC_BANDGAP_CHOPPER_EN);
1040 }
1041
rk_tsadcv6_initialize(struct regmap * grf,void __iomem * regs,enum tshut_polarity tshut_polarity)1042 static void rk_tsadcv6_initialize(struct regmap *grf, void __iomem *regs,
1043 enum tshut_polarity tshut_polarity)
1044 {
1045 rk_tsadcv2_initialize(grf, regs, tshut_polarity);
1046
1047 if (!IS_ERR(grf))
1048 regmap_write(grf, RV1126_GRF0_TSADC_CON,
1049 RV1126_GRF0_TSADC_TRM);
1050 }
1051
rk_tsadcv7_initialize(struct regmap * grf,void __iomem * regs,enum tshut_polarity tshut_polarity)1052 static void rk_tsadcv7_initialize(struct regmap *grf, void __iomem *regs,
1053 enum tshut_polarity tshut_polarity)
1054 {
1055 writel_relaxed(TSADCV5_USER_INTER_PD_SOC, regs + TSADCV2_USER_CON);
1056 writel_relaxed(TSADCV5_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
1057 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
1058 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
1059 writel_relaxed(TSADCV5_AUTO_PERIOD_HT_TIME,
1060 regs + TSADCV2_AUTO_PERIOD_HT);
1061 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
1062 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
1063
1064 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
1065 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
1066 regs + TSADCV2_AUTO_CON);
1067 else
1068 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
1069 regs + TSADCV2_AUTO_CON);
1070
1071 /*
1072 * The general register file will is optional
1073 * and might not be available.
1074 */
1075 if (!IS_ERR(grf)) {
1076 regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN);
1077 /*
1078 * RK3568 TRM, section 18.5. requires a delay no less
1079 * than 10us between the rising edge of tsadc_tsen_en
1080 * and the rising edge of tsadc_ana_reg_0/1/2.
1081 */
1082 udelay(15);
1083 regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
1084 regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
1085 regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
1086
1087 /*
1088 * RK3568 TRM, section 18.5. requires a delay no less
1089 * than 90us after the rising edge of tsadc_ana_reg_0/1/2.
1090 */
1091 usleep_range(100, 200);
1092 }
1093 }
1094
rk_tsadcv8_initialize(struct regmap * grf,void __iomem * regs,enum tshut_polarity tshut_polarity)1095 static void rk_tsadcv8_initialize(struct regmap *grf, void __iomem *regs,
1096 enum tshut_polarity tshut_polarity)
1097 {
1098 writel_relaxed(TSADCV6_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
1099 writel_relaxed(TSADCV6_AUTO_PERIOD_HT_TIME,
1100 regs + TSADCV3_AUTO_PERIOD_HT);
1101 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
1102 regs + TSADCV3_HIGHT_INT_DEBOUNCE);
1103 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
1104 regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
1105 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
1106 writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
1107 TSADCV2_AUTO_TSHUT_POLARITY_MASK,
1108 regs + TSADCV2_AUTO_CON);
1109 else
1110 writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
1111 regs + TSADCV2_AUTO_CON);
1112 }
1113
rk_tsadcv9_initialize(struct regmap * grf,void __iomem * regs,enum tshut_polarity tshut_polarity)1114 static void rk_tsadcv9_initialize(struct regmap *grf, void __iomem *regs,
1115 enum tshut_polarity tshut_polarity)
1116 {
1117 regmap_write(grf, RV1106_VOGRF_TSADC_CON, RV1106_VOGRF_TSADC_TSEN);
1118 udelay(10);
1119 regmap_write(grf, RV1106_VOGRF_TSADC_CON, RV1106_VOGRF_TSADC_ANA);
1120 udelay(100);
1121
1122 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
1123 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME,
1124 regs + TSADCV3_AUTO_PERIOD_HT);
1125 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
1126 regs + TSADCV3_HIGHT_INT_DEBOUNCE);
1127 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
1128 regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
1129 writel_relaxed(TSADCV9_AUTO_SRC, regs + TSADCV2_INT_PD);
1130 writel_relaxed(TSADCV9_PD_MODE, regs + TSADCV9_FLOW_CON);
1131 writel_relaxed(TSADCV9_Q_MAX_VAL, regs + TSADCV9_Q_MAX);
1132 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
1133 writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
1134 TSADCV2_AUTO_TSHUT_POLARITY_MASK,
1135 regs + TSADCV2_AUTO_CON);
1136 else
1137 writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
1138 regs + TSADCV2_AUTO_CON);
1139 writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | (TSADCV3_AUTO_Q_SEL_EN << 16),
1140 regs + TSADCV2_AUTO_CON);
1141 }
1142
rk_tsadcv10_initialize(struct regmap * grf,void __iomem * regs,enum tshut_polarity tshut_polarity)1143 static void rk_tsadcv10_initialize(struct regmap *grf, void __iomem *regs,
1144 enum tshut_polarity tshut_polarity)
1145 {
1146 rk_tsadcv2_initialize(grf, regs, tshut_polarity);
1147 if (!IS_ERR(grf)) {
1148 regmap_write(grf, PX30_GRF_SOC_CON0, PX30S_TSADC_TDC_MODE);
1149 regmap_write(grf, PX30_GRF_SOC_CON0, PX30S_TSADC_TRIM);
1150 }
1151 }
1152
rk_tsadcv11_initialize(struct regmap * grf,void __iomem * regs,enum tshut_polarity tshut_polarity)1153 static void rk_tsadcv11_initialize(struct regmap *grf, void __iomem *regs,
1154 enum tshut_polarity tshut_polarity)
1155 {
1156 writel_relaxed(TSADCV7_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
1157 writel_relaxed(TSADCV7_AUTO_PERIOD_HT_TIME,
1158 regs + TSADCV3_AUTO_PERIOD_HT);
1159 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
1160 regs + TSADCV3_HIGHT_INT_DEBOUNCE);
1161 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
1162 regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
1163 writel_relaxed(TSADCV3_Q_MAX_VAL, regs + TSADCV9_Q_MAX);
1164 writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
1165 regs + TSADCV2_AUTO_CON);
1166 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
1167 writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
1168 TSADCV2_AUTO_TSHUT_POLARITY_MASK,
1169 regs + TSADCV2_AUTO_CON);
1170 else
1171 writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
1172 regs + TSADCV2_AUTO_CON);
1173
1174 if (!IS_ERR(grf)) {
1175 regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN);
1176 udelay(15);
1177 regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
1178 regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
1179 regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
1180 usleep_range(100, 200);
1181 }
1182 }
1183
rk_tsadcv12_initialize(struct regmap * grf,void __iomem * regs,enum tshut_polarity tshut_polarity)1184 static void rk_tsadcv12_initialize(struct regmap *grf, void __iomem *regs,
1185 enum tshut_polarity tshut_polarity)
1186 {
1187 writel_relaxed(TSADCV12_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
1188 writel_relaxed(TSADCV12_AUTO_PERIOD_HT_TIME,
1189 regs + TSADCV3_AUTO_PERIOD_HT);
1190 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
1191 regs + TSADCV3_HIGHT_INT_DEBOUNCE);
1192 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
1193 regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
1194 writel_relaxed(TSADCV12_Q_MAX_VAL, regs + TSADCV9_Q_MAX);
1195 writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
1196 regs + TSADCV2_AUTO_CON);
1197 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
1198 writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
1199 TSADCV2_AUTO_TSHUT_POLARITY_MASK,
1200 regs + TSADCV2_AUTO_CON);
1201 else
1202 writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
1203 regs + TSADCV2_AUTO_CON);
1204
1205 if (!IS_ERR(grf)) {
1206 regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN);
1207 udelay(15);
1208 regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
1209 regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
1210 regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
1211 usleep_range(100, 200);
1212 }
1213 }
1214
rk_tsadcv2_irq_ack(void __iomem * regs)1215 static void rk_tsadcv2_irq_ack(void __iomem *regs)
1216 {
1217 u32 val;
1218
1219 val = readl_relaxed(regs + TSADCV2_INT_PD);
1220 writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
1221 }
1222
rk_tsadcv3_irq_ack(void __iomem * regs)1223 static void rk_tsadcv3_irq_ack(void __iomem *regs)
1224 {
1225 u32 val;
1226
1227 val = readl_relaxed(regs + TSADCV2_INT_PD);
1228 writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
1229 }
1230
rk_tsadcv4_irq_ack(void __iomem * regs)1231 static void rk_tsadcv4_irq_ack(void __iomem *regs)
1232 {
1233 u32 val;
1234
1235 val = readl_relaxed(regs + TSADCV3_INT_PD);
1236 writel_relaxed(val & TSADCV4_INT_PD_CLEAR_MASK, regs + TSADCV3_INT_PD);
1237 val = readl_relaxed(regs + TSADCV3_HSHUT_PD);
1238 writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK,
1239 regs + TSADCV3_HSHUT_PD);
1240 }
1241
rk_tsadcv2_control(void __iomem * regs,bool enable)1242 static void rk_tsadcv2_control(void __iomem *regs, bool enable)
1243 {
1244 u32 val;
1245
1246 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
1247 if (enable)
1248 val |= TSADCV2_AUTO_EN;
1249 else
1250 val &= ~TSADCV2_AUTO_EN;
1251
1252 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
1253 }
1254
1255 /**
1256 * rk_tsadcv3_control - the tsadc controller is enabled or disabled.
1257 * @regs: the base address of tsadc controller
1258 * @enable: boolean flag to enable the controller
1259 *
1260 * NOTE: TSADC controller works at auto mode, and some SoCs need set the
1261 * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output
1262 * adc value if setting this bit to enable.
1263 */
rk_tsadcv3_control(void __iomem * regs,bool enable)1264 static void rk_tsadcv3_control(void __iomem *regs, bool enable)
1265 {
1266 u32 val;
1267
1268 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
1269 if (enable)
1270 val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN;
1271 else
1272 val &= ~TSADCV2_AUTO_EN;
1273
1274 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
1275 }
1276
rk_tsadcv4_control(void __iomem * regs,bool enable)1277 static void rk_tsadcv4_control(void __iomem *regs, bool enable)
1278 {
1279 u32 val;
1280
1281 if (enable)
1282 val = TSADCV2_AUTO_EN | TSADCV2_AUTO_EN_MASK;
1283 else
1284 val = TSADCV2_AUTO_EN_MASK;
1285
1286 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
1287 }
1288
rk_tsadcv2_get_temp(const struct chip_tsadc_table * table,int chn,void __iomem * regs,int * temp)1289 static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table,
1290 int chn, void __iomem *regs, int *temp)
1291 {
1292 u32 val;
1293
1294 val = readl_relaxed(regs + TSADCV2_DATA(chn));
1295
1296 return rk_tsadcv2_code_to_temp(table, val, temp);
1297 }
1298
rk_tsadcv4_get_temp(const struct chip_tsadc_table * table,int chn,void __iomem * regs,int * temp)1299 static int rk_tsadcv4_get_temp(const struct chip_tsadc_table *table,
1300 int chn, void __iomem *regs, int *temp)
1301 {
1302 u32 val;
1303
1304 val = readl_relaxed(regs + TSADCV3_DATA(chn));
1305
1306 return rk_tsadcv2_code_to_temp(table, val, temp);
1307 }
1308
rk_tsadcv2_alarm_temp(const struct chip_tsadc_table * table,int chn,void __iomem * regs,int temp)1309 static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table,
1310 int chn, void __iomem *regs, int temp)
1311 {
1312 u32 alarm_value;
1313 u32 int_en, int_clr;
1314
1315 /*
1316 * In some cases, some sensors didn't need the trip points, the
1317 * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
1318 * in the end, ignore this case and disable the high temperature
1319 * interrupt.
1320 */
1321 if (temp == INT_MAX) {
1322 int_clr = readl_relaxed(regs + TSADCV2_INT_EN);
1323 int_clr &= ~TSADCV2_INT_SRC_EN(chn);
1324 writel_relaxed(int_clr, regs + TSADCV2_INT_EN);
1325 return 0;
1326 }
1327
1328 /* Make sure the value is valid */
1329 alarm_value = rk_tsadcv2_temp_to_code(table, temp);
1330 if (alarm_value == table->data_mask)
1331 return -ERANGE;
1332
1333 writel_relaxed(alarm_value & table->data_mask,
1334 regs + TSADCV2_COMP_INT(chn));
1335
1336 int_en = readl_relaxed(regs + TSADCV2_INT_EN);
1337 int_en |= TSADCV2_INT_SRC_EN(chn);
1338 writel_relaxed(int_en, regs + TSADCV2_INT_EN);
1339
1340 return 0;
1341 }
1342
rk_tsadcv3_alarm_temp(const struct chip_tsadc_table * table,int chn,void __iomem * regs,int temp)1343 static int rk_tsadcv3_alarm_temp(const struct chip_tsadc_table *table,
1344 int chn, void __iomem *regs, int temp)
1345 {
1346 u32 alarm_value;
1347
1348 /*
1349 * In some cases, some sensors didn't need the trip points, the
1350 * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
1351 * in the end, ignore this case and disable the high temperature
1352 * interrupt.
1353 */
1354 if (temp == INT_MAX) {
1355 writel_relaxed(TSADCV2_INT_SRC_EN_MASK(chn),
1356 regs + TSADCV3_HT_INT_EN);
1357 return 0;
1358 }
1359 /* Make sure the value is valid */
1360 alarm_value = rk_tsadcv2_temp_to_code(table, temp);
1361 if (alarm_value == table->data_mask)
1362 return -ERANGE;
1363 writel_relaxed(alarm_value & table->data_mask,
1364 regs + TSADCV3_COMP_INT(chn));
1365 writel_relaxed(TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn),
1366 regs + TSADCV3_HT_INT_EN);
1367 return 0;
1368 }
1369
rk_tsadcv2_tshut_temp(const struct chip_tsadc_table * table,int chn,void __iomem * regs,int temp)1370 static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table,
1371 int chn, void __iomem *regs, int temp)
1372 {
1373 u32 tshut_value, val;
1374
1375 /* Make sure the value is valid */
1376 tshut_value = rk_tsadcv2_temp_to_code(table, temp);
1377 if (tshut_value == table->data_mask)
1378 return -ERANGE;
1379
1380 writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn));
1381
1382 /* TSHUT will be valid */
1383 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
1384 writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON);
1385
1386 return 0;
1387 }
1388
rk_tsadcv3_tshut_temp(const struct chip_tsadc_table * table,int chn,void __iomem * regs,int temp)1389 static int rk_tsadcv3_tshut_temp(const struct chip_tsadc_table *table,
1390 int chn, void __iomem *regs, int temp)
1391 {
1392 u32 tshut_value;
1393
1394 /* Make sure the value is valid */
1395 tshut_value = rk_tsadcv2_temp_to_code(table, temp);
1396 if (tshut_value == table->data_mask)
1397 return -ERANGE;
1398
1399 writel_relaxed(tshut_value, regs + TSADCV3_COMP_SHUT(chn));
1400
1401 /* TSHUT will be valid */
1402 writel_relaxed(TSADCV3_AUTO_SRC_EN(chn) | TSADCV3_AUTO_SRC_EN_MASK(chn),
1403 regs + TSADCV3_AUTO_SRC_CON);
1404
1405 return 0;
1406 }
1407
rk_tsadcv2_tshut_mode(struct regmap * grf,int chn,void __iomem * regs,enum tshut_mode mode)1408 static void rk_tsadcv2_tshut_mode(struct regmap *grf, int chn,
1409 void __iomem *regs,
1410 enum tshut_mode mode)
1411 {
1412 u32 val;
1413
1414 val = readl_relaxed(regs + TSADCV2_INT_EN);
1415 if (mode == TSHUT_MODE_OTP) {
1416 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
1417 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
1418 } else {
1419 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
1420 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
1421 }
1422
1423 writel_relaxed(val, regs + TSADCV2_INT_EN);
1424 }
1425
rk_tsadcv3_tshut_mode(struct regmap * grf,int chn,void __iomem * regs,enum tshut_mode mode)1426 static void rk_tsadcv3_tshut_mode(struct regmap *grf, int chn,
1427 void __iomem *regs,
1428 enum tshut_mode mode)
1429 {
1430 u32 val;
1431
1432 val = readl_relaxed(regs + TSADCV2_INT_EN);
1433 if (mode == TSHUT_MODE_OTP) {
1434 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
1435 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
1436 if (!IS_ERR(grf))
1437 regmap_write(grf, RV1126_GRF0_TSADC_CON,
1438 RV1126_GRF0_TSADC_SHUT_2GPIO);
1439 } else {
1440 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
1441 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
1442 if (!IS_ERR(grf))
1443 regmap_write(grf, RV1126_GRF0_TSADC_CON,
1444 RV1126_GRF0_TSADC_SHUT_2CRU);
1445 }
1446
1447 writel_relaxed(val, regs + TSADCV2_INT_EN);
1448 }
1449
rk_tsadcv4_tshut_mode(struct regmap * grf,int chn,void __iomem * regs,enum tshut_mode mode)1450 static void rk_tsadcv4_tshut_mode(struct regmap *grf, int chn,
1451 void __iomem *regs,
1452 enum tshut_mode mode)
1453 {
1454 u32 val_gpio, val_cru;
1455
1456 if (mode == TSHUT_MODE_OTP) {
1457 val_gpio = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
1458 val_cru = TSADCV2_INT_SRC_EN_MASK(chn);
1459 } else {
1460 val_cru = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
1461 val_gpio = TSADCV2_INT_SRC_EN_MASK(chn);
1462 }
1463 writel_relaxed(val_gpio, regs + TSADCV3_HSHUT_GPIO_INT_EN);
1464 writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN);
1465 }
1466
rk_tsadcv1_get_trim_code(const struct chip_tsadc_table * table,int code,int trim_base,int trim_base_frac)1467 static int rk_tsadcv1_get_trim_code(const struct chip_tsadc_table *table,
1468 int code, int trim_base, int trim_base_frac)
1469 {
1470 u32 base_code = (trim_base * table->kNum +
1471 trim_base_frac * table->kNum / 10) / 1000 + table->bNum;
1472
1473 return code - base_code;
1474 }
1475
rk_tsadcv2_get_trim_code(const struct chip_tsadc_table * table,int code,int trim_base,int trim_base_frac)1476 static int rk_tsadcv2_get_trim_code(const struct chip_tsadc_table *table,
1477 int code, int trim_base, int trim_base_frac)
1478 {
1479 int temp = trim_base * 1000 + trim_base_frac * 100;
1480 u32 base_code = rk_tsadcv2_temp_to_code(table, temp);
1481
1482 return code - base_code;
1483 }
1484
rk_tsadcv3_get_trim_code(const struct chip_tsadc_table * table,int code,int trim_base,int trim_base_frac)1485 static int rk_tsadcv3_get_trim_code(const struct chip_tsadc_table *table,
1486 int code, int trim_base, int trim_base_frac)
1487 {
1488 int temp = trim_base * 1000 + trim_base_frac * 100;
1489 u32 base_code = rk_tsadcv2_temp_to_code(table, temp);
1490
1491 rk_tsadcv2_temp_to_code(table, temp);
1492
1493 return (TSADCV3_Q_MAX_VAL - code) - base_code;
1494 }
1495
rk_tsadcv1_set_clk_rate(struct platform_device * pdev)1496 static int rk_tsadcv1_set_clk_rate(struct platform_device *pdev)
1497 {
1498 struct clk *clk;
1499 int error;
1500
1501 clk = devm_clk_get(&pdev->dev, "tsadc");
1502 if (IS_ERR(clk)) {
1503 error = PTR_ERR(clk);
1504 dev_err(&pdev->dev, "failed to get tsadc clock\n");
1505 return error;
1506 }
1507 error = clk_set_rate(clk, 4000000);
1508 if (error < 0) {
1509 devm_clk_put(&pdev->dev, clk);
1510 dev_err(&pdev->dev,
1511 "failed to set tsadc clk rate to 4000000Hz\n");
1512 return error;
1513 }
1514 devm_clk_put(&pdev->dev, clk);
1515
1516 return 0;
1517 }
1518
1519 static const struct rockchip_tsadc_chip px30_tsadc_data = {
1520 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1521 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1522 .chn_num = 2, /* 2 channels for tsadc */
1523
1524 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1525 .tshut_temp = 95000,
1526
1527 .initialize = rk_tsadcv4_initialize,
1528 .irq_ack = rk_tsadcv3_irq_ack,
1529 .control = rk_tsadcv3_control,
1530 .get_temp = rk_tsadcv2_get_temp,
1531 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1532 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1533 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1534
1535 .table = {
1536 .id = rk3328_code_table,
1537 .length = ARRAY_SIZE(rk3328_code_table),
1538 .data_mask = TSADCV2_DATA_MASK,
1539 .mode = ADC_INCREMENT,
1540 },
1541 };
1542
1543 static const struct rockchip_tsadc_chip px30s_tsadc_data = {
1544 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1545 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1546 .chn_num = 2, /* 1 channels for tsadc */
1547 .conversion_time = 2100, /* us */
1548 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1549 .tshut_temp = 95000,
1550 .initialize = rk_tsadcv10_initialize,
1551 .irq_ack = rk_tsadcv3_irq_ack,
1552 .control = rk_tsadcv2_control,
1553 .get_temp = rk_tsadcv2_get_temp,
1554 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1555 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1556 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1557 .set_clk_rate = rk_tsadcv1_set_clk_rate,
1558 .table = {
1559 .kNum = 2699,
1560 .bNum = 2796,
1561 .data_mask = TSADCV2_DATA_MASK,
1562 .mode = ADC_INCREMENT,
1563 },
1564 };
1565
1566 static const struct rockchip_tsadc_chip rv1106_tsadc_data = {
1567 /* top, big_core0, big_core1, little_core, center, gpu, npu */
1568 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1569 .chn_num = 1, /* seven channels for tsadc */
1570 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1571 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1572 .tshut_temp = 95000,
1573 .initialize = rk_tsadcv9_initialize,
1574 .irq_ack = rk_tsadcv4_irq_ack,
1575 .control = rk_tsadcv4_control,
1576 .get_temp = rk_tsadcv4_get_temp,
1577 .set_alarm_temp = rk_tsadcv3_alarm_temp,
1578 .set_tshut_temp = rk_tsadcv3_tshut_temp,
1579 .set_tshut_mode = rk_tsadcv4_tshut_mode,
1580 .table = {
1581 .id = rv1106_code_table,
1582 .length = ARRAY_SIZE(rv1106_code_table),
1583 .data_mask = TSADCV2_DATA_MASK,
1584 .mode = ADC_INCREMENT,
1585 },
1586 };
1587
1588 static const struct rockchip_tsadc_chip rv1108_tsadc_data = {
1589 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1590 .chn_num = 1, /* one channel for tsadc */
1591
1592 .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
1593 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1594 .tshut_temp = 95000,
1595
1596 .initialize = rk_tsadcv2_initialize,
1597 .irq_ack = rk_tsadcv3_irq_ack,
1598 .control = rk_tsadcv3_control,
1599 .get_temp = rk_tsadcv2_get_temp,
1600 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1601 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1602 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1603
1604 .table = {
1605 .id = rv1108_table,
1606 .length = ARRAY_SIZE(rv1108_table),
1607 .data_mask = TSADCV2_DATA_MASK,
1608 .mode = ADC_INCREMENT,
1609 },
1610 };
1611
1612 static const struct rockchip_tsadc_chip rv1126_tsadc_data = {
1613 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1614 .chn_num = 1, /* one channel for tsadc */
1615
1616 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1617 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1618 .tshut_temp = 95000,
1619
1620 .initialize = rk_tsadcv6_initialize,
1621 .irq_ack = rk_tsadcv3_irq_ack,
1622 .control = rk_tsadcv2_control,
1623 .get_temp = rk_tsadcv2_get_temp,
1624 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1625 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1626 .set_tshut_mode = rk_tsadcv3_tshut_mode,
1627 .get_trim_code = rk_tsadcv1_get_trim_code,
1628 .trim_slope = 500,
1629
1630 .table = {
1631 .kNum = 2263,
1632 .bNum = 2704,
1633 .data_mask = TSADCV2_DATA_MASK,
1634 .mode = ADC_INCREMENT,
1635 },
1636 };
1637
1638 static const struct rockchip_tsadc_chip rk1808_tsadc_data = {
1639 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1640 .chn_num = 1, /* one channel for tsadc */
1641
1642 .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
1643 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1644 .tshut_temp = 95000,
1645
1646 .initialize = rk_tsadcv5_initialize,
1647 .irq_ack = rk_tsadcv3_irq_ack,
1648 .control = rk_tsadcv3_control,
1649 .get_temp = rk_tsadcv2_get_temp,
1650 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1651 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1652 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1653
1654 .table = {
1655 .id = rk1808_code_table,
1656 .length = ARRAY_SIZE(rk1808_code_table),
1657 .data_mask = TSADCV2_DATA_MASK,
1658 .mode = ADC_INCREMENT,
1659 },
1660 };
1661
1662 static const struct rockchip_tsadc_chip rk3228_tsadc_data = {
1663 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1664 .chn_num = 1, /* one channel for tsadc */
1665
1666 .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
1667 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1668 .tshut_temp = 95000,
1669
1670 .initialize = rk_tsadcv2_initialize,
1671 .irq_ack = rk_tsadcv3_irq_ack,
1672 .control = rk_tsadcv3_control,
1673 .get_temp = rk_tsadcv2_get_temp,
1674 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1675 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1676 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1677
1678 .table = {
1679 .id = rk3228_code_table,
1680 .length = ARRAY_SIZE(rk3228_code_table),
1681 .data_mask = TSADCV3_DATA_MASK,
1682 .mode = ADC_INCREMENT,
1683 },
1684 };
1685
1686 static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
1687 .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */
1688 .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */
1689 .chn_num = 2, /* two channels for tsadc */
1690
1691 .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
1692 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1693 .tshut_temp = 95000,
1694
1695 .initialize = rk_tsadcv2_initialize,
1696 .irq_ack = rk_tsadcv2_irq_ack,
1697 .control = rk_tsadcv2_control,
1698 .get_temp = rk_tsadcv2_get_temp,
1699 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1700 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1701 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1702
1703 .table = {
1704 .id = rk3288_code_table,
1705 .length = ARRAY_SIZE(rk3288_code_table),
1706 .data_mask = TSADCV2_DATA_MASK,
1707 .mode = ADC_DECREMENT,
1708 },
1709 };
1710
1711 static const struct rockchip_tsadc_chip rk3308_tsadc_data = {
1712 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1713 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1714 .chn_num = 2, /* 2 channels for tsadc */
1715
1716 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1717 .tshut_temp = 95000,
1718
1719 .initialize = rk_tsadcv2_initialize,
1720 .irq_ack = rk_tsadcv3_irq_ack,
1721 .control = rk_tsadcv3_control,
1722 .get_temp = rk_tsadcv2_get_temp,
1723 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1724 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1725 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1726
1727 .table = {
1728 .id = rk3328_code_table,
1729 .length = ARRAY_SIZE(rk3328_code_table),
1730 .data_mask = TSADCV2_DATA_MASK,
1731 .mode = ADC_INCREMENT,
1732 },
1733 };
1734
1735 static const struct rockchip_tsadc_chip rk3308bs_tsadc_data = {
1736 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1737 .chn_num = 1, /* 1 channels for tsadc */
1738
1739 .conversion_time = 2100, /* us */
1740
1741 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1742 .tshut_temp = 95000,
1743
1744 .initialize = rk_tsadcv2_initialize,
1745 .irq_ack = rk_tsadcv3_irq_ack,
1746 .control = rk_tsadcv2_control,
1747 .get_temp = rk_tsadcv2_get_temp,
1748 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1749 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1750 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1751 .set_clk_rate = rk_tsadcv1_set_clk_rate,
1752
1753 .table = {
1754 .kNum = 2699,
1755 .bNum = 2796,
1756 .data_mask = TSADCV2_DATA_MASK,
1757 .mode = ADC_INCREMENT,
1758 },
1759 };
1760
1761 static const struct rockchip_tsadc_chip rk3328_tsadc_data = {
1762 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1763 .chn_num = 1, /* one channels for tsadc */
1764
1765 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1766 .tshut_temp = 95000,
1767
1768 .initialize = rk_tsadcv2_initialize,
1769 .irq_ack = rk_tsadcv3_irq_ack,
1770 .control = rk_tsadcv3_control,
1771 .get_temp = rk_tsadcv2_get_temp,
1772 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1773 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1774 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1775
1776 .table = {
1777 .id = rk3328_code_table,
1778 .length = ARRAY_SIZE(rk3328_code_table),
1779 .data_mask = TSADCV2_DATA_MASK,
1780 .mode = ADC_INCREMENT,
1781 },
1782 };
1783
1784 static const struct rockchip_tsadc_chip rk3366_tsadc_data = {
1785 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1786 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1787 .chn_num = 2, /* two channels for tsadc */
1788
1789 .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
1790 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1791 .tshut_temp = 95000,
1792
1793 .initialize = rk_tsadcv3_initialize,
1794 .irq_ack = rk_tsadcv3_irq_ack,
1795 .control = rk_tsadcv3_control,
1796 .get_temp = rk_tsadcv2_get_temp,
1797 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1798 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1799 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1800
1801 .table = {
1802 .id = rk3228_code_table,
1803 .length = ARRAY_SIZE(rk3228_code_table),
1804 .data_mask = TSADCV3_DATA_MASK,
1805 .mode = ADC_INCREMENT,
1806 },
1807 };
1808
1809 static const struct rockchip_tsadc_chip rk3368_tsadc_data = {
1810 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1811 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1812 .chn_num = 2, /* two channels for tsadc */
1813
1814 .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
1815 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1816 .tshut_temp = 95000,
1817
1818 .initialize = rk_tsadcv2_initialize,
1819 .irq_ack = rk_tsadcv2_irq_ack,
1820 .control = rk_tsadcv2_control,
1821 .get_temp = rk_tsadcv2_get_temp,
1822 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1823 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1824 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1825
1826 .table = {
1827 .id = rk3368_code_table,
1828 .length = ARRAY_SIZE(rk3368_code_table),
1829 .data_mask = TSADCV3_DATA_MASK,
1830 .mode = ADC_INCREMENT,
1831 },
1832 };
1833
1834 static const struct rockchip_tsadc_chip rk3399_tsadc_data = {
1835 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1836 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1837 .chn_num = 2, /* two channels for tsadc */
1838
1839 .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
1840 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1841 .tshut_temp = 95000,
1842
1843 .initialize = rk_tsadcv3_initialize,
1844 .irq_ack = rk_tsadcv3_irq_ack,
1845 .control = rk_tsadcv3_control,
1846 .get_temp = rk_tsadcv2_get_temp,
1847 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1848 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1849 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1850
1851 .table = {
1852 .id = rk3399_code_table,
1853 .length = ARRAY_SIZE(rk3399_code_table),
1854 .data_mask = TSADCV3_DATA_MASK,
1855 .mode = ADC_INCREMENT,
1856 },
1857 };
1858
1859 static const struct rockchip_tsadc_chip rk3528_tsadc_data = {
1860 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1861 .chn_num = 1, /* one channels for tsadc */
1862
1863 .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
1864 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1865 .tshut_temp = 95000,
1866
1867 .initialize = rk_tsadcv11_initialize,
1868 .irq_ack = rk_tsadcv4_irq_ack,
1869 .control = rk_tsadcv4_control,
1870 .get_temp = rk_tsadcv4_get_temp,
1871 .set_alarm_temp = rk_tsadcv3_alarm_temp,
1872 .set_tshut_temp = rk_tsadcv3_tshut_temp,
1873 .set_tshut_mode = rk_tsadcv4_tshut_mode,
1874
1875 .table = {
1876 .id = rk3528_code_table,
1877 .length = ARRAY_SIZE(rk3528_code_table),
1878 .data_mask = TSADCV2_DATA_MASK,
1879 .mode = ADC_INCREMENT,
1880 },
1881 };
1882
1883 static const struct rockchip_tsadc_chip rk3562_tsadc_data = {
1884 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1885 .chn_num = 1, /* one channels for tsadc */
1886
1887 .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
1888 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1889 .tshut_temp = 95000,
1890
1891 .initialize = rk_tsadcv12_initialize,
1892 .irq_ack = rk_tsadcv4_irq_ack,
1893 .control = rk_tsadcv4_control,
1894 .get_temp = rk_tsadcv4_get_temp,
1895 .set_alarm_temp = rk_tsadcv3_alarm_temp,
1896 .set_tshut_temp = rk_tsadcv3_tshut_temp,
1897 .set_tshut_mode = rk_tsadcv4_tshut_mode,
1898 .get_trim_code = rk_tsadcv3_get_trim_code,
1899 .trim_slope = 588,
1900
1901 .table = {
1902 .id = rk3562_code_table,
1903 .length = ARRAY_SIZE(rk3562_code_table),
1904 .data_mask = TSADCV2_DATA_MASK,
1905 .mode = ADC_INCREMENT,
1906 },
1907 };
1908
1909 static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
1910 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1911 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1912 .chn_num = 2, /* two channels for tsadc */
1913
1914 .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
1915 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1916 .tshut_temp = 95000,
1917
1918 .initialize = rk_tsadcv7_initialize,
1919 .irq_ack = rk_tsadcv3_irq_ack,
1920 .control = rk_tsadcv3_control,
1921 .get_temp = rk_tsadcv2_get_temp,
1922 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1923 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1924 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1925 .get_trim_code = rk_tsadcv2_get_trim_code,
1926 .trim_slope = 147,
1927
1928 .table = {
1929 .id = rk3568_code_table,
1930 .length = ARRAY_SIZE(rk3568_code_table),
1931 .data_mask = TSADCV2_DATA_MASK,
1932 .mode = ADC_INCREMENT,
1933 },
1934 };
1935
1936 static const struct rockchip_tsadc_chip rk3588_tsadc_data = {
1937 /* top, big_core0, big_core1, little_core, center, gpu, npu */
1938 .chn_id = {0, 1, 2, 3, 4, 5, 6},
1939 .chn_num = 7, /* seven channels for tsadc */
1940 .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
1941 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1942 .tshut_temp = 95000,
1943 .initialize = rk_tsadcv8_initialize,
1944 .irq_ack = rk_tsadcv4_irq_ack,
1945 .control = rk_tsadcv4_control,
1946 .get_temp = rk_tsadcv4_get_temp,
1947 .set_alarm_temp = rk_tsadcv3_alarm_temp,
1948 .set_tshut_temp = rk_tsadcv3_tshut_temp,
1949 .set_tshut_mode = rk_tsadcv4_tshut_mode,
1950 .table = {
1951 .id = rk3588_code_table,
1952 .length = ARRAY_SIZE(rk3588_code_table),
1953 .data_mask = TSADCV4_DATA_MASK,
1954 .mode = ADC_INCREMENT,
1955 },
1956 };
1957
1958 static const struct of_device_id of_rockchip_thermal_match[] = {
1959 #ifdef CONFIG_CPU_PX30
1960 { .compatible = "rockchip,px30-tsadc",
1961 .data = (void *)&px30_tsadc_data,
1962 },
1963 { .compatible = "rockchip,px30s-tsadc",
1964 .data = (void *)&px30s_tsadc_data,
1965 },
1966 #endif
1967 #ifdef CONFIG_CPU_RV1106
1968 {
1969 .compatible = "rockchip,rv1106-tsadc",
1970 .data = (void *)&rv1106_tsadc_data,
1971 },
1972 #endif
1973 #ifdef CONFIG_CPU_RV1108
1974 {
1975 .compatible = "rockchip,rv1108-tsadc",
1976 .data = (void *)&rv1108_tsadc_data,
1977 },
1978 #endif
1979 #ifdef CONFIG_CPU_RV1126
1980 {
1981 .compatible = "rockchip,rv1126-tsadc",
1982 .data = (void *)&rv1126_tsadc_data,
1983 },
1984 #endif
1985 #ifdef CONFIG_CPU_RK1808
1986 {
1987 .compatible = "rockchip,rk1808-tsadc",
1988 .data = (void *)&rk1808_tsadc_data,
1989 },
1990 #endif
1991 #ifdef CONFIG_CPU_RK322X
1992 {
1993 .compatible = "rockchip,rk3228-tsadc",
1994 .data = (void *)&rk3228_tsadc_data,
1995 },
1996 #endif
1997 #ifdef CONFIG_CPU_RK3288
1998 {
1999 .compatible = "rockchip,rk3288-tsadc",
2000 .data = (void *)&rk3288_tsadc_data,
2001 },
2002 #endif
2003 #ifdef CONFIG_CPU_RK3308
2004 {
2005 .compatible = "rockchip,rk3308-tsadc",
2006 .data = (void *)&rk3308_tsadc_data,
2007 },
2008 {
2009 .compatible = "rockchip,rk3308bs-tsadc",
2010 .data = (void *)&rk3308bs_tsadc_data,
2011 },
2012 #endif
2013 #ifdef CONFIG_CPU_RK3328
2014 {
2015 .compatible = "rockchip,rk3328-tsadc",
2016 .data = (void *)&rk3328_tsadc_data,
2017 },
2018 #endif
2019 #ifdef CONFIG_CPU_RK3366
2020 {
2021 .compatible = "rockchip,rk3366-tsadc",
2022 .data = (void *)&rk3366_tsadc_data,
2023 },
2024 #endif
2025 #ifdef CONFIG_CPU_RK3368
2026 {
2027 .compatible = "rockchip,rk3368-tsadc",
2028 .data = (void *)&rk3368_tsadc_data,
2029 },
2030 #endif
2031 #ifdef CONFIG_CPU_RK3399
2032 {
2033 .compatible = "rockchip,rk3399-tsadc",
2034 .data = (void *)&rk3399_tsadc_data,
2035 },
2036 #endif
2037 #ifdef CONFIG_CPU_RK3528
2038 {
2039 .compatible = "rockchip,rk3528-tsadc",
2040 .data = (void *)&rk3528_tsadc_data,
2041 },
2042 #endif
2043 #ifdef CONFIG_CPU_RK3562
2044 {
2045 .compatible = "rockchip,rk3562-tsadc",
2046 .data = (void *)&rk3562_tsadc_data,
2047 },
2048 #endif
2049 #ifdef CONFIG_CPU_RK3568
2050 {
2051 .compatible = "rockchip,rk3568-tsadc",
2052 .data = (void *)&rk3568_tsadc_data,
2053 },
2054 #endif
2055 #ifdef CONFIG_CPU_RK3588
2056 {
2057 .compatible = "rockchip,rk3588-tsadc",
2058 .data = (void *)&rk3588_tsadc_data,
2059 },
2060 #endif
2061 { /* end */ },
2062 };
2063 MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);
2064
2065 static void
rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor * sensor,bool on)2066 rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on)
2067 {
2068 struct thermal_zone_device *tzd = sensor->tzd;
2069
2070 if (on)
2071 thermal_zone_device_enable(tzd);
2072 else
2073 thermal_zone_device_disable(tzd);
2074 }
2075
rockchip_thermal_alarm_irq_thread(int irq,void * dev)2076 static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev)
2077 {
2078 struct rockchip_thermal_data *thermal = dev;
2079 int i;
2080
2081 dev_dbg(&thermal->pdev->dev, "thermal alarm\n");
2082
2083 thermal->chip->irq_ack(thermal->regs);
2084
2085 for (i = 0; i < thermal->chip->chn_num; i++)
2086 thermal_zone_device_update(thermal->sensors[i].tzd,
2087 THERMAL_EVENT_UNSPECIFIED);
2088
2089 return IRQ_HANDLED;
2090 }
2091
rockchip_thermal_set_trips(void * _sensor,int low,int high)2092 static int rockchip_thermal_set_trips(void *_sensor, int low, int high)
2093 {
2094 struct rockchip_thermal_sensor *sensor = _sensor;
2095 struct rockchip_thermal_data *thermal = sensor->thermal;
2096 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
2097
2098 dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n",
2099 __func__, sensor->id, low, high);
2100
2101 high += sensor->trim_temp;
2102
2103 return tsadc->set_alarm_temp(&tsadc->table,
2104 sensor->id, thermal->regs, high);
2105 }
2106
rockchip_thermal_get_temp(void * _sensor,int * out_temp)2107 static int rockchip_thermal_get_temp(void *_sensor, int *out_temp)
2108 {
2109 struct rockchip_thermal_sensor *sensor = _sensor;
2110 struct rockchip_thermal_data *thermal = sensor->thermal;
2111 const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip;
2112 int retval;
2113
2114 retval = tsadc->get_temp(&tsadc->table,
2115 sensor->id, thermal->regs, out_temp);
2116 *out_temp -= sensor->trim_temp;
2117 dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n",
2118 sensor->id, *out_temp, retval);
2119
2120 return retval;
2121 }
2122
2123 static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = {
2124 .get_temp = rockchip_thermal_get_temp,
2125 .set_trips = rockchip_thermal_set_trips,
2126 };
2127
thermal_pinctrl_select_otp(struct rockchip_thermal_data * thermal)2128 static void thermal_pinctrl_select_otp(struct rockchip_thermal_data *thermal)
2129 {
2130 if (!IS_ERR(thermal->pinctrl) && !IS_ERR_OR_NULL(thermal->otp_state))
2131 pinctrl_select_state(thermal->pinctrl,
2132 thermal->otp_state);
2133 }
2134
thermal_pinctrl_select_gpio(struct rockchip_thermal_data * thermal)2135 static void thermal_pinctrl_select_gpio(struct rockchip_thermal_data *thermal)
2136 {
2137 if (!IS_ERR(thermal->pinctrl) && !IS_ERR_OR_NULL(thermal->gpio_state))
2138 pinctrl_select_state(thermal->pinctrl,
2139 thermal->gpio_state);
2140 }
2141
rockchip_get_efuse_value(struct device_node * np,char * porp_name,int * value)2142 static int rockchip_get_efuse_value(struct device_node *np, char *porp_name,
2143 int *value)
2144 {
2145 struct nvmem_cell *cell;
2146 unsigned char *buf;
2147 size_t len;
2148
2149 cell = of_nvmem_cell_get(np, porp_name);
2150 if (IS_ERR(cell))
2151 return PTR_ERR(cell);
2152
2153 buf = (unsigned char *)nvmem_cell_read(cell, &len);
2154
2155 nvmem_cell_put(cell);
2156
2157 if (IS_ERR(buf))
2158 return PTR_ERR(buf);
2159
2160 *value = buf[0];
2161
2162 kfree(buf);
2163
2164 return 0;
2165 }
2166
rockchip_get_trim_configure(struct device * dev,struct device_node * np,struct rockchip_thermal_data * thermal)2167 static int rockchip_get_trim_configure(struct device *dev,
2168 struct device_node *np,
2169 struct rockchip_thermal_data *thermal)
2170 {
2171 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
2172 struct device_node *node;
2173 int trim_base = 0, trim_base_frac = 0, trim_l = 0, trim_h = 0;
2174 int trim_temp, trim_code;
2175 int i, id;
2176
2177 if (!tsadc->get_trim_code)
2178 return 0;
2179 /*
2180 * The tsadc won't to handle the error in here
2181 * since some SoCs didn't need this property.
2182 */
2183 rockchip_get_efuse_value(np, "trim_base", &trim_base);
2184 if (!trim_base)
2185 trim_base = 30;
2186 rockchip_get_efuse_value(np, "trim_base_frac", &trim_base_frac);
2187 /*
2188 * If the tsadc node contains trim_h and trim_l property,
2189 * all channels use the common trim configure, otherwise,
2190 * get trim configure from child nodes.
2191 */
2192 if (!rockchip_get_efuse_value(np, "trim_l", &trim_l) &&
2193 !rockchip_get_efuse_value(np, "trim_h", &trim_h)) {
2194 if (!trim_l && !trim_h)
2195 return 0;
2196 trim_code = tsadc->get_trim_code(&tsadc->table,
2197 (trim_h << 8) | trim_l,
2198 trim_base, trim_base_frac);
2199 trim_temp = thermal->chip->trim_slope * trim_code;
2200 for (i = 0; i < thermal->chip->chn_num; i++) {
2201 thermal->sensors[i].trim_temp = trim_temp;
2202 thermal->sensors[i].tshut_temp += trim_temp;
2203 if (thermal->sensors[i].tshut_temp > MAX_TEMP)
2204 thermal->sensors[i].tshut_temp = MAX_TEMP;
2205 }
2206 } else {
2207 for_each_available_child_of_node(np, node) {
2208 if (of_property_read_u32(node, "reg", &id)) {
2209 dev_info(dev, "Missing tsadc id property\n");
2210 continue;
2211 }
2212 if (id >= SOC_MAX_SENSORS)
2213 continue;
2214 if (rockchip_get_efuse_value(node, "trim_l", &trim_l)) {
2215 dev_info(dev, "ch%d Missing trim_l property\n",
2216 id);
2217 continue;
2218 }
2219 if (rockchip_get_efuse_value(node, "trim_h", &trim_h)) {
2220 dev_info(dev, "ch%d Missing trim_h property\n",
2221 id);
2222 continue;
2223 }
2224 if (!trim_l && !trim_h)
2225 continue;
2226 trim_code = tsadc->get_trim_code(&tsadc->table,
2227 (trim_h << 8) | trim_l,
2228 trim_base,
2229 trim_base_frac);
2230 trim_temp = thermal->chip->trim_slope * trim_code;
2231 thermal->sensors[id].trim_temp = trim_temp;
2232 thermal->sensors[id].tshut_temp += trim_temp;
2233 if (thermal->sensors[id].tshut_temp > MAX_TEMP)
2234 thermal->sensors[id].tshut_temp = MAX_TEMP;
2235 }
2236 }
2237
2238 return 0;
2239 }
2240
rockchip_configure_from_dt(struct device * dev,struct device_node * np,struct rockchip_thermal_data * thermal)2241 static int rockchip_configure_from_dt(struct device *dev,
2242 struct device_node *np,
2243 struct rockchip_thermal_data *thermal)
2244 {
2245 u32 shut_temp, tshut_mode, tshut_polarity;
2246 int i;
2247
2248 if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) {
2249 dev_warn(dev,
2250 "Missing tshut temp property, using default %d\n",
2251 thermal->chip->tshut_temp);
2252 shut_temp = thermal->chip->tshut_temp;
2253 }
2254 if (shut_temp > INT_MAX) {
2255 dev_err(dev, "Invalid tshut temperature specified: %d\n",
2256 shut_temp);
2257 return -ERANGE;
2258 }
2259 for (i = 0; i < thermal->chip->chn_num; i++)
2260 thermal->sensors[i].tshut_temp = shut_temp;
2261
2262 if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) {
2263 dev_warn(dev,
2264 "Missing tshut mode property, using default (%s)\n",
2265 thermal->chip->tshut_mode == TSHUT_MODE_OTP ?
2266 "gpio" : "cru");
2267 thermal->tshut_mode = thermal->chip->tshut_mode;
2268 } else {
2269 thermal->tshut_mode = tshut_mode;
2270 }
2271
2272 if (thermal->tshut_mode > 1) {
2273 dev_err(dev, "Invalid tshut mode specified: %d\n",
2274 thermal->tshut_mode);
2275 return -EINVAL;
2276 }
2277
2278 if (of_property_read_u32(np, "rockchip,hw-tshut-polarity",
2279 &tshut_polarity)) {
2280 dev_warn(dev,
2281 "Missing tshut-polarity property, using default (%s)\n",
2282 thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ?
2283 "low" : "high");
2284 thermal->tshut_polarity = thermal->chip->tshut_polarity;
2285 } else {
2286 thermal->tshut_polarity = tshut_polarity;
2287 }
2288
2289 if (thermal->tshut_polarity > 1) {
2290 dev_err(dev, "Invalid tshut-polarity specified: %d\n",
2291 thermal->tshut_polarity);
2292 return -EINVAL;
2293 }
2294
2295 /* The tsadc wont to handle the error in here since some SoCs didn't
2296 * need this property.
2297 */
2298 thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
2299 if (IS_ERR(thermal->grf))
2300 dev_warn(dev, "Missing rockchip,grf property\n");
2301
2302 rockchip_get_trim_configure(dev, np, thermal);
2303
2304 return 0;
2305 }
2306
2307 static int
rockchip_thermal_register_sensor(struct platform_device * pdev,struct rockchip_thermal_data * thermal,struct rockchip_thermal_sensor * sensor,int id)2308 rockchip_thermal_register_sensor(struct platform_device *pdev,
2309 struct rockchip_thermal_data *thermal,
2310 struct rockchip_thermal_sensor *sensor,
2311 int id)
2312 {
2313 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
2314 int error;
2315
2316 tsadc->set_tshut_mode(thermal->grf, id, thermal->regs,
2317 thermal->tshut_mode);
2318
2319 error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs,
2320 sensor->tshut_temp);
2321 if (error)
2322 dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n",
2323 __func__, sensor->tshut_temp, error);
2324
2325 sensor->thermal = thermal;
2326 sensor->id = id;
2327 sensor->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, id,
2328 sensor, &rockchip_of_thermal_ops);
2329 if (IS_ERR(sensor->tzd)) {
2330 error = PTR_ERR(sensor->tzd);
2331 dev_err(&pdev->dev, "failed to register sensor %d: %d\n",
2332 id, error);
2333 return error;
2334 }
2335
2336 return 0;
2337 }
2338
2339 /**
2340 * Reset TSADC Controller, reset all tsadc registers.
2341 * @reset: the reset controller of tsadc
2342 */
rockchip_thermal_reset_controller(struct reset_control * reset)2343 static void rockchip_thermal_reset_controller(struct reset_control *reset)
2344 {
2345 reset_control_assert(reset);
2346 usleep_range(10, 20);
2347 reset_control_deassert(reset);
2348 }
2349
rockchip_dump_temperature(struct rockchip_thermal_data * thermal)2350 static void rockchip_dump_temperature(struct rockchip_thermal_data *thermal)
2351 {
2352 struct platform_device *pdev;
2353 int i;
2354
2355 if (!thermal)
2356 return;
2357
2358 pdev = thermal->pdev;
2359
2360 for (i = 0; i < thermal->chip->chn_num; i++) {
2361 struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
2362 struct thermal_zone_device *tz = sensor->tzd;
2363
2364 if (tz->temperature != THERMAL_TEMP_INVALID)
2365 dev_warn(&pdev->dev, "channal %d: temperature(%d C)\n",
2366 i, tz->temperature / 1000);
2367 }
2368
2369 if (thermal->regs) {
2370 pr_warn("THERMAL REGS:\n");
2371 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
2372 32, 4, thermal->regs, 0x88, false);
2373 }
2374 }
2375
rockchip_thermal_panic(struct notifier_block * this,unsigned long ev,void * ptr)2376 static int rockchip_thermal_panic(struct notifier_block *this,
2377 unsigned long ev, void *ptr)
2378 {
2379 struct rockchip_thermal_data *thermal;
2380
2381 thermal = container_of(this, struct rockchip_thermal_data, panic_nb);
2382 rockchip_dump_temperature(thermal);
2383
2384 return NOTIFY_DONE;
2385 }
2386
rockchip_thermal_probe(struct platform_device * pdev)2387 static int rockchip_thermal_probe(struct platform_device *pdev)
2388 {
2389 struct device_node *np = pdev->dev.of_node;
2390 struct rockchip_thermal_data *thermal;
2391 const struct of_device_id *match;
2392 struct resource *res;
2393 int irq;
2394 int i;
2395 int error;
2396
2397 match = of_match_node(of_rockchip_thermal_match, np);
2398 if (!match)
2399 return -ENXIO;
2400
2401 irq = platform_get_irq(pdev, 0);
2402 if (irq < 0)
2403 return -EINVAL;
2404
2405 thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data),
2406 GFP_KERNEL);
2407 if (!thermal)
2408 return -ENOMEM;
2409
2410 thermal->pdev = pdev;
2411
2412 thermal->chip = (const struct rockchip_tsadc_chip *)match->data;
2413 if (!thermal->chip)
2414 return -EINVAL;
2415 if (soc_is_px30s())
2416 thermal->chip = &px30s_tsadc_data;
2417 if (soc_is_rk3308bs())
2418 thermal->chip = &rk3308bs_tsadc_data;
2419
2420 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2421 thermal->regs = devm_ioremap_resource(&pdev->dev, res);
2422 if (IS_ERR(thermal->regs))
2423 return PTR_ERR(thermal->regs);
2424
2425 thermal->reset = devm_reset_control_array_get(&pdev->dev, false, false);
2426 if (IS_ERR(thermal->reset)) {
2427 if (PTR_ERR(thermal->reset) != -EPROBE_DEFER)
2428 dev_err(&pdev->dev, "failed to get tsadc reset lines\n");
2429 return PTR_ERR(thermal->reset);
2430 }
2431
2432 thermal->num_clks = devm_clk_bulk_get_all(&pdev->dev, &thermal->clks);
2433 if (thermal->num_clks < 1)
2434 return -ENODEV;
2435
2436 error = clk_bulk_prepare_enable(thermal->num_clks, thermal->clks);
2437 if (error) {
2438 dev_err(&pdev->dev, "failed to prepare enable tsadc bulk clks: %d\n",
2439 error);
2440 return error;
2441 }
2442 platform_set_drvdata(pdev, thermal);
2443
2444 if (thermal->chip->set_clk_rate)
2445 thermal->chip->set_clk_rate(pdev);
2446
2447 thermal->chip->control(thermal->regs, false);
2448
2449 rockchip_thermal_reset_controller(thermal->reset);
2450
2451 error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
2452 if (error) {
2453 dev_err(&pdev->dev, "failed to parse device tree data: %d\n",
2454 error);
2455 goto err_disable_clocks;
2456 }
2457
2458 thermal->chip->initialize(thermal->grf, thermal->regs,
2459 thermal->tshut_polarity);
2460
2461 if (thermal->tshut_mode == TSHUT_MODE_OTP) {
2462 thermal->pinctrl = devm_pinctrl_get(&pdev->dev);
2463 if (IS_ERR(thermal->pinctrl))
2464 dev_err(&pdev->dev, "failed to find thermal pinctrl\n");
2465
2466 thermal->gpio_state = pinctrl_lookup_state(thermal->pinctrl,
2467 "gpio");
2468 if (IS_ERR_OR_NULL(thermal->gpio_state))
2469 dev_err(&pdev->dev, "failed to find thermal gpio state\n");
2470
2471 thermal->otp_state = pinctrl_lookup_state(thermal->pinctrl,
2472 "otpout");
2473 if (IS_ERR_OR_NULL(thermal->otp_state))
2474 dev_err(&pdev->dev, "failed to find thermal otpout state\n");
2475
2476 thermal_pinctrl_select_otp(thermal);
2477 }
2478
2479 for (i = 0; i < thermal->chip->chn_num; i++) {
2480 error = rockchip_thermal_register_sensor(pdev, thermal,
2481 &thermal->sensors[i],
2482 thermal->chip->chn_id[i]);
2483 if (error) {
2484 dev_err(&pdev->dev,
2485 "failed to register sensor[%d] : error = %d\n",
2486 i, error);
2487 goto err_disable_clocks;
2488 }
2489 }
2490
2491 error = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2492 &rockchip_thermal_alarm_irq_thread,
2493 IRQF_ONESHOT,
2494 "rockchip_thermal", thermal);
2495 if (error) {
2496 dev_err(&pdev->dev,
2497 "failed to request tsadc irq: %d\n", error);
2498 goto err_disable_clocks;
2499 }
2500
2501 thermal->chip->control(thermal->regs, true);
2502 if (thermal->chip->conversion_time)
2503 usleep_range(thermal->chip->conversion_time,
2504 thermal->chip->conversion_time + 50);
2505
2506 for (i = 0; i < thermal->chip->chn_num; i++) {
2507 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
2508 thermal->sensors[i].tzd->tzp->no_hwmon = false;
2509 error = thermal_add_hwmon_sysfs(thermal->sensors[i].tzd);
2510 if (error)
2511 dev_warn(&pdev->dev,
2512 "failed to register sensor %d with hwmon: %d\n",
2513 i, error);
2514 }
2515
2516 thermal->panic_nb.notifier_call = rockchip_thermal_panic;
2517 atomic_notifier_chain_register(&panic_notifier_list,
2518 &thermal->panic_nb);
2519
2520 dev_info(&pdev->dev, "tsadc is probed successfully!\n");
2521
2522 return 0;
2523
2524 err_disable_clocks:
2525 clk_bulk_disable_unprepare(thermal->num_clks, thermal->clks);
2526
2527 return error;
2528 }
2529
rockchip_thermal_remove(struct platform_device * pdev)2530 static int rockchip_thermal_remove(struct platform_device *pdev)
2531 {
2532 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
2533 int i;
2534
2535 for (i = 0; i < thermal->chip->chn_num; i++) {
2536 struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
2537
2538 thermal_remove_hwmon_sysfs(sensor->tzd);
2539 rockchip_thermal_toggle_sensor(sensor, false);
2540 }
2541
2542 thermal->chip->control(thermal->regs, false);
2543
2544 clk_bulk_disable_unprepare(thermal->num_clks, thermal->clks);
2545
2546 return 0;
2547 }
2548
rockchip_thermal_shutdown(struct platform_device * pdev)2549 static void rockchip_thermal_shutdown(struct platform_device *pdev)
2550 {
2551 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
2552 int i;
2553
2554 for (i = 0; i < thermal->chip->chn_num; i++) {
2555 int id = thermal->sensors[i].id;
2556
2557 if (thermal->tshut_mode != TSHUT_MODE_CRU)
2558 thermal->chip->set_tshut_mode(thermal->grf, id,
2559 thermal->regs,
2560 TSHUT_MODE_CRU);
2561 }
2562 if (thermal->tshut_mode == TSHUT_MODE_OTP)
2563 thermal_pinctrl_select_gpio(thermal);
2564 }
2565
rockchip_thermal_suspend(struct device * dev)2566 static int __maybe_unused rockchip_thermal_suspend(struct device *dev)
2567 {
2568 struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
2569 int i;
2570
2571 for (i = 0; i < thermal->chip->chn_num; i++)
2572 rockchip_thermal_toggle_sensor(&thermal->sensors[i], false);
2573
2574 thermal->chip->control(thermal->regs, false);
2575
2576 clk_bulk_disable(thermal->num_clks, thermal->clks);
2577
2578 if (thermal->tshut_mode == TSHUT_MODE_OTP)
2579 thermal_pinctrl_select_gpio(thermal);
2580
2581 return 0;
2582 }
2583
rockchip_thermal_resume(struct device * dev)2584 static int __maybe_unused rockchip_thermal_resume(struct device *dev)
2585 {
2586 struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
2587 int i;
2588 int error;
2589
2590 error = clk_bulk_enable(thermal->num_clks, thermal->clks);
2591 if (error) {
2592 dev_err(dev, "failed to enable tsadc bulk clks: %d\n",
2593 error);
2594 return error;
2595 }
2596
2597 rockchip_thermal_reset_controller(thermal->reset);
2598
2599 thermal->chip->initialize(thermal->grf, thermal->regs,
2600 thermal->tshut_polarity);
2601
2602 for (i = 0; i < thermal->chip->chn_num; i++) {
2603 int id = thermal->sensors[i].id;
2604 int tshut_temp = thermal->sensors[i].tshut_temp;
2605
2606 thermal->chip->set_tshut_mode(thermal->grf, id, thermal->regs,
2607 thermal->tshut_mode);
2608
2609 error = thermal->chip->set_tshut_temp(&thermal->chip->table,
2610 id, thermal->regs,
2611 tshut_temp);
2612 if (error)
2613 dev_err(dev, "%s: invalid tshut=%d, error=%d\n",
2614 __func__, tshut_temp, error);
2615 }
2616
2617 thermal->chip->control(thermal->regs, true);
2618 if (thermal->chip->conversion_time)
2619 usleep_range(thermal->chip->conversion_time,
2620 thermal->chip->conversion_time + 50);
2621
2622 for (i = 0; i < thermal->chip->chn_num; i++)
2623 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
2624
2625 if (thermal->tshut_mode == TSHUT_MODE_OTP)
2626 thermal_pinctrl_select_otp(thermal);
2627
2628 return 0;
2629 }
2630
2631 static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops,
2632 rockchip_thermal_suspend, rockchip_thermal_resume);
2633
2634 static struct platform_driver rockchip_thermal_driver = {
2635 .driver = {
2636 .name = "rockchip-thermal",
2637 .pm = &rockchip_thermal_pm_ops,
2638 .of_match_table = of_rockchip_thermal_match,
2639 },
2640 .probe = rockchip_thermal_probe,
2641 .remove = rockchip_thermal_remove,
2642 .shutdown = rockchip_thermal_shutdown,
2643 };
2644
rockchip_thermal_driver_init(void)2645 static int __init rockchip_thermal_driver_init(void)
2646 {
2647 return platform_driver_register(&rockchip_thermal_driver);
2648 }
2649 rootfs_initcall(rockchip_thermal_driver_init);
2650
rockchip_thermal_driver_exit(void)2651 static void __exit rockchip_thermal_driver_exit(void)
2652 {
2653 platform_driver_unregister(&rockchip_thermal_driver);
2654 }
2655 module_exit(rockchip_thermal_driver_exit);
2656
2657 MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver");
2658 MODULE_AUTHOR("Rockchip, Inc.");
2659 MODULE_LICENSE("GPL v2");
2660 MODULE_ALIAS("platform:rockchip-thermal");
2661