1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Rockchip Generic power domain support.
4 *
5 * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
6 */
7
8 #include <linux/module.h>
9 #include <linux/io.h>
10 #include <linux/iopoll.h>
11 #include <linux/err.h>
12 #include <linux/pm_clock.h>
13 #include <linux/pm_domain.h>
14 #include <linux/of_address.h>
15 #include <linux/of_clk.h>
16 #include <linux/of_platform.h>
17 #include <linux/clk.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
20 #include <linux/mfd/syscon.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/rockchip/cpu.h>
24 #include <soc/rockchip/pm_domains.h>
25 #include <soc/rockchip/rockchip_dmc.h>
26 #include <dt-bindings/power/px30-power.h>
27 #include <dt-bindings/power/rv1126-power.h>
28 #include <dt-bindings/power/rk1808-power.h>
29 #include <dt-bindings/power/rk3036-power.h>
30 #include <dt-bindings/power/rk3066-power.h>
31 #include <dt-bindings/power/rk3128-power.h>
32 #include <dt-bindings/power/rk3188-power.h>
33 #include <dt-bindings/power/rk3228-power.h>
34 #include <dt-bindings/power/rk3288-power.h>
35 #include <dt-bindings/power/rk3328-power.h>
36 #include <dt-bindings/power/rk3366-power.h>
37 #include <dt-bindings/power/rk3368-power.h>
38 #include <dt-bindings/power/rk3399-power.h>
39 #include <dt-bindings/power/rk3528-power.h>
40 #include <dt-bindings/power/rk3562-power.h>
41 #include <dt-bindings/power/rk3568-power.h>
42 #include <dt-bindings/power/rk3588-power.h>
43
44 struct rockchip_domain_info {
45 const char *name;
46 int pwr_mask;
47 int status_mask;
48 int req_mask;
49 int idle_mask;
50 int ack_mask;
51 bool active_wakeup;
52 int pwr_w_mask;
53 int req_w_mask;
54 int mem_status_mask;
55 int repair_status_mask;
56 int clk_ungate_mask;
57 int clk_ungate_w_mask;
58 int mem_num;
59 bool keepon_startup;
60 bool always_on;
61 u32 pwr_offset;
62 u32 mem_offset;
63 u32 req_offset;
64 };
65
66 struct rockchip_pmu_info {
67 u32 pwr_offset;
68 u32 status_offset;
69 u32 req_offset;
70 u32 idle_offset;
71 u32 ack_offset;
72 u32 mem_pwr_offset;
73 u32 chain_status_offset;
74 u32 mem_status_offset;
75 u32 repair_status_offset;
76 u32 clk_ungate_offset;
77 u32 mem_sd_offset;
78
79 u32 core_pwrcnt_offset;
80 u32 gpu_pwrcnt_offset;
81
82 unsigned int core_power_transition_time;
83 unsigned int gpu_power_transition_time;
84
85 int num_domains;
86 const struct rockchip_domain_info *domain_info;
87 };
88
89 #define MAX_QOS_REGS_NUM 5
90 #define QOS_PRIORITY 0x08
91 #define QOS_MODE 0x0c
92 #define QOS_BANDWIDTH 0x10
93 #define QOS_SATURATION 0x14
94 #define QOS_EXTCONTROL 0x18
95
96 struct rockchip_pm_domain {
97 struct generic_pm_domain genpd;
98 const struct rockchip_domain_info *info;
99 struct rockchip_pmu *pmu;
100 int num_qos;
101 struct regmap **qos_regmap;
102 u32 *qos_save_regs[MAX_QOS_REGS_NUM];
103 bool *qos_is_need_init[MAX_QOS_REGS_NUM];
104 int num_clks;
105 struct clk_bulk_data *clks;
106 bool is_ignore_pwr;
107 bool is_qos_saved;
108 bool is_qos_need_init;
109 struct regulator *supply;
110 };
111
112 struct rockchip_pmu {
113 struct device *dev;
114 struct regmap *regmap;
115 const struct rockchip_pmu_info *info;
116 struct mutex mutex; /* mutex lock for pmu */
117 struct genpd_onecell_data genpd_data;
118 struct generic_pm_domain *domains[];
119 };
120
121 static struct rockchip_pmu *g_pmu;
122 static bool pm_domain_always_on;
123
124 module_param_named(always_on, pm_domain_always_on, bool, 0644);
125 MODULE_PARM_DESC(always_on,
126 "Always keep pm domains power on except for system suspend.");
127
128 #ifdef MODULE
129 static bool keepon_startup = true;
130 static void rockchip_pd_keepon_do_release(void);
131
pd_param_set_keepon_startup(const char * val,const struct kernel_param * kp)132 static int pd_param_set_keepon_startup(const char *val,
133 const struct kernel_param *kp)
134 {
135 int ret;
136
137 ret = param_set_bool(val, kp);
138 if (ret)
139 return ret;
140
141 if (!keepon_startup)
142 rockchip_pd_keepon_do_release();
143
144 return 0;
145 }
146
147 static const struct kernel_param_ops pd_keepon_startup_ops = {
148 .set = pd_param_set_keepon_startup,
149 .get = param_get_bool,
150 };
151
152 module_param_cb(keepon_startup, &pd_keepon_startup_ops, &keepon_startup, 0644);
153 MODULE_PARM_DESC(keepon_startup,
154 "Keep pm domains power on during system startup.");
155 #endif
156
rockchip_pmu_lock(struct rockchip_pm_domain * pd)157 static void rockchip_pmu_lock(struct rockchip_pm_domain *pd)
158 {
159 mutex_lock(&pd->pmu->mutex);
160 rockchip_dmcfreq_lock_nested();
161 }
162
rockchip_pmu_unlock(struct rockchip_pm_domain * pd)163 static void rockchip_pmu_unlock(struct rockchip_pm_domain *pd)
164 {
165 rockchip_dmcfreq_unlock();
166 mutex_unlock(&pd->pmu->mutex);
167 }
168
169 #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
170
171 #define DOMAIN(_name, pwr, status, req, idle, ack, wakeup, keepon) \
172 { \
173 .name = _name, \
174 .pwr_mask = (pwr), \
175 .status_mask = (status), \
176 .req_mask = (req), \
177 .idle_mask = (idle), \
178 .ack_mask = (ack), \
179 .active_wakeup = (wakeup), \
180 .keepon_startup = (keepon), \
181 }
182
183 #define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup, keepon) \
184 { \
185 .name = _name, \
186 .pwr_w_mask = (pwr) << 16, \
187 .pwr_mask = (pwr), \
188 .status_mask = (status), \
189 .req_w_mask = (req) << 16, \
190 .req_mask = (req), \
191 .idle_mask = (idle), \
192 .ack_mask = (ack), \
193 .active_wakeup = wakeup, \
194 .keepon_startup = keepon, \
195 }
196
197 #define DOMAIN_M_A(pwr, status, req, idle, ack, always, wakeup, keepon) \
198 { \
199 .pwr_w_mask = (pwr) << 16, \
200 .pwr_mask = (pwr), \
201 .status_mask = (status), \
202 .req_w_mask = (req) << 16, \
203 .req_mask = (req), \
204 .idle_mask = (idle), \
205 .ack_mask = (ack), \
206 .always_on = always, \
207 .active_wakeup = wakeup, \
208 .keepon_startup = keepon, \
209 }
210
211 #define DOMAIN_M_C_SD(_name, pwr, status, req, idle, ack, clk, mem, wakeup, keepon) \
212 { \
213 .name = _name, \
214 .pwr_w_mask = (pwr) << 16, \
215 .pwr_mask = (pwr), \
216 .status_mask = (status), \
217 .req_w_mask = (req) << 16, \
218 .req_mask = (req), \
219 .idle_mask = (idle), \
220 .ack_mask = (ack), \
221 .clk_ungate_mask = (clk), \
222 .clk_ungate_w_mask = (clk) << 16, \
223 .mem_num = (mem), \
224 .active_wakeup = wakeup, \
225 .keepon_startup = keepon, \
226 }
227
228 #define DOMAIN_M_O(_name, pwr, status, p_offset, req, idle, ack, r_offset, wakeup, keepon) \
229 { \
230 .name = _name, \
231 .pwr_w_mask = (pwr) << 16, \
232 .pwr_mask = (pwr), \
233 .status_mask = (status), \
234 .req_w_mask = (req) << 16, \
235 .req_mask = (req), \
236 .idle_mask = (idle), \
237 .ack_mask = (ack), \
238 .active_wakeup = wakeup, \
239 .keepon_startup = keepon, \
240 .pwr_offset = p_offset, \
241 .req_offset = r_offset, \
242 }
243
244 #define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup, keepon) \
245 { \
246 .name = _name, \
247 .pwr_offset = p_offset, \
248 .pwr_w_mask = (pwr) << 16, \
249 .pwr_mask = (pwr), \
250 .status_mask = (status), \
251 .mem_offset = m_offset, \
252 .mem_status_mask = (m_status), \
253 .repair_status_mask = (r_status), \
254 .req_offset = r_offset, \
255 .req_w_mask = (req) << 16, \
256 .req_mask = (req), \
257 .idle_mask = (idle), \
258 .ack_mask = (ack), \
259 .active_wakeup = wakeup, \
260 .keepon_startup = keepon, \
261 }
262
263 #define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \
264 { \
265 .name = _name, \
266 .req_mask = (req), \
267 .req_w_mask = (req) << 16, \
268 .ack_mask = (ack), \
269 .idle_mask = (idle), \
270 .active_wakeup = wakeup, \
271 }
272
273 #define DOMAIN_PX30(name, pwr, status, req, wakeup) \
274 DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup, false)
275
276 #define DOMAIN_PX30_PROTECT(name, pwr, status, req, wakeup) \
277 DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup, true)
278
279 #define DOMAIN_RV1126(name, pwr, req, idle, wakeup) \
280 DOMAIN_M(name, pwr, pwr, req, idle, idle, wakeup, false)
281
282 #define DOMAIN_RV1126_PROTECT(name, pwr, req, idle, wakeup) \
283 DOMAIN_M(name, pwr, pwr, req, idle, idle, wakeup, true)
284
285 #define DOMAIN_RV1126_O(name, pwr, req, idle, r_offset, wakeup) \
286 DOMAIN_M_O(name, pwr, pwr, 0, req, idle, idle, r_offset, wakeup, false)
287
288 #define DOMAIN_RK3288(name, pwr, status, req, wakeup) \
289 DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup, false)
290
291 #define DOMAIN_RK3288_PROTECT(name, pwr, status, req, wakeup) \
292 DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup, true)
293
294 #define DOMAIN_RK3328(name, pwr, status, req, wakeup) \
295 DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup, false)
296
297 #define DOMAIN_RK3368(name, pwr, status, req, wakeup) \
298 DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup, false)
299
300 #define DOMAIN_RK3368_PROTECT(name, pwr, status, req, wakeup) \
301 DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup, true)
302
303 #define DOMAIN_RK3399(name, pwr, status, req, wakeup) \
304 DOMAIN(name, pwr, status, req, req, req, wakeup, false)
305
306 #define DOMAIN_RK3399_PROTECT(name, pwr, status, req, wakeup) \
307 DOMAIN(name, pwr, status, req, req, req, wakeup, true)
308
309 #define DOMAIN_RK3528(pwr, req, always, wakeup) \
310 DOMAIN_M_A(pwr, pwr, req, req, req, always, wakeup, false)
311
312 #define DOMAIN_RK3562(name, pwr, req, mem, wakeup) \
313 DOMAIN_M_C_SD(name, pwr, pwr, req, req, req, req, mem, wakeup, false)
314
315 #define DOMAIN_RK3562_PROTECT(name, pwr, req, mem, wakeup) \
316 DOMAIN_M_C_SD(name, pwr, pwr, req, req, req, req, mem, wakeup, true)
317
318 #define DOMAIN_RK3568(name, pwr, req, wakeup) \
319 DOMAIN_M(name, pwr, pwr, req, req, req, wakeup, false)
320
321 #define DOMAIN_RK3568_PROTECT(name, pwr, req, wakeup) \
322 DOMAIN_M(name, pwr, pwr, req, req, req, wakeup, true)
323
324 #define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup) \
325 DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup, false)
326
327 #define DOMAIN_RK3588_P(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup) \
328 DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup, true)
329
rockchip_pmu_domain_is_idle(struct rockchip_pm_domain * pd)330 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
331 {
332 struct rockchip_pmu *pmu = pd->pmu;
333 const struct rockchip_domain_info *pd_info = pd->info;
334 unsigned int val;
335
336 regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
337 return (val & pd_info->idle_mask) == pd_info->idle_mask;
338 }
339
rockchip_pmu_read_ack(struct rockchip_pmu * pmu)340 static unsigned int rockchip_pmu_read_ack(struct rockchip_pmu *pmu)
341 {
342 unsigned int val;
343
344 regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
345 return val;
346 }
347
rockchip_pmu_ungate_clk(struct rockchip_pm_domain * pd,bool ungate)348 static int rockchip_pmu_ungate_clk(struct rockchip_pm_domain *pd, bool ungate)
349 {
350 const struct rockchip_domain_info *pd_info = pd->info;
351 struct rockchip_pmu *pmu = pd->pmu;
352 unsigned int val;
353
354 if (!pd_info->clk_ungate_mask)
355 return 0;
356 if (!pmu->info->clk_ungate_offset)
357 return 0;
358
359 val = ungate ? (pd_info->clk_ungate_mask | pd_info->clk_ungate_w_mask) :
360 pd_info->clk_ungate_w_mask;
361 regmap_write(pmu->regmap, pmu->info->clk_ungate_offset, val);
362
363 return 0;
364 }
365
rockchip_pmu_mem_shut_down(struct rockchip_pm_domain * pd,bool sd)366 static int rockchip_pmu_mem_shut_down(struct rockchip_pm_domain *pd, bool sd)
367 {
368 const struct rockchip_domain_info *pd_info = pd->info;
369 struct rockchip_pmu *pmu = pd->pmu;
370 unsigned int i;
371
372 if (!pd_info->mem_num)
373 return 0;
374 if (!pmu->info->mem_sd_offset)
375 return 0;
376
377 for (i = 0; i < pd_info->mem_num; i++)
378 regmap_write(pmu->regmap, pmu->info->mem_sd_offset,
379 (sd << i) | (1 << (i + 16)));
380
381 return 0;
382 }
383
rockchip_pmu_set_idle_request(struct rockchip_pm_domain * pd,bool idle)384 static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
385 bool idle)
386 {
387 const struct rockchip_domain_info *pd_info = pd->info;
388 struct generic_pm_domain *genpd = &pd->genpd;
389 struct rockchip_pmu *pmu = pd->pmu;
390 u32 pd_req_offset = 0;
391 unsigned int target_ack;
392 unsigned int val;
393 bool is_idle;
394 int ret = 0;
395
396 if (pd_info->req_offset)
397 pd_req_offset = pd_info->req_offset;
398
399 if (pd_info->req_mask == 0)
400 return 0;
401 else if (pd_info->req_w_mask)
402 regmap_write(pmu->regmap, pmu->info->req_offset + pd_req_offset,
403 idle ? (pd_info->req_mask | pd_info->req_w_mask) :
404 pd_info->req_w_mask);
405 else
406 regmap_update_bits(pmu->regmap, pmu->info->req_offset +
407 pd_req_offset, pd_info->req_mask,
408 idle ? -1U : 0);
409
410 dsb(sy);
411
412 /* Wait util idle_ack = 1 */
413 target_ack = idle ? pd_info->ack_mask : 0;
414 ret = readx_poll_timeout_atomic(rockchip_pmu_read_ack, pmu, val,
415 (val & pd_info->ack_mask) == target_ack,
416 0, 10000);
417 if (ret) {
418 dev_err(pmu->dev,
419 "failed to get ack on domain '%s', target_idle = %d, target_ack = %d, val=0x%x\n",
420 genpd->name, idle, target_ack, val);
421 goto error;
422 }
423
424 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_idle, pd,
425 is_idle, is_idle == idle, 0, 10000);
426 if (ret) {
427 dev_err(pmu->dev,
428 "failed to set idle on domain '%s', target_idle = %d, val=%d\n",
429 genpd->name, idle, is_idle);
430 goto error;
431 }
432
433 return ret;
434 error:
435 panic("panic_on_set_idle set ...\n");
436 return ret;
437 }
438
rockchip_pmu_idle_request(struct device * dev,bool idle)439 int rockchip_pmu_idle_request(struct device *dev, bool idle)
440 {
441 struct generic_pm_domain *genpd;
442 struct rockchip_pm_domain *pd;
443 int ret;
444
445 if (IS_ERR_OR_NULL(dev))
446 return -EINVAL;
447
448 if (IS_ERR_OR_NULL(dev->pm_domain))
449 return -EINVAL;
450
451 genpd = pd_to_genpd(dev->pm_domain);
452 pd = to_rockchip_pd(genpd);
453
454 rockchip_pmu_lock(pd);
455 ret = rockchip_pmu_set_idle_request(pd, idle);
456 rockchip_pmu_unlock(pd);
457
458 return ret;
459 }
460 EXPORT_SYMBOL(rockchip_pmu_idle_request);
461
rockchip_pmu_save_qos(struct rockchip_pm_domain * pd)462 static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
463 {
464 int i;
465
466 for (i = 0; i < pd->num_qos; i++) {
467 regmap_read(pd->qos_regmap[i],
468 QOS_PRIORITY,
469 &pd->qos_save_regs[0][i]);
470 regmap_read(pd->qos_regmap[i],
471 QOS_MODE,
472 &pd->qos_save_regs[1][i]);
473 regmap_read(pd->qos_regmap[i],
474 QOS_BANDWIDTH,
475 &pd->qos_save_regs[2][i]);
476 regmap_read(pd->qos_regmap[i],
477 QOS_SATURATION,
478 &pd->qos_save_regs[3][i]);
479 regmap_read(pd->qos_regmap[i],
480 QOS_EXTCONTROL,
481 &pd->qos_save_regs[4][i]);
482 }
483 return 0;
484 }
485
rockchip_pmu_restore_qos(struct rockchip_pm_domain * pd)486 static int rockchip_pmu_restore_qos(struct rockchip_pm_domain *pd)
487 {
488 int i;
489
490 for (i = 0; i < pd->num_qos; i++) {
491 regmap_write(pd->qos_regmap[i],
492 QOS_PRIORITY,
493 pd->qos_save_regs[0][i]);
494 regmap_write(pd->qos_regmap[i],
495 QOS_MODE,
496 pd->qos_save_regs[1][i]);
497 regmap_write(pd->qos_regmap[i],
498 QOS_BANDWIDTH,
499 pd->qos_save_regs[2][i]);
500 regmap_write(pd->qos_regmap[i],
501 QOS_SATURATION,
502 pd->qos_save_regs[3][i]);
503 regmap_write(pd->qos_regmap[i],
504 QOS_EXTCONTROL,
505 pd->qos_save_regs[4][i]);
506 }
507
508 return 0;
509 }
510
rockchip_pmu_init_qos(struct rockchip_pm_domain * pd)511 static void rockchip_pmu_init_qos(struct rockchip_pm_domain *pd)
512 {
513 int i;
514
515 if (!pd->is_qos_need_init)
516 return;
517
518 for (i = 0; i < pd->num_qos; i++) {
519 if (pd->qos_is_need_init[0][i])
520 regmap_write(pd->qos_regmap[i],
521 QOS_PRIORITY,
522 pd->qos_save_regs[0][i]);
523
524 if (pd->qos_is_need_init[1][i])
525 regmap_write(pd->qos_regmap[i],
526 QOS_MODE,
527 pd->qos_save_regs[1][i]);
528
529 if (pd->qos_is_need_init[2][i])
530 regmap_write(pd->qos_regmap[i],
531 QOS_BANDWIDTH,
532 pd->qos_save_regs[2][i]);
533
534 if (pd->qos_is_need_init[3][i])
535 regmap_write(pd->qos_regmap[i],
536 QOS_SATURATION,
537 pd->qos_save_regs[3][i]);
538
539 if (pd->qos_is_need_init[4][i])
540 regmap_write(pd->qos_regmap[i],
541 QOS_EXTCONTROL,
542 pd->qos_save_regs[4][i]);
543 }
544
545 kfree(pd->qos_is_need_init[0]);
546 pd->qos_is_need_init[0] = NULL;
547 pd->is_qos_need_init = false;
548 }
549
rockchip_save_qos(struct device * dev)550 int rockchip_save_qos(struct device *dev)
551 {
552 struct generic_pm_domain *genpd;
553 struct rockchip_pm_domain *pd;
554 int ret;
555
556 if (IS_ERR_OR_NULL(dev))
557 return -EINVAL;
558
559 if (IS_ERR_OR_NULL(dev->pm_domain))
560 return -EINVAL;
561
562 genpd = pd_to_genpd(dev->pm_domain);
563 pd = to_rockchip_pd(genpd);
564
565 rockchip_pmu_lock(pd);
566 ret = rockchip_pmu_save_qos(pd);
567 rockchip_pmu_unlock(pd);
568
569 return ret;
570 }
571 EXPORT_SYMBOL(rockchip_save_qos);
572
rockchip_restore_qos(struct device * dev)573 int rockchip_restore_qos(struct device *dev)
574 {
575 struct generic_pm_domain *genpd;
576 struct rockchip_pm_domain *pd;
577 int ret;
578
579 if (IS_ERR_OR_NULL(dev))
580 return -EINVAL;
581
582 if (IS_ERR_OR_NULL(dev->pm_domain))
583 return -EINVAL;
584
585 genpd = pd_to_genpd(dev->pm_domain);
586 pd = to_rockchip_pd(genpd);
587
588 rockchip_pmu_lock(pd);
589 ret = rockchip_pmu_restore_qos(pd);
590 rockchip_pmu_unlock(pd);
591
592 return ret;
593 }
594 EXPORT_SYMBOL(rockchip_restore_qos);
595
rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain * pd)596 static bool rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain *pd)
597 {
598 struct rockchip_pmu *pmu = pd->pmu;
599 unsigned int val;
600
601 regmap_read(pmu->regmap,
602 pmu->info->mem_status_offset + pd->info->mem_offset, &val);
603
604 /* 1'b0: power on, 1'b1: power off */
605 return !(val & pd->info->mem_status_mask);
606 }
607
rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain * pd)608 static bool rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain *pd)
609 {
610 struct rockchip_pmu *pmu = pd->pmu;
611 unsigned int val;
612
613 regmap_read(pmu->regmap,
614 pmu->info->chain_status_offset + pd->info->mem_offset, &val);
615
616 /* 1'b1: power on, 1'b0: power off */
617 return val & pd->info->mem_status_mask;
618 }
619
rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain * pd)620 static int rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain *pd)
621 {
622 struct rockchip_pmu *pmu = pd->pmu;
623 struct generic_pm_domain *genpd = &pd->genpd;
624 bool is_on;
625 int ret = 0;
626
627 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_chain_on, pd, is_on,
628 is_on == true, 0, 10000);
629 if (ret) {
630 dev_err(pmu->dev,
631 "failed to get chain status '%s', target_on=1, val=%d\n",
632 genpd->name, is_on);
633 goto error;
634 }
635
636 udelay(60);
637
638 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
639 (pd->info->pwr_mask | pd->info->pwr_w_mask));
640 dsb(sy);
641
642 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
643 is_on == false, 0, 10000);
644 if (ret) {
645 dev_err(pmu->dev,
646 "failed to get mem status '%s', target_on=0, val=%d\n",
647 genpd->name, is_on);
648 goto error;
649 }
650
651 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
652 pd->info->pwr_w_mask);
653 dsb(sy);
654
655 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
656 is_on == true, 0, 10000);
657 if (ret) {
658 dev_err(pmu->dev,
659 "failed to get mem status '%s', target_on=1, val=%d\n",
660 genpd->name, is_on);
661 }
662
663 error:
664
665 return ret;
666 }
667
rockchip_pmu_domain_is_on(struct rockchip_pm_domain * pd)668 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
669 {
670 struct rockchip_pmu *pmu = pd->pmu;
671 unsigned int val;
672
673 if (pd->info->repair_status_mask) {
674 regmap_read(pmu->regmap, pmu->info->repair_status_offset, &val);
675 /* 1'b1: power on, 1'b0: power off */
676 return val & pd->info->repair_status_mask;
677 }
678
679 /* check idle status for idle-only domains */
680 if (pd->info->status_mask == 0)
681 return !rockchip_pmu_domain_is_idle(pd);
682
683 regmap_read(pmu->regmap, pmu->info->status_offset, &val);
684
685 /* 1'b0: power on, 1'b1: power off */
686 return !(val & pd->info->status_mask);
687 }
688
rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain * pd,bool on)689 static int rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
690 bool on)
691 {
692 struct rockchip_pmu *pmu = pd->pmu;
693 struct generic_pm_domain *genpd = &pd->genpd;
694 u32 pd_pwr_offset = 0;
695 bool is_on, is_mem_on = false;
696 int ret = 0;
697
698 if (pd->info->pwr_mask == 0)
699 return 0;
700
701 if (on && pd->info->mem_status_mask)
702 is_mem_on = rockchip_pmu_domain_is_mem_on(pd);
703
704 if (pd->info->pwr_offset)
705 pd_pwr_offset = pd->info->pwr_offset;
706
707 if (pd->info->pwr_w_mask)
708 regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
709 on ? pd->info->pwr_w_mask :
710 (pd->info->pwr_mask | pd->info->pwr_w_mask));
711 else
712 regmap_update_bits(pmu->regmap, pmu->info->pwr_offset +
713 pd_pwr_offset, pd->info->pwr_mask,
714 on ? 0 : -1U);
715
716 dsb(sy);
717
718 if (is_mem_on) {
719 ret = rockchip_pmu_domain_mem_reset(pd);
720 if (ret)
721 goto error;
722 }
723
724 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
725 is_on == on, 0, 10000);
726 if (ret) {
727 dev_err(pmu->dev,
728 "failed to set domain '%s', target_on= %d, val=%d\n",
729 genpd->name, on, is_on);
730 goto error;
731 }
732 return ret;
733
734 error:
735 panic("panic_on_set_domain set ...\n");
736 return ret;
737 }
738
rockchip_pd_power(struct rockchip_pm_domain * pd,bool power_on)739 static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
740 {
741 struct rockchip_pmu *pmu = pd->pmu;
742 int ret = 0;
743 struct generic_pm_domain *genpd = &pd->genpd;
744
745 if (pm_domain_always_on && !power_on)
746 return 0;
747
748 if (!power_on && soc_is_px30s()) {
749 if (genpd->name && !strcmp(genpd->name, "gpu"))
750 return 0;
751 }
752
753 rockchip_pmu_lock(pd);
754
755 if (rockchip_pmu_domain_is_on(pd) != power_on) {
756 if (IS_ERR_OR_NULL(pd->supply) &&
757 PTR_ERR(pd->supply) != -ENODEV)
758 pd->supply = devm_regulator_get_optional(pd->pmu->dev,
759 genpd->name);
760
761 if (power_on && !IS_ERR(pd->supply)) {
762 ret = regulator_enable(pd->supply);
763 if (ret < 0) {
764 dev_err(pd->pmu->dev, "failed to set vdd supply enable '%s',\n",
765 genpd->name);
766 rockchip_pmu_unlock(pd);
767 return ret;
768 }
769 }
770
771 ret = clk_bulk_enable(pd->num_clks, pd->clks);
772 if (ret < 0) {
773 dev_err(pmu->dev, "failed to enable clocks\n");
774 rockchip_pmu_unlock(pd);
775 return ret;
776 }
777 rockchip_pmu_ungate_clk(pd, true);
778
779 if (!power_on) {
780 rockchip_pmu_save_qos(pd);
781 pd->is_qos_saved = true;
782
783 /* if powering down, idle request to NIU first */
784 ret = rockchip_pmu_set_idle_request(pd, true);
785 if (ret) {
786 dev_err(pd->pmu->dev, "failed to set idle request '%s',\n",
787 genpd->name);
788 goto out;
789 }
790 rockchip_pmu_mem_shut_down(pd, true);
791 }
792
793 ret = rockchip_do_pmu_set_power_domain(pd, power_on);
794 if (ret) {
795 dev_err(pd->pmu->dev, "failed to set power '%s' = %d,\n",
796 genpd->name, power_on);
797 goto out;
798 }
799
800 if (power_on) {
801 rockchip_pmu_mem_shut_down(pd, false);
802 /* if powering up, leave idle mode */
803 ret = rockchip_pmu_set_idle_request(pd, false);
804 if (ret) {
805 dev_err(pd->pmu->dev, "failed to set deidle request '%s',\n",
806 genpd->name);
807 goto out;
808 }
809
810 if (pd->is_qos_saved)
811 rockchip_pmu_restore_qos(pd);
812 if (pd->is_qos_need_init)
813 rockchip_pmu_init_qos(pd);
814 }
815
816 out:
817 rockchip_pmu_ungate_clk(pd, false);
818 clk_bulk_disable(pd->num_clks, pd->clks);
819
820 if (!power_on && !IS_ERR(pd->supply))
821 ret = regulator_disable(pd->supply);
822 }
823
824 rockchip_pmu_unlock(pd);
825 return ret;
826 }
827
rockchip_pd_power_on(struct generic_pm_domain * domain)828 static int rockchip_pd_power_on(struct generic_pm_domain *domain)
829 {
830 struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
831
832 if (pd->is_ignore_pwr)
833 return 0;
834
835 return rockchip_pd_power(pd, true);
836 }
837
rockchip_pd_power_off(struct generic_pm_domain * domain)838 static int rockchip_pd_power_off(struct generic_pm_domain *domain)
839 {
840 struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
841
842 if (pd->is_ignore_pwr)
843 return 0;
844
845 return rockchip_pd_power(pd, false);
846 }
847
rockchip_pmu_pd_on(struct device * dev)848 int rockchip_pmu_pd_on(struct device *dev)
849 {
850 struct generic_pm_domain *genpd;
851 struct rockchip_pm_domain *pd;
852
853 if (IS_ERR_OR_NULL(dev))
854 return -EINVAL;
855
856 if (IS_ERR_OR_NULL(dev->pm_domain))
857 return -EINVAL;
858
859 genpd = pd_to_genpd(dev->pm_domain);
860 pd = to_rockchip_pd(genpd);
861
862 return rockchip_pd_power(pd, true);
863 }
864 EXPORT_SYMBOL(rockchip_pmu_pd_on);
865
rockchip_pmu_pd_off(struct device * dev)866 int rockchip_pmu_pd_off(struct device *dev)
867 {
868 struct generic_pm_domain *genpd;
869 struct rockchip_pm_domain *pd;
870
871 if (IS_ERR_OR_NULL(dev))
872 return -EINVAL;
873
874 if (IS_ERR_OR_NULL(dev->pm_domain))
875 return -EINVAL;
876
877 genpd = pd_to_genpd(dev->pm_domain);
878 pd = to_rockchip_pd(genpd);
879
880 return rockchip_pd_power(pd, false);
881 }
882 EXPORT_SYMBOL(rockchip_pmu_pd_off);
883
rockchip_pmu_pd_is_on(struct device * dev)884 bool rockchip_pmu_pd_is_on(struct device *dev)
885 {
886 struct generic_pm_domain *genpd;
887 struct rockchip_pm_domain *pd;
888 bool is_on;
889
890 if (IS_ERR_OR_NULL(dev))
891 return false;
892
893 if (IS_ERR_OR_NULL(dev->pm_domain))
894 return false;
895
896 genpd = pd_to_genpd(dev->pm_domain);
897 pd = to_rockchip_pd(genpd);
898
899 rockchip_pmu_lock(pd);
900 is_on = rockchip_pmu_domain_is_on(pd);
901 rockchip_pmu_unlock(pd);
902
903 return is_on;
904 }
905 EXPORT_SYMBOL(rockchip_pmu_pd_is_on);
906
rockchip_pd_attach_dev(struct generic_pm_domain * genpd,struct device * dev)907 static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd,
908 struct device *dev)
909 {
910 struct clk *clk;
911 int i;
912 int error;
913
914 dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name);
915
916 error = pm_clk_create(dev);
917 if (error) {
918 dev_err(dev, "pm_clk_create failed %d\n", error);
919 return error;
920 }
921
922 i = 0;
923 while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) {
924 dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk);
925 error = pm_clk_add_clk(dev, clk);
926 if (error) {
927 dev_err(dev, "pm_clk_add_clk failed %d\n", error);
928 clk_put(clk);
929 pm_clk_destroy(dev);
930 return error;
931 }
932 }
933
934 return 0;
935 }
936
rockchip_pd_detach_dev(struct generic_pm_domain * genpd,struct device * dev)937 static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd,
938 struct device *dev)
939 {
940 dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name);
941
942 pm_clk_destroy(dev);
943 }
944
rockchip_pd_qos_init(struct rockchip_pm_domain * pd)945 static void rockchip_pd_qos_init(struct rockchip_pm_domain *pd)
946 {
947 int is_pd_on, ret = 0;
948
949 if (!pd->is_qos_need_init) {
950 kfree(pd->qos_is_need_init[0]);
951 pd->qos_is_need_init[0] = NULL;
952 return;
953 }
954
955 is_pd_on = rockchip_pmu_domain_is_on(pd);
956 if (is_pd_on) {
957 ret = clk_bulk_enable(pd->num_clks, pd->clks);
958 if (ret < 0) {
959 dev_err(pd->pmu->dev, "failed to enable clocks\n");
960 return;
961 }
962 rockchip_pmu_init_qos(pd);
963 clk_bulk_disable(pd->num_clks, pd->clks);
964 }
965 }
966
rockchip_pd_add_alwasy_on_flag(struct rockchip_pm_domain * pd)967 static int rockchip_pd_add_alwasy_on_flag(struct rockchip_pm_domain *pd)
968 {
969 int error;
970
971 if (pd->genpd.flags & GENPD_FLAG_ALWAYS_ON)
972 return 0;
973 pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON;
974 if (!rockchip_pmu_domain_is_on(pd)) {
975 error = rockchip_pd_power(pd, true);
976 if (error) {
977 dev_err(pd->pmu->dev,
978 "failed to power on domain '%s': %d\n",
979 pd->genpd.name, error);
980 return error;
981 }
982 }
983
984 return 0;
985 }
986
rockchip_pm_add_one_domain(struct rockchip_pmu * pmu,struct device_node * node)987 static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
988 struct device_node *node)
989 {
990 const struct rockchip_domain_info *pd_info;
991 struct rockchip_pm_domain *pd;
992 struct device_node *qos_node;
993 int num_qos = 0, num_qos_reg = 0;
994 int i, j;
995 u32 id, val;
996 int error;
997
998 error = of_property_read_u32(node, "reg", &id);
999 if (error) {
1000 dev_err(pmu->dev,
1001 "%pOFn: failed to retrieve domain id (reg): %d\n",
1002 node, error);
1003 return -EINVAL;
1004 }
1005
1006 if (id >= pmu->info->num_domains) {
1007 dev_err(pmu->dev, "%pOFn: invalid domain id %d\n",
1008 node, id);
1009 return -EINVAL;
1010 }
1011 if (pmu->genpd_data.domains[id])
1012 return 0;
1013
1014 pd_info = &pmu->info->domain_info[id];
1015 if (!pd_info) {
1016 dev_err(pmu->dev, "%pOFn: undefined domain id %d\n",
1017 node, id);
1018 return -EINVAL;
1019 }
1020
1021 pd = devm_kzalloc(pmu->dev, sizeof(*pd), GFP_KERNEL);
1022 if (!pd)
1023 return -ENOMEM;
1024
1025 pd->info = pd_info;
1026 pd->pmu = pmu;
1027 if (!pd_info->pwr_mask)
1028 pd->is_ignore_pwr = true;
1029
1030 pd->num_clks = of_clk_get_parent_count(node);
1031 if (pd->num_clks > 0) {
1032 pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
1033 sizeof(*pd->clks), GFP_KERNEL);
1034 if (!pd->clks)
1035 return -ENOMEM;
1036 } else {
1037 dev_dbg(pmu->dev, "%pOFn: doesn't have clocks: %d\n",
1038 node, pd->num_clks);
1039 pd->num_clks = 0;
1040 }
1041
1042 for (i = 0; i < pd->num_clks; i++) {
1043 pd->clks[i].clk = of_clk_get(node, i);
1044 if (IS_ERR(pd->clks[i].clk)) {
1045 error = PTR_ERR(pd->clks[i].clk);
1046 dev_err(pmu->dev,
1047 "%pOFn: failed to get clk at index %d: %d\n",
1048 node, i, error);
1049 return error;
1050 }
1051 }
1052
1053 error = clk_bulk_prepare(pd->num_clks, pd->clks);
1054 if (error)
1055 goto err_put_clocks;
1056
1057 num_qos = of_count_phandle_with_args(node, "pm_qos", NULL);
1058
1059 for (j = 0; j < num_qos; j++) {
1060 qos_node = of_parse_phandle(node, "pm_qos", j);
1061 if (qos_node && of_device_is_available(qos_node))
1062 pd->num_qos++;
1063 of_node_put(qos_node);
1064 }
1065
1066 if (pd->num_qos > 0) {
1067 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos,
1068 sizeof(*pd->qos_regmap),
1069 GFP_KERNEL);
1070 if (!pd->qos_regmap) {
1071 error = -ENOMEM;
1072 goto err_unprepare_clocks;
1073 }
1074
1075 pd->qos_save_regs[0] = (u32 *)devm_kmalloc(pmu->dev,
1076 sizeof(u32) *
1077 MAX_QOS_REGS_NUM *
1078 pd->num_qos,
1079 GFP_KERNEL);
1080 if (!pd->qos_save_regs[0]) {
1081 error = -ENOMEM;
1082 goto err_unprepare_clocks;
1083 }
1084 pd->qos_is_need_init[0] = kzalloc(sizeof(bool) *
1085 MAX_QOS_REGS_NUM *
1086 pd->num_qos,
1087 GFP_KERNEL);
1088 if (!pd->qos_is_need_init[0]) {
1089 error = -ENOMEM;
1090 goto err_unprepare_clocks;
1091 }
1092 for (i = 1; i < MAX_QOS_REGS_NUM; i++) {
1093 pd->qos_save_regs[i] = pd->qos_save_regs[i - 1] +
1094 num_qos;
1095 pd->qos_is_need_init[i] = pd->qos_is_need_init[i - 1] +
1096 num_qos;
1097 }
1098
1099 for (j = 0; j < num_qos; j++) {
1100 qos_node = of_parse_phandle(node, "pm_qos", j);
1101 if (!qos_node) {
1102 error = -ENODEV;
1103 goto err_unprepare_clocks;
1104 }
1105 if (of_device_is_available(qos_node)) {
1106 pd->qos_regmap[num_qos_reg] =
1107 syscon_node_to_regmap(qos_node);
1108 if (IS_ERR(pd->qos_regmap[num_qos_reg])) {
1109 error = -ENODEV;
1110 of_node_put(qos_node);
1111 goto err_unprepare_clocks;
1112 }
1113 if (!of_property_read_u32(qos_node,
1114 "priority-init",
1115 &val)) {
1116 pd->qos_save_regs[0][j] = val;
1117 pd->qos_is_need_init[0][j] = true;
1118 pd->is_qos_need_init = true;
1119 }
1120
1121 if (!of_property_read_u32(qos_node,
1122 "mode-init",
1123 &val)) {
1124 pd->qos_save_regs[1][j] = val;
1125 pd->qos_is_need_init[1][j] = true;
1126 pd->is_qos_need_init = true;
1127 }
1128
1129 if (!of_property_read_u32(qos_node,
1130 "bandwidth-init",
1131 &val)) {
1132 pd->qos_save_regs[2][j] = val;
1133 pd->qos_is_need_init[2][j] = true;
1134 pd->is_qos_need_init = true;
1135 }
1136
1137 if (!of_property_read_u32(qos_node,
1138 "saturation-init",
1139 &val)) {
1140 pd->qos_save_regs[3][j] = val;
1141 pd->qos_is_need_init[3][j] = true;
1142 pd->is_qos_need_init = true;
1143 }
1144
1145 if (!of_property_read_u32(qos_node,
1146 "extcontrol-init",
1147 &val)) {
1148 pd->qos_save_regs[4][j] = val;
1149 pd->qos_is_need_init[4][j] = true;
1150 pd->is_qos_need_init = true;
1151 }
1152
1153 num_qos_reg++;
1154 }
1155 of_node_put(qos_node);
1156 if (num_qos_reg > pd->num_qos) {
1157 error = -EINVAL;
1158 goto err_unprepare_clocks;
1159 }
1160 }
1161 }
1162
1163 if (pd->info->name)
1164 pd->genpd.name = pd->info->name;
1165 else
1166 pd->genpd.name = kbasename(node->full_name);
1167 pd->genpd.power_off = rockchip_pd_power_off;
1168 pd->genpd.power_on = rockchip_pd_power_on;
1169 pd->genpd.attach_dev = rockchip_pd_attach_dev;
1170 pd->genpd.detach_dev = rockchip_pd_detach_dev;
1171 if (pd_info->active_wakeup)
1172 pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
1173 if (pd_info->always_on || pd_info->keepon_startup) {
1174 error = rockchip_pd_add_alwasy_on_flag(pd);
1175 if (error)
1176 goto err_unprepare_clocks;
1177 }
1178 rockchip_pd_qos_init(pd);
1179
1180 pm_genpd_init(&pd->genpd, NULL, !rockchip_pmu_domain_is_on(pd));
1181
1182 pmu->genpd_data.domains[id] = &pd->genpd;
1183 return 0;
1184
1185 err_unprepare_clocks:
1186 kfree(pd->qos_is_need_init[0]);
1187 pd->qos_is_need_init[0] = NULL;
1188 clk_bulk_unprepare(pd->num_clks, pd->clks);
1189 err_put_clocks:
1190 clk_bulk_put(pd->num_clks, pd->clks);
1191 return error;
1192 }
1193
rockchip_pm_remove_one_domain(struct rockchip_pm_domain * pd)1194 static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
1195 {
1196 int ret;
1197
1198 /*
1199 * We're in the error cleanup already, so we only complain,
1200 * but won't emit another error on top of the original one.
1201 */
1202 ret = pm_genpd_remove(&pd->genpd);
1203 if (ret < 0)
1204 dev_err(pd->pmu->dev, "failed to remove domain '%s' : %d - state may be inconsistent\n",
1205 pd->genpd.name, ret);
1206
1207 clk_bulk_unprepare(pd->num_clks, pd->clks);
1208 clk_bulk_put(pd->num_clks, pd->clks);
1209
1210 /* protect the zeroing of pm->num_clks */
1211 rockchip_pmu_lock(pd);
1212 pd->num_clks = 0;
1213 rockchip_pmu_unlock(pd);
1214
1215 /* devm will free our memory */
1216 }
1217
rockchip_pm_domain_cleanup(struct rockchip_pmu * pmu)1218 static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu)
1219 {
1220 struct generic_pm_domain *genpd;
1221 struct rockchip_pm_domain *pd;
1222 int i;
1223
1224 for (i = 0; i < pmu->genpd_data.num_domains; i++) {
1225 genpd = pmu->genpd_data.domains[i];
1226 if (genpd) {
1227 pd = to_rockchip_pd(genpd);
1228 rockchip_pm_remove_one_domain(pd);
1229 }
1230 }
1231
1232 /* devm will free our memory */
1233 }
1234
rockchip_configure_pd_cnt(struct rockchip_pmu * pmu,u32 domain_reg_offset,unsigned int count)1235 static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu,
1236 u32 domain_reg_offset,
1237 unsigned int count)
1238 {
1239 /* First configure domain power down transition count ... */
1240 regmap_write(pmu->regmap, domain_reg_offset, count);
1241 /* ... and then power up count. */
1242 regmap_write(pmu->regmap, domain_reg_offset + 4, count);
1243 }
1244
rockchip_pm_add_subdomain(struct rockchip_pmu * pmu,struct device_node * parent)1245 static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
1246 struct device_node *parent)
1247 {
1248 struct device_node *np;
1249 struct generic_pm_domain *child_domain, *parent_domain;
1250 struct rockchip_pm_domain *child_pd, *parent_pd;
1251 int error;
1252
1253 for_each_child_of_node(parent, np) {
1254 u32 idx;
1255
1256 error = of_property_read_u32(parent, "reg", &idx);
1257 if (error) {
1258 dev_err(pmu->dev,
1259 "%pOFn: failed to retrieve domain id (reg): %d\n",
1260 parent, error);
1261 goto err_out;
1262 }
1263 parent_domain = pmu->genpd_data.domains[idx];
1264
1265 error = rockchip_pm_add_one_domain(pmu, np);
1266 if (error) {
1267 dev_err(pmu->dev, "failed to handle node %pOFn: %d\n",
1268 np, error);
1269 goto err_out;
1270 }
1271
1272 error = of_property_read_u32(np, "reg", &idx);
1273 if (error) {
1274 dev_err(pmu->dev,
1275 "%pOFn: failed to retrieve domain id (reg): %d\n",
1276 np, error);
1277 goto err_out;
1278 }
1279 child_domain = pmu->genpd_data.domains[idx];
1280
1281 error = pm_genpd_add_subdomain(parent_domain, child_domain);
1282 if (error) {
1283 dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n",
1284 parent_domain->name, child_domain->name, error);
1285 goto err_out;
1286 } else {
1287 dev_dbg(pmu->dev, "%s add subdomain: %s\n",
1288 parent_domain->name, child_domain->name);
1289 }
1290
1291 /*
1292 * If child_pd doesn't do idle request or power on/off,
1293 * parent_pd may fail to do power on/off, so if parent_pd
1294 * need to power on/off, child_pd can't ignore to do idle
1295 * request and power on/off.
1296 */
1297 child_pd = to_rockchip_pd(child_domain);
1298 parent_pd = to_rockchip_pd(parent_domain);
1299 if (!parent_pd->is_ignore_pwr)
1300 child_pd->is_ignore_pwr = false;
1301
1302 rockchip_pm_add_subdomain(pmu, np);
1303 }
1304
1305 return 0;
1306
1307 err_out:
1308 of_node_put(np);
1309 return error;
1310 }
1311
rockchip_pd_keepon_do_release(void)1312 static void rockchip_pd_keepon_do_release(void)
1313 {
1314 struct generic_pm_domain *genpd;
1315 struct rockchip_pm_domain *pd;
1316 int i;
1317
1318 if (!g_pmu)
1319 return;
1320
1321 for (i = 0; i < g_pmu->genpd_data.num_domains; i++) {
1322 genpd = g_pmu->genpd_data.domains[i];
1323 if (genpd) {
1324 pd = to_rockchip_pd(genpd);
1325 if (pd->info->always_on)
1326 continue;
1327 if (!pd->info->keepon_startup)
1328 continue;
1329 if (!(genpd->flags & GENPD_FLAG_ALWAYS_ON))
1330 continue;
1331 genpd->flags &= (~GENPD_FLAG_ALWAYS_ON);
1332 queue_work(pm_wq, &genpd->power_off_work);
1333 }
1334 }
1335 }
1336
1337 #ifndef MODULE
rockchip_pd_keepon_release(void)1338 static int __init rockchip_pd_keepon_release(void)
1339 {
1340 rockchip_pd_keepon_do_release();
1341
1342 return 0;
1343 }
1344 late_initcall_sync(rockchip_pd_keepon_release);
1345 #endif
1346
1347 static void __iomem *pd_base;
1348
dump_offset(const char * name,u32 offset)1349 static void dump_offset(const char *name, u32 offset)
1350 {
1351 if (!offset)
1352 return;
1353
1354 pr_warn("%-9s 0x%04x: ", name, offset);
1355 print_hex_dump(KERN_CONT, "", DUMP_PREFIX_NONE, 16, 4, pd_base + offset, 16, false);
1356 }
1357
rockchip_dump_pmu(void)1358 void rockchip_dump_pmu(void)
1359 {
1360 if (!pd_base)
1361 return;
1362
1363 pr_warn("PMU:\n");
1364 dump_offset("pwr", g_pmu->info->pwr_offset);
1365 dump_offset("status", g_pmu->info->status_offset);
1366 dump_offset("req", g_pmu->info->req_offset);
1367 dump_offset("idle", g_pmu->info->idle_offset);
1368 dump_offset("ack", g_pmu->info->ack_offset);
1369 dump_offset("mem_pwr", g_pmu->info->mem_pwr_offset);
1370 dump_offset("chain_st", g_pmu->info->chain_status_offset);
1371 dump_offset("mem_st", g_pmu->info->mem_status_offset);
1372 dump_offset("repair_st", g_pmu->info->repair_status_offset);
1373 dump_offset("clkungate", g_pmu->info->clk_ungate_offset);
1374 dump_offset("mem_sd", g_pmu->info->mem_sd_offset);
1375 }
1376 EXPORT_SYMBOL_GPL(rockchip_dump_pmu);
1377
rockchip_pmu_panic(struct notifier_block * this,unsigned long ev,void * ptr)1378 static int rockchip_pmu_panic(struct notifier_block *this,
1379 unsigned long ev, void *ptr)
1380 {
1381 rockchip_dump_pmu();
1382 return NOTIFY_DONE;
1383 }
1384
1385 static struct notifier_block pmu_panic_block = {
1386 .notifier_call = rockchip_pmu_panic,
1387 };
1388
rockchip_pm_domain_probe(struct platform_device * pdev)1389 static int rockchip_pm_domain_probe(struct platform_device *pdev)
1390 {
1391 struct device *dev = &pdev->dev;
1392 struct device_node *np = dev->of_node;
1393 struct device_node *node;
1394 struct device *parent;
1395 struct rockchip_pmu *pmu;
1396 const struct of_device_id *match;
1397 const struct rockchip_pmu_info *pmu_info;
1398 int error;
1399 void __iomem *reg_base;
1400
1401 if (!np) {
1402 dev_err(dev, "device tree node not found\n");
1403 return -ENODEV;
1404 }
1405
1406 match = of_match_device(dev->driver->of_match_table, dev);
1407 if (!match || !match->data) {
1408 dev_err(dev, "missing pmu data\n");
1409 return -EINVAL;
1410 }
1411
1412 pmu_info = match->data;
1413
1414 pmu = devm_kzalloc(dev,
1415 struct_size(pmu, domains, pmu_info->num_domains),
1416 GFP_KERNEL);
1417 if (!pmu)
1418 return -ENOMEM;
1419
1420 pmu->dev = &pdev->dev;
1421 mutex_init(&pmu->mutex);
1422
1423 pmu->info = pmu_info;
1424
1425 pmu->genpd_data.domains = pmu->domains;
1426 pmu->genpd_data.num_domains = pmu_info->num_domains;
1427
1428 parent = dev->parent;
1429 if (!parent) {
1430 dev_err(dev, "no parent for syscon devices\n");
1431 return -ENODEV;
1432 }
1433
1434 pmu->regmap = syscon_node_to_regmap(parent->of_node);
1435 if (IS_ERR(pmu->regmap)) {
1436 dev_err(dev, "no regmap available\n");
1437 return PTR_ERR(pmu->regmap);
1438 }
1439
1440 reg_base = of_iomap(parent->of_node, 0);
1441 if (!reg_base) {
1442 dev_err(dev, "%s: could not map pmu region\n", __func__);
1443 return -ENOMEM;
1444 }
1445
1446 pd_base = reg_base;
1447
1448 /*
1449 * Configure power up and down transition delays for CORE
1450 * and GPU domains.
1451 */
1452 if (pmu_info->core_power_transition_time)
1453 rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
1454 pmu_info->core_power_transition_time);
1455 if (pmu_info->gpu_pwrcnt_offset)
1456 rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
1457 pmu_info->gpu_power_transition_time);
1458
1459 error = -ENODEV;
1460
1461 for_each_available_child_of_node(np, node) {
1462 error = rockchip_pm_add_one_domain(pmu, node);
1463 if (error) {
1464 dev_err(dev, "failed to handle node %pOFn: %d\n",
1465 node, error);
1466 of_node_put(node);
1467 goto err_out;
1468 }
1469
1470 error = rockchip_pm_add_subdomain(pmu, node);
1471 if (error < 0) {
1472 dev_err(dev, "failed to handle subdomain node %pOFn: %d\n",
1473 node, error);
1474 of_node_put(node);
1475 goto err_out;
1476 }
1477 }
1478
1479 if (error) {
1480 dev_dbg(dev, "no power domains defined\n");
1481 goto err_out;
1482 }
1483
1484 error = of_genpd_add_provider_onecell(np, &pmu->genpd_data);
1485 if (error) {
1486 dev_err(dev, "failed to add provider: %d\n", error);
1487 goto err_out;
1488 }
1489
1490 atomic_notifier_chain_register(&panic_notifier_list,
1491 &pmu_panic_block);
1492
1493 g_pmu = pmu;
1494 return 0;
1495
1496 err_out:
1497 rockchip_pm_domain_cleanup(pmu);
1498 return error;
1499 }
1500
1501 static const struct rockchip_domain_info px30_pm_domains[] = {
1502 [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), true),
1503 [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false),
1504 [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false),
1505 [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false),
1506 [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false),
1507 [PX30_PD_VO] = DOMAIN_PX30_PROTECT("vo", BIT(13), BIT(13), BIT(7), false),
1508 [PX30_PD_VI] = DOMAIN_PX30_PROTECT("vi", BIT(14), BIT(14), BIT(8), false),
1509 [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false),
1510 };
1511
1512 static const struct rockchip_domain_info rv1126_pm_domains[] = {
1513 [RV1126_PD_CRYPTO] = DOMAIN_RV1126_O("crypto", BIT(10), BIT(4), BIT(20), 0x4, false),
1514 [RV1126_PD_VEPU] = DOMAIN_RV1126("vepu", BIT(2), BIT(9), BIT(9), false),
1515 [RV1126_PD_VI] = DOMAIN_RV1126("vi", BIT(4), BIT(6), BIT(6), false),
1516 [RV1126_PD_VO] = DOMAIN_RV1126_PROTECT("vo", BIT(5), BIT(7), BIT(7), false),
1517 [RV1126_PD_ISPP] = DOMAIN_RV1126("ispp", BIT(1), BIT(8), BIT(8), false),
1518 [RV1126_PD_VDPU] = DOMAIN_RV1126("vdpu", BIT(3), BIT(10), BIT(10), false),
1519 [RV1126_PD_NVM] = DOMAIN_RV1126("nvm", BIT(7), BIT(11), BIT(11), false),
1520 [RV1126_PD_SDIO] = DOMAIN_RV1126("sdio", BIT(8), BIT(13), BIT(13), false),
1521 [RV1126_PD_USB] = DOMAIN_RV1126("usb", BIT(9), BIT(15), BIT(15), true),
1522 [RV1126_PD_NPU] = DOMAIN_RV1126_O("npu", BIT(0), BIT(2), BIT(18), 0x4, false),
1523 };
1524
1525 static const struct rockchip_domain_info rk1808_pm_domains[] = {
1526 [RK1808_VD_NPU] = DOMAIN_PX30("npu", BIT(15), BIT(15), BIT(2), false),
1527 [RK1808_PD_PCIE] = DOMAIN_PX30("pcie", BIT(9), BIT(9), BIT(4), true),
1528 [RK1808_PD_VPU] = DOMAIN_PX30("vpu", BIT(13), BIT(13), BIT(7), false),
1529 [RK1808_PD_VIO] = DOMAIN_PX30_PROTECT("vio", BIT(14), BIT(14), BIT(8), false),
1530 };
1531
1532 static const struct rockchip_domain_info rk3036_pm_domains[] = {
1533 [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true),
1534 [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false),
1535 [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false),
1536 [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false),
1537 [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false),
1538 [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false),
1539 [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false),
1540 };
1541
1542 static const struct rockchip_domain_info rk3066_pm_domains[] = {
1543 [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false, false),
1544 [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false, false),
1545 [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false, true),
1546 [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false, false),
1547 [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false, false),
1548 };
1549
1550 static const struct rockchip_domain_info rk3128_pm_domains[] = {
1551 [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false),
1552 [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true),
1553 [RK3128_PD_VIO] = DOMAIN_RK3288_PROTECT("vio", BIT(3), BIT(3), BIT(2), false),
1554 [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false),
1555 [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false),
1556 };
1557
1558 static const struct rockchip_domain_info rk3188_pm_domains[] = {
1559 [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false, false),
1560 [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false, false),
1561 [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false, true),
1562 [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false, false),
1563 [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false, false),
1564 };
1565
1566 static const struct rockchip_domain_info rk3228_pm_domains[] = {
1567 [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true),
1568 [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true),
1569 [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true),
1570 [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true),
1571 [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false),
1572 [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false),
1573 [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false),
1574 [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false),
1575 [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false),
1576 [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true),
1577 [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false),
1578 };
1579
1580 static const struct rockchip_domain_info rk3288_pm_domains[] = {
1581 [RK3288_PD_VIO] = DOMAIN_RK3288_PROTECT("vio", BIT(7), BIT(7), BIT(4), false),
1582 [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false),
1583 [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false),
1584 [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false),
1585 };
1586
1587 static const struct rockchip_domain_info rk3328_pm_domains[] = {
1588 [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false),
1589 [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false),
1590 [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true),
1591 [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true),
1592 [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true),
1593 [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false),
1594 [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false),
1595 [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false),
1596 [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false),
1597 };
1598
1599 static const struct rockchip_domain_info rk3366_pm_domains[] = {
1600 [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true),
1601 [RK3366_PD_VIO] = DOMAIN_RK3368_PROTECT("vio", BIT(14), BIT(14), BIT(8), false),
1602 [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false),
1603 [RK3366_PD_RKVDEC] = DOMAIN_RK3368("rkvdec", BIT(11), BIT(11), BIT(7), false),
1604 [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false),
1605 [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false),
1606 [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false),
1607 };
1608
1609 static const struct rockchip_domain_info rk3368_pm_domains[] = {
1610 [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true),
1611 [RK3368_PD_VIO] = DOMAIN_RK3368_PROTECT("vio", BIT(15), BIT(14), BIT(8), false),
1612 [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false),
1613 [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false),
1614 [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false),
1615 };
1616
1617 static const struct rockchip_domain_info rk3399_pm_domains[] = {
1618 [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false),
1619 [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false),
1620 [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true),
1621 [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true),
1622 [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true),
1623 [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true),
1624 [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true),
1625 [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true),
1626 [RK3399_PD_VIO] = DOMAIN_RK3399_PROTECT("vio", BIT(14), BIT(14), BIT(17), false),
1627 [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false),
1628 [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false),
1629 [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false),
1630 [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false),
1631 [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false),
1632 [RK3399_PD_VO] = DOMAIN_RK3399_PROTECT("vo", BIT(20), BIT(20), 0, false),
1633 [RK3399_PD_VOPB] = DOMAIN_RK3399_PROTECT("vopb", 0, 0, BIT(7), false),
1634 [RK3399_PD_VOPL] = DOMAIN_RK3399_PROTECT("vopl", 0, 0, BIT(8), false),
1635 [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false),
1636 [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false),
1637 [RK3399_PD_HDCP] = DOMAIN_RK3399_PROTECT("hdcp", BIT(24), BIT(24), BIT(11), false),
1638 [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true),
1639 [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true),
1640 [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true),
1641 [RK3399_PD_EDP] = DOMAIN_RK3399_PROTECT("edp", BIT(28), BIT(28), BIT(22), false),
1642 [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true),
1643 [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true),
1644 [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true),
1645 };
1646
1647 static const struct rockchip_domain_info rk3528_pm_domains[] = {
1648 [RK3528_PD_PMU] = DOMAIN_RK3528(0, BIT(0), true, false),
1649 [RK3528_PD_BUS] = DOMAIN_RK3528(0, BIT(1), true, false),
1650 [RK3528_PD_DDR] = DOMAIN_RK3528(0, BIT(2), true, false),
1651 [RK3528_PD_MSCH] = DOMAIN_RK3528(0, BIT(3), true, false),
1652 [RK3528_PD_GPU] = DOMAIN_RK3528(BIT(0), BIT(4), true, false),
1653 [RK3528_PD_RKVDEC] = DOMAIN_RK3528(0, BIT(5), true, false),
1654 [RK3528_PD_RKVENC] = DOMAIN_RK3528(0, BIT(6), true, false),
1655 [RK3528_PD_VO] = DOMAIN_RK3528(0, BIT(7), true, false),
1656 [RK3528_PD_VPU] = DOMAIN_RK3528(0, BIT(8), true, false),
1657 };
1658
1659 static const struct rockchip_domain_info rk3562_pm_domains[] = {
1660 [RK3562_PD_GPU] = DOMAIN_RK3562("gpu", BIT(0), BIT(1), 0, false),
1661 [RK3562_PD_NPU] = DOMAIN_RK3562("npu", BIT(1), BIT(2), 0, false),
1662 [RK3562_PD_VDPU] = DOMAIN_RK3562("vdpu", BIT(2), BIT(6), 0, false),
1663 [RK3562_PD_VEPU] = DOMAIN_RK3562("vepu", BIT(3), BIT(7), 0, false),
1664 [RK3562_PD_RGA] = DOMAIN_RK3562("rga", BIT(4), BIT(5), 0, false),
1665 [RK3562_PD_VI] = DOMAIN_RK3562("vi", BIT(5), BIT(3), 0, false),
1666 [RK3562_PD_VO] = DOMAIN_RK3562_PROTECT("vo", BIT(6), BIT(4), 16, false),
1667 [RK3562_PD_PHP] = DOMAIN_RK3562("php", BIT(7), BIT(8), 0, false),
1668 };
1669
1670 static const struct rockchip_domain_info rk3568_pm_domains[] = {
1671 [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false),
1672 [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false),
1673 [RK3568_PD_VI] = DOMAIN_RK3568("vi", BIT(6), BIT(3), false),
1674 [RK3568_PD_VO] = DOMAIN_RK3568_PROTECT("vo", BIT(7), BIT(4), false),
1675 [RK3568_PD_RGA] = DOMAIN_RK3568("rga", BIT(5), BIT(5), false),
1676 [RK3568_PD_VPU] = DOMAIN_RK3568("vpu", BIT(2), BIT(6), false),
1677 [RK3568_PD_RKVDEC] = DOMAIN_RK3568("rkvdec", BIT(4), BIT(8), false),
1678 [RK3568_PD_RKVENC] = DOMAIN_RK3568("rkvenc", BIT(3), BIT(7), false),
1679 [RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false),
1680 };
1681
1682 static const struct rockchip_domain_info rk3588_pm_domains[] = {
1683 /* name p_offset pwr status m_offset m_status r_status r_offset req idle wakeup */
1684 [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false),
1685 [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false),
1686 [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false),
1687 [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false),
1688 [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false),
1689 [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false),
1690 [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false),
1691 [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false),
1692 [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false),
1693 [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, 0x0, BIT(17), BIT(8), 0x0, BIT(7), BIT(7), false),
1694 [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, 0x0, BIT(18), BIT(9), 0x0, BIT(8), BIT(8), false),
1695 [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, 0x0, BIT(19), BIT(10), 0x0, 0, 0, false),
1696 [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, 0x0, BIT(20), BIT(11), 0x0, BIT(9), BIT(9), false),
1697 [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, 0x0, BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false),
1698 [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, 0x0, BIT(22), BIT(13), 0x0, 0, 0, false),
1699 [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, 0x0, BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false),
1700 [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, 0x0, BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false),
1701 [RK3588_PD_VOP] = DOMAIN_RK3588_P("vop", 0x4, BIT(1), 0, 0x0, BIT(25), BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false),
1702 [RK3588_PD_VO0] = DOMAIN_RK3588_P("vo0", 0x4, BIT(2), 0, 0x0, BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false),
1703 [RK3588_PD_VO1] = DOMAIN_RK3588_P("vo1", 0x4, BIT(3), 0, 0x0, BIT(27), BIT(18), 0x4, BIT(0), BIT(16), false),
1704 [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, 0x0, BIT(28), BIT(19), 0x4, BIT(1), BIT(17), false),
1705 [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, 0x0, BIT(29), BIT(20), 0x4, BIT(5), BIT(21), false),
1706 [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, 0x0, BIT(30), BIT(21), 0x0, 0, 0, false),
1707 [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, 0x0, BIT(31), BIT(22), 0x0, 0, 0, true),
1708 [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0x4, 0, 0, 0x4, BIT(2), BIT(18), false),
1709 [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, 0x4, BIT(1), BIT(23), 0x0, 0, 0, false),
1710 [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, 0x4, BIT(2), BIT(24), 0x4, BIT(3), BIT(19), false),
1711 [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, 0x4, BIT(3), BIT(25), 0x4, BIT(4), BIT(20), true),
1712 [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, 0x4, BIT(5), BIT(26), 0x0, 0, 0, false),
1713 };
1714
1715 static const struct rockchip_pmu_info px30_pmu = {
1716 .pwr_offset = 0x18,
1717 .status_offset = 0x20,
1718 .req_offset = 0x64,
1719 .idle_offset = 0x6c,
1720 .ack_offset = 0x6c,
1721
1722 .num_domains = ARRAY_SIZE(px30_pm_domains),
1723 .domain_info = px30_pm_domains,
1724 };
1725
1726 static const struct rockchip_pmu_info rk1808_pmu = {
1727 .pwr_offset = 0x18,
1728 .status_offset = 0x20,
1729 .req_offset = 0x64,
1730 .idle_offset = 0x6c,
1731 .ack_offset = 0x6c,
1732
1733 .num_domains = ARRAY_SIZE(rk1808_pm_domains),
1734 .domain_info = rk1808_pm_domains,
1735 };
1736
1737 static const struct rockchip_pmu_info rk3036_pmu = {
1738 .req_offset = 0x148,
1739 .idle_offset = 0x14c,
1740 .ack_offset = 0x14c,
1741
1742 .num_domains = ARRAY_SIZE(rk3036_pm_domains),
1743 .domain_info = rk3036_pm_domains,
1744 };
1745
1746 static const struct rockchip_pmu_info rk3066_pmu = {
1747 .pwr_offset = 0x08,
1748 .status_offset = 0x0c,
1749 .req_offset = 0x38, /* PMU_MISC_CON1 */
1750 .idle_offset = 0x0c,
1751 .ack_offset = 0x0c,
1752
1753 .num_domains = ARRAY_SIZE(rk3066_pm_domains),
1754 .domain_info = rk3066_pm_domains,
1755 };
1756
1757 static const struct rockchip_pmu_info rk3128_pmu = {
1758 .pwr_offset = 0x04,
1759 .status_offset = 0x08,
1760 .req_offset = 0x0c,
1761 .idle_offset = 0x10,
1762 .ack_offset = 0x10,
1763
1764 .num_domains = ARRAY_SIZE(rk3128_pm_domains),
1765 .domain_info = rk3128_pm_domains,
1766 };
1767
1768 static const struct rockchip_pmu_info rk3188_pmu = {
1769 .pwr_offset = 0x08,
1770 .status_offset = 0x0c,
1771 .req_offset = 0x38, /* PMU_MISC_CON1 */
1772 .idle_offset = 0x0c,
1773 .ack_offset = 0x0c,
1774
1775 .num_domains = ARRAY_SIZE(rk3188_pm_domains),
1776 .domain_info = rk3188_pm_domains,
1777 };
1778
1779 static const struct rockchip_pmu_info rk3228_pmu = {
1780 .req_offset = 0x40c,
1781 .idle_offset = 0x488,
1782 .ack_offset = 0x488,
1783
1784 .num_domains = ARRAY_SIZE(rk3228_pm_domains),
1785 .domain_info = rk3228_pm_domains,
1786 };
1787
1788 static const struct rockchip_pmu_info rk3288_pmu = {
1789 .pwr_offset = 0x08,
1790 .status_offset = 0x0c,
1791 .req_offset = 0x10,
1792 .idle_offset = 0x14,
1793 .ack_offset = 0x14,
1794
1795 .core_pwrcnt_offset = 0x34,
1796 .gpu_pwrcnt_offset = 0x3c,
1797
1798 .core_power_transition_time = 24, /* 1us */
1799 .gpu_power_transition_time = 24, /* 1us */
1800
1801 .num_domains = ARRAY_SIZE(rk3288_pm_domains),
1802 .domain_info = rk3288_pm_domains,
1803 };
1804
1805 static const struct rockchip_pmu_info rk3328_pmu = {
1806 .req_offset = 0x414,
1807 .idle_offset = 0x484,
1808 .ack_offset = 0x484,
1809
1810 .num_domains = ARRAY_SIZE(rk3328_pm_domains),
1811 .domain_info = rk3328_pm_domains,
1812 };
1813
1814 static const struct rockchip_pmu_info rk3366_pmu = {
1815 .pwr_offset = 0x0c,
1816 .status_offset = 0x10,
1817 .req_offset = 0x3c,
1818 .idle_offset = 0x40,
1819 .ack_offset = 0x40,
1820
1821 .core_pwrcnt_offset = 0x48,
1822 .gpu_pwrcnt_offset = 0x50,
1823
1824 .core_power_transition_time = 24,
1825 .gpu_power_transition_time = 24,
1826
1827 .num_domains = ARRAY_SIZE(rk3366_pm_domains),
1828 .domain_info = rk3366_pm_domains,
1829 };
1830
1831 static const struct rockchip_pmu_info rk3368_pmu = {
1832 .pwr_offset = 0x0c,
1833 .status_offset = 0x10,
1834 .req_offset = 0x3c,
1835 .idle_offset = 0x40,
1836 .ack_offset = 0x40,
1837
1838 .core_pwrcnt_offset = 0x48,
1839 .gpu_pwrcnt_offset = 0x50,
1840
1841 .core_power_transition_time = 24,
1842 .gpu_power_transition_time = 24,
1843
1844 .num_domains = ARRAY_SIZE(rk3368_pm_domains),
1845 .domain_info = rk3368_pm_domains,
1846 };
1847
1848 static const struct rockchip_pmu_info rk3399_pmu = {
1849 .pwr_offset = 0x14,
1850 .status_offset = 0x18,
1851 .req_offset = 0x60,
1852 .idle_offset = 0x64,
1853 .ack_offset = 0x68,
1854
1855 /* ARM Trusted Firmware manages power transition times */
1856
1857 .num_domains = ARRAY_SIZE(rk3399_pm_domains),
1858 .domain_info = rk3399_pm_domains,
1859 };
1860
1861 static const struct rockchip_pmu_info rk3528_pmu = {
1862 .pwr_offset = 0x1210,
1863 .status_offset = 0x1230,
1864 .req_offset = 0x1110,
1865 .idle_offset = 0x1128,
1866 .ack_offset = 0x1120,
1867
1868 .num_domains = ARRAY_SIZE(rk3528_pm_domains),
1869 .domain_info = rk3528_pm_domains,
1870 };
1871
1872 static const struct rockchip_pmu_info rk3562_pmu = {
1873 .pwr_offset = 0x210,
1874 .status_offset = 0x230,
1875 .req_offset = 0x110,
1876 .idle_offset = 0x128,
1877 .ack_offset = 0x120,
1878 .clk_ungate_offset = 0x140,
1879 .mem_sd_offset = 0x300,
1880
1881 .num_domains = ARRAY_SIZE(rk3562_pm_domains),
1882 .domain_info = rk3562_pm_domains,
1883 };
1884
1885 static const struct rockchip_pmu_info rk3568_pmu = {
1886 .pwr_offset = 0xa0,
1887 .status_offset = 0x98,
1888 .req_offset = 0x50,
1889 .idle_offset = 0x68,
1890 .ack_offset = 0x60,
1891
1892 .num_domains = ARRAY_SIZE(rk3568_pm_domains),
1893 .domain_info = rk3568_pm_domains,
1894 };
1895
1896 static const struct rockchip_pmu_info rk3588_pmu = {
1897 .pwr_offset = 0x14c,
1898 .status_offset = 0x180,
1899 .req_offset = 0x10c,
1900 .idle_offset = 0x120,
1901 .ack_offset = 0x118,
1902 .mem_pwr_offset = 0x1a0,
1903 .chain_status_offset = 0x1f0,
1904 .mem_status_offset = 0x1f8,
1905 .repair_status_offset = 0x290,
1906
1907 .num_domains = ARRAY_SIZE(rk3588_pm_domains),
1908 .domain_info = rk3588_pm_domains,
1909 };
1910
1911 static const struct rockchip_pmu_info rv1126_pmu = {
1912 .pwr_offset = 0x110,
1913 .status_offset = 0x108,
1914 .req_offset = 0xc0,
1915 .idle_offset = 0xd8,
1916 .ack_offset = 0xd0,
1917
1918 .num_domains = ARRAY_SIZE(rv1126_pm_domains),
1919 .domain_info = rv1126_pm_domains,
1920 };
1921
1922 static const struct of_device_id rockchip_pm_domain_dt_match[] = {
1923 {
1924 .compatible = "rockchip,px30-power-controller",
1925 .data = (void *)&px30_pmu,
1926 },
1927 {
1928 .compatible = "rockchip,rk1808-power-controller",
1929 .data = (void *)&rk1808_pmu,
1930 },
1931 {
1932 .compatible = "rockchip,rk3036-power-controller",
1933 .data = (void *)&rk3036_pmu,
1934 },
1935 {
1936 .compatible = "rockchip,rk3066-power-controller",
1937 .data = (void *)&rk3066_pmu,
1938 },
1939 {
1940 .compatible = "rockchip,rk3128-power-controller",
1941 .data = (void *)&rk3128_pmu,
1942 },
1943 {
1944 .compatible = "rockchip,rk3188-power-controller",
1945 .data = (void *)&rk3188_pmu,
1946 },
1947 {
1948 .compatible = "rockchip,rk3228-power-controller",
1949 .data = (void *)&rk3228_pmu,
1950 },
1951 {
1952 .compatible = "rockchip,rk3288-power-controller",
1953 .data = (void *)&rk3288_pmu,
1954 },
1955 {
1956 .compatible = "rockchip,rk3328-power-controller",
1957 .data = (void *)&rk3328_pmu,
1958 },
1959 {
1960 .compatible = "rockchip,rk3366-power-controller",
1961 .data = (void *)&rk3366_pmu,
1962 },
1963 {
1964 .compatible = "rockchip,rk3368-power-controller",
1965 .data = (void *)&rk3368_pmu,
1966 },
1967 {
1968 .compatible = "rockchip,rk3399-power-controller",
1969 .data = (void *)&rk3399_pmu,
1970 },
1971 #ifdef CONFIG_CPU_RK3528
1972 {
1973 .compatible = "rockchip,rk3528-power-controller",
1974 .data = (void *)&rk3528_pmu,
1975 },
1976 #endif
1977 {
1978 .compatible = "rockchip,rk3562-power-controller",
1979 .data = (void *)&rk3562_pmu,
1980 },
1981 {
1982 .compatible = "rockchip,rk3568-power-controller",
1983 .data = (void *)&rk3568_pmu,
1984 },
1985 {
1986 .compatible = "rockchip,rk3588-power-controller",
1987 .data = (void *)&rk3588_pmu,
1988 },
1989 {
1990 .compatible = "rockchip,rv1126-power-controller",
1991 .data = (void *)&rv1126_pmu,
1992 },
1993 { /* sentinel */ },
1994 };
1995 MODULE_DEVICE_TABLE(of, rockchip_pm_domain_dt_match);
1996
1997 static struct platform_driver rockchip_pm_domain_driver = {
1998 .probe = rockchip_pm_domain_probe,
1999 .driver = {
2000 .name = "rockchip-pm-domain",
2001 .of_match_table = rockchip_pm_domain_dt_match,
2002 /*
2003 * We can't forcibly eject devices form power domain,
2004 * so we can't really remove power domains once they
2005 * were added.
2006 */
2007 .suppress_bind_attrs = true,
2008 },
2009 };
2010
rockchip_pm_domain_drv_register(void)2011 static int __init rockchip_pm_domain_drv_register(void)
2012 {
2013 return platform_driver_register(&rockchip_pm_domain_driver);
2014 }
2015 postcore_initcall(rockchip_pm_domain_drv_register);
2016
rockchip_pm_domain_drv_unregister(void)2017 static void __exit rockchip_pm_domain_drv_unregister(void)
2018 {
2019 platform_driver_unregister(&rockchip_pm_domain_driver);
2020 }
2021 module_exit(rockchip_pm_domain_drv_unregister);
2022
2023 MODULE_DESCRIPTION("ROCKCHIP PM Domain Driver");
2024 MODULE_LICENSE("GPL");
2025