1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2019 MediaTek Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _UFS_MEDIATEK_H 7*4882a593Smuzhiyun #define _UFS_MEDIATEK_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/bitops.h> 10*4882a593Smuzhiyun #include <linux/soc/mediatek/mtk_sip_svc.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * Vendor specific UFSHCI Registers 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #define REG_UFS_REFCLK_CTRL 0x144 16*4882a593Smuzhiyun #define REG_UFS_EXTREG 0x2100 17*4882a593Smuzhiyun #define REG_UFS_MPHYCTRL 0x2200 18*4882a593Smuzhiyun #define REG_UFS_REJECT_MON 0x22AC 19*4882a593Smuzhiyun #define REG_UFS_DEBUG_SEL 0x22C0 20*4882a593Smuzhiyun #define REG_UFS_PROBE 0x22C8 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * Ref-clk control 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * Values for register REG_UFS_REFCLK_CTRL 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun #define REFCLK_RELEASE 0x0 28*4882a593Smuzhiyun #define REFCLK_REQUEST BIT(0) 29*4882a593Smuzhiyun #define REFCLK_ACK BIT(1) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define REFCLK_REQ_TIMEOUT_US 3000 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * Vendor specific pre-defined parameters 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun #define UFS_MTK_LIMIT_NUM_LANES_RX 2 37*4882a593Smuzhiyun #define UFS_MTK_LIMIT_NUM_LANES_TX 2 38*4882a593Smuzhiyun #define UFS_MTK_LIMIT_HSGEAR_RX UFS_HS_G4 39*4882a593Smuzhiyun #define UFS_MTK_LIMIT_HSGEAR_TX UFS_HS_G4 40*4882a593Smuzhiyun #define UFS_MTK_LIMIT_PWMGEAR_RX UFS_PWM_G4 41*4882a593Smuzhiyun #define UFS_MTK_LIMIT_PWMGEAR_TX UFS_PWM_G4 42*4882a593Smuzhiyun #define UFS_MTK_LIMIT_RX_PWR_PWM SLOW_MODE 43*4882a593Smuzhiyun #define UFS_MTK_LIMIT_TX_PWR_PWM SLOW_MODE 44*4882a593Smuzhiyun #define UFS_MTK_LIMIT_RX_PWR_HS FAST_MODE 45*4882a593Smuzhiyun #define UFS_MTK_LIMIT_TX_PWR_HS FAST_MODE 46*4882a593Smuzhiyun #define UFS_MTK_LIMIT_HS_RATE PA_HS_MODE_B 47*4882a593Smuzhiyun #define UFS_MTK_LIMIT_DESIRED_MODE UFS_HS_MODE 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* 50*4882a593Smuzhiyun * Other attributes 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun #define VS_DEBUGCLOCKENABLE 0xD0A1 53*4882a593Smuzhiyun #define VS_SAVEPOWERCONTROL 0xD0A6 54*4882a593Smuzhiyun #define VS_UNIPROPOWERDOWNCONTROL 0xD0A8 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* 57*4882a593Smuzhiyun * Vendor specific link state 58*4882a593Smuzhiyun */ 59*4882a593Smuzhiyun enum { 60*4882a593Smuzhiyun VS_LINK_DISABLED = 0, 61*4882a593Smuzhiyun VS_LINK_DOWN = 1, 62*4882a593Smuzhiyun VS_LINK_UP = 2, 63*4882a593Smuzhiyun VS_LINK_HIBERN8 = 3, 64*4882a593Smuzhiyun VS_LINK_LOST = 4, 65*4882a593Smuzhiyun VS_LINK_CFG = 5, 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* 69*4882a593Smuzhiyun * SiP commands 70*4882a593Smuzhiyun */ 71*4882a593Smuzhiyun #define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276) 72*4882a593Smuzhiyun #define UFS_MTK_SIP_VA09_PWR_CTRL BIT(0) 73*4882a593Smuzhiyun #define UFS_MTK_SIP_DEVICE_RESET BIT(1) 74*4882a593Smuzhiyun #define UFS_MTK_SIP_CRYPTO_CTRL BIT(2) 75*4882a593Smuzhiyun #define UFS_MTK_SIP_REF_CLK_NOTIFICATION BIT(3) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* 78*4882a593Smuzhiyun * VS_DEBUGCLOCKENABLE 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun enum { 81*4882a593Smuzhiyun TX_SYMBOL_CLK_REQ_FORCE = 5, 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* 85*4882a593Smuzhiyun * VS_SAVEPOWERCONTROL 86*4882a593Smuzhiyun */ 87*4882a593Smuzhiyun enum { 88*4882a593Smuzhiyun RX_SYMBOL_CLK_GATE_EN = 0, 89*4882a593Smuzhiyun SYS_CLK_GATE_EN = 2, 90*4882a593Smuzhiyun TX_CLK_GATE_EN = 3, 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* 94*4882a593Smuzhiyun * Host capability 95*4882a593Smuzhiyun */ 96*4882a593Smuzhiyun enum ufs_mtk_host_caps { 97*4882a593Smuzhiyun UFS_MTK_CAP_BOOST_CRYPT_ENGINE = 1 << 0, 98*4882a593Smuzhiyun UFS_MTK_CAP_VA09_PWR_CTRL = 1 << 1, 99*4882a593Smuzhiyun UFS_MTK_CAP_DISABLE_AH8 = 1 << 2, 100*4882a593Smuzhiyun UFS_MTK_CAP_BROKEN_VCC = 1 << 3, 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun struct ufs_mtk_crypt_cfg { 104*4882a593Smuzhiyun struct regulator *reg_vcore; 105*4882a593Smuzhiyun struct clk *clk_crypt_perf; 106*4882a593Smuzhiyun struct clk *clk_crypt_mux; 107*4882a593Smuzhiyun struct clk *clk_crypt_lp; 108*4882a593Smuzhiyun int vcore_volt; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun struct ufs_mtk_hw_ver { 112*4882a593Smuzhiyun u8 step; 113*4882a593Smuzhiyun u8 minor; 114*4882a593Smuzhiyun u8 major; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun struct ufs_mtk_host { 118*4882a593Smuzhiyun struct phy *mphy; 119*4882a593Smuzhiyun struct regulator *reg_va09; 120*4882a593Smuzhiyun struct ufs_mtk_hw_ver hw_ver; 121*4882a593Smuzhiyun struct reset_control *hci_reset; 122*4882a593Smuzhiyun struct reset_control *unipro_reset; 123*4882a593Smuzhiyun struct reset_control *crypto_reset; 124*4882a593Smuzhiyun struct ufs_hba *hba; 125*4882a593Smuzhiyun struct ufs_mtk_crypt_cfg *crypt; 126*4882a593Smuzhiyun enum ufs_mtk_host_caps caps; 127*4882a593Smuzhiyun bool mphy_powered_on; 128*4882a593Smuzhiyun bool unipro_lpm; 129*4882a593Smuzhiyun bool ref_clk_enabled; 130*4882a593Smuzhiyun u16 ref_clk_ungating_wait_us; 131*4882a593Smuzhiyun u16 ref_clk_gating_wait_us; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #endif /* !_UFS_MEDIATEK_H */ 135