1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2019 MediaTek Inc. 4 */ 5 6 #ifndef _UFS_MEDIATEK_H 7 #define _UFS_MEDIATEK_H 8 9 #include <linux/bitops.h> 10 #include <linux/soc/mediatek/mtk_sip_svc.h> 11 12 /* 13 * Vendor specific UFSHCI Registers 14 */ 15 #define REG_UFS_REFCLK_CTRL 0x144 16 #define REG_UFS_EXTREG 0x2100 17 #define REG_UFS_MPHYCTRL 0x2200 18 #define REG_UFS_REJECT_MON 0x22AC 19 #define REG_UFS_DEBUG_SEL 0x22C0 20 #define REG_UFS_PROBE 0x22C8 21 22 /* 23 * Ref-clk control 24 * 25 * Values for register REG_UFS_REFCLK_CTRL 26 */ 27 #define REFCLK_RELEASE 0x0 28 #define REFCLK_REQUEST BIT(0) 29 #define REFCLK_ACK BIT(1) 30 31 #define REFCLK_REQ_TIMEOUT_US 3000 32 33 /* 34 * Vendor specific pre-defined parameters 35 */ 36 #define UFS_MTK_LIMIT_NUM_LANES_RX 2 37 #define UFS_MTK_LIMIT_NUM_LANES_TX 2 38 #define UFS_MTK_LIMIT_HSGEAR_RX UFS_HS_G4 39 #define UFS_MTK_LIMIT_HSGEAR_TX UFS_HS_G4 40 #define UFS_MTK_LIMIT_PWMGEAR_RX UFS_PWM_G4 41 #define UFS_MTK_LIMIT_PWMGEAR_TX UFS_PWM_G4 42 #define UFS_MTK_LIMIT_RX_PWR_PWM SLOW_MODE 43 #define UFS_MTK_LIMIT_TX_PWR_PWM SLOW_MODE 44 #define UFS_MTK_LIMIT_RX_PWR_HS FAST_MODE 45 #define UFS_MTK_LIMIT_TX_PWR_HS FAST_MODE 46 #define UFS_MTK_LIMIT_HS_RATE PA_HS_MODE_B 47 #define UFS_MTK_LIMIT_DESIRED_MODE UFS_HS_MODE 48 49 /* 50 * Other attributes 51 */ 52 #define VS_DEBUGCLOCKENABLE 0xD0A1 53 #define VS_SAVEPOWERCONTROL 0xD0A6 54 #define VS_UNIPROPOWERDOWNCONTROL 0xD0A8 55 56 /* 57 * Vendor specific link state 58 */ 59 enum { 60 VS_LINK_DISABLED = 0, 61 VS_LINK_DOWN = 1, 62 VS_LINK_UP = 2, 63 VS_LINK_HIBERN8 = 3, 64 VS_LINK_LOST = 4, 65 VS_LINK_CFG = 5, 66 }; 67 68 /* 69 * SiP commands 70 */ 71 #define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276) 72 #define UFS_MTK_SIP_VA09_PWR_CTRL BIT(0) 73 #define UFS_MTK_SIP_DEVICE_RESET BIT(1) 74 #define UFS_MTK_SIP_CRYPTO_CTRL BIT(2) 75 #define UFS_MTK_SIP_REF_CLK_NOTIFICATION BIT(3) 76 77 /* 78 * VS_DEBUGCLOCKENABLE 79 */ 80 enum { 81 TX_SYMBOL_CLK_REQ_FORCE = 5, 82 }; 83 84 /* 85 * VS_SAVEPOWERCONTROL 86 */ 87 enum { 88 RX_SYMBOL_CLK_GATE_EN = 0, 89 SYS_CLK_GATE_EN = 2, 90 TX_CLK_GATE_EN = 3, 91 }; 92 93 /* 94 * Host capability 95 */ 96 enum ufs_mtk_host_caps { 97 UFS_MTK_CAP_BOOST_CRYPT_ENGINE = 1 << 0, 98 UFS_MTK_CAP_VA09_PWR_CTRL = 1 << 1, 99 UFS_MTK_CAP_DISABLE_AH8 = 1 << 2, 100 UFS_MTK_CAP_BROKEN_VCC = 1 << 3, 101 }; 102 103 struct ufs_mtk_crypt_cfg { 104 struct regulator *reg_vcore; 105 struct clk *clk_crypt_perf; 106 struct clk *clk_crypt_mux; 107 struct clk *clk_crypt_lp; 108 int vcore_volt; 109 }; 110 111 struct ufs_mtk_hw_ver { 112 u8 step; 113 u8 minor; 114 u8 major; 115 }; 116 117 struct ufs_mtk_host { 118 struct phy *mphy; 119 struct regulator *reg_va09; 120 struct ufs_mtk_hw_ver hw_ver; 121 struct reset_control *hci_reset; 122 struct reset_control *unipro_reset; 123 struct reset_control *crypto_reset; 124 struct ufs_hba *hba; 125 struct ufs_mtk_crypt_cfg *crypt; 126 enum ufs_mtk_host_caps caps; 127 bool mphy_powered_on; 128 bool unipro_lpm; 129 bool ref_clk_enabled; 130 u16 ref_clk_ungating_wait_us; 131 u16 ref_clk_gating_wait_us; 132 }; 133 134 #endif /* !_UFS_MEDIATEK_H */ 135