1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2018, Fuzhou Rockchip Electronics Co., Ltd
4 * Author: Jeffy Chen <jeffy.chen@rock-chips.com>
5 *
6 * Base on the Rockchip timer driver drivers/clocksource/rockchip_timer.c by
7 * Daniel Lezcano <daniel.lezcano@linaro.org>
8 */
9
10 #include <linux/clk.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
17 #include <linux/rtc.h>
18
19 #define DRV_NAME "rk-timer-rtc"
20
21 #define TIMER_LOAD_COUNT0 0x00
22 #define TIMER_LOAD_COUNT1 0x04
23 #define TIMER_CURRENT_VALUE0 0x08
24 #define TIMER_CURRENT_VALUE1 0x0C
25 #define TIMER_CONTROL_REG3288 0x10
26 #define TIMER_INT_STATUS 0x18
27
28 #define TIMER_ENABLE BIT(0)
29 #define TIMER_MODE_USER_DEFINED_COUNT BIT(1)
30 #define TIMER_INT_UNMASK BIT(2)
31
32 /* Forbid any alarms which would trigger inside the threshold */
33 #define TIMER_ALARM_THRESHOLD_MS 10
34
35 #if !defined(UINT64_MAX)
36 #define UINT64_MAX ((u64)-1)
37 #endif
38
39 /**
40 * struct rk_timer_rtc_data - Differences between SoC variants
41 *
42 * @ctrl_reg_offset: The offset of timer control register
43 */
44 struct rk_timer_rtc_data {
45 int ctrl_reg_offset;
46 };
47
48 /**
49 * struct rk_timer_rtc - Driver data for Rockchip timer RTC
50 *
51 * @data: Pointer to rk_timer_rtc_data
52 * @regmap: Register map of the timer
53 * @rtc: Pointer to RTC device
54 * @clk: The timer clock
55 * @pclk: The peripheral clock
56 * @freq: The freq of timer clock
57 * @timebase: The base time of the timer RTC
58 * @alarm_irq_enabled: Whether to report alarm irqs
59 * @irq: The timer IRQ number
60 */
61 struct rk_timer_rtc {
62 const struct rk_timer_rtc_data *data;
63 struct regmap *regmap;
64 struct rtc_device *rtc;
65 struct clk *clk;
66 struct clk *pclk;
67 u32 freq;
68 u64 timebase;
69 int alarm_irq_enabled;
70 int irq;
71 };
72
tick_to_sec(struct rk_timer_rtc * rk_timer_rtc,u64 tick)73 static inline u64 tick_to_sec(struct rk_timer_rtc *rk_timer_rtc, u64 tick)
74 {
75 do_div(tick, rk_timer_rtc->freq);
76 return tick;
77 }
78
ms_to_tick(struct rk_timer_rtc * rk_timer_rtc,int ms)79 static inline u64 ms_to_tick(struct rk_timer_rtc *rk_timer_rtc, int ms)
80 {
81 return ms * rk_timer_rtc->freq / 1000;
82 }
83
tick_to_time64(struct rk_timer_rtc * rk_timer_rtc,u64 tick)84 static inline u64 tick_to_time64(struct rk_timer_rtc *rk_timer_rtc, u64 tick)
85 {
86 return tick_to_sec(rk_timer_rtc, tick) + rk_timer_rtc->timebase;
87 }
88
time64_to_tick(struct rk_timer_rtc * rk_timer_rtc,u64 time)89 static inline u64 time64_to_tick(struct rk_timer_rtc *rk_timer_rtc, u64 time)
90 {
91 return (time - rk_timer_rtc->timebase) * rk_timer_rtc->freq;
92 }
93
rk_timer_rtc_write64(struct rk_timer_rtc * rk_timer_rtc,u32 reg,u64 val)94 static inline int rk_timer_rtc_write64(struct rk_timer_rtc *rk_timer_rtc,
95 u32 reg, u64 val)
96 {
97 return regmap_bulk_write(rk_timer_rtc->regmap, reg, &val, 2);
98 }
99
rk_timer_rtc_read64(struct rk_timer_rtc * rk_timer_rtc,u32 reg,u64 * val)100 static inline int rk_timer_rtc_read64(struct rk_timer_rtc *rk_timer_rtc,
101 u32 reg, u64 *val)
102 {
103 u32 val_lo, val_hi, tmp_hi;
104 int ret;
105
106 do {
107 ret = regmap_read(rk_timer_rtc->regmap, reg + 4, &val_hi);
108 if (ret)
109 return ret;
110
111 ret = regmap_read(rk_timer_rtc->regmap, reg, &val_lo);
112 if (ret)
113 return ret;
114
115 ret = regmap_read(rk_timer_rtc->regmap, reg + 4, &tmp_hi);
116 if (ret)
117 return ret;
118 } while (val_hi != tmp_hi);
119
120 *val = ((u64) val_hi << 32) | val_lo;
121
122 return 0;
123 }
124
rk_timer_rtc_irq_clear(struct rk_timer_rtc * rk_timer_rtc)125 static inline int rk_timer_rtc_irq_clear(struct rk_timer_rtc *rk_timer_rtc)
126 {
127 return regmap_write(rk_timer_rtc->regmap, TIMER_INT_STATUS, 1);
128 }
129
rk_timer_rtc_irq_enable(struct rk_timer_rtc * rk_timer_rtc,unsigned int enabled)130 static inline int rk_timer_rtc_irq_enable(struct rk_timer_rtc *rk_timer_rtc,
131 unsigned int enabled)
132 {
133 /* Clear any pending irq before enable it */
134 if (enabled)
135 rk_timer_rtc_irq_clear(rk_timer_rtc);
136
137 return regmap_update_bits(rk_timer_rtc->regmap,
138 rk_timer_rtc->data->ctrl_reg_offset,
139 TIMER_INT_UNMASK,
140 enabled ? TIMER_INT_UNMASK : 0);
141 }
142
rk_timer_rtc_reset(struct rk_timer_rtc * rk_timer_rtc)143 static int rk_timer_rtc_reset(struct rk_timer_rtc *rk_timer_rtc)
144 {
145 int ret;
146
147 ret = regmap_write(rk_timer_rtc->regmap,
148 rk_timer_rtc->data->ctrl_reg_offset, 0);
149 if (ret)
150 return ret;
151
152 /* Init load count to UINT64_MAX to keep timer running */
153 ret = rk_timer_rtc_write64(rk_timer_rtc, TIMER_LOAD_COUNT0, UINT64_MAX);
154 if (ret)
155 return ret;
156
157 /* Clear any pending irq before enable it */
158 rk_timer_rtc_irq_clear(rk_timer_rtc);
159
160 /* Enable timer in user-defined count mode with irq unmasked */
161 return regmap_write(rk_timer_rtc->regmap,
162 rk_timer_rtc->data->ctrl_reg_offset,
163 TIMER_ENABLE | TIMER_MODE_USER_DEFINED_COUNT |
164 TIMER_INT_UNMASK);
165 }
166
rk_timer_rtc_read_time(struct device * dev,struct rtc_time * tm)167 static int rk_timer_rtc_read_time(struct device *dev, struct rtc_time *tm)
168 {
169 struct rk_timer_rtc *rk_timer_rtc = dev_get_drvdata(dev);
170 int ret;
171 u64 tick;
172
173 ret = rk_timer_rtc_read64(rk_timer_rtc, TIMER_CURRENT_VALUE0, &tick);
174 if (ret)
175 return ret;
176
177 rtc_time64_to_tm(tick_to_time64(rk_timer_rtc, tick), tm);
178
179 dev_dbg(dev, "Read RTC: %4d-%02d-%02d(%d) %02d:%02d:%02d\n",
180 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday,
181 tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec);
182
183 return rtc_valid_tm(tm);
184 }
185
rk_timer_rtc_set_time(struct device * dev,struct rtc_time * tm)186 static int rk_timer_rtc_set_time(struct device *dev, struct rtc_time *tm)
187 {
188 struct rk_timer_rtc *rk_timer_rtc = dev_get_drvdata(dev);
189 int ret;
190
191 dev_dbg(dev, "Set RTC:%4d-%02d-%02d(%d) %02d:%02d:%02d\n",
192 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday,
193 tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec);
194
195 ret = rtc_valid_tm(tm);
196 if (ret)
197 return ret;
198
199 rk_timer_rtc->timebase = rtc_tm_to_time64(tm);
200
201 dev_dbg(dev, "Setting new timebase:%lld\n", rk_timer_rtc->timebase);
202
203 /* Restart timer for new timebase */
204 ret = rk_timer_rtc_reset(rk_timer_rtc);
205 if (ret) {
206 dev_err(dev, "Failed to reset timer:%d\n", ret);
207 return ret;
208 }
209
210 /* Tell framework to check alarms */
211 rtc_update_irq(rk_timer_rtc->rtc, 1, RTC_IRQF | RTC_AF);
212
213 return 0;
214 }
215
rk_timer_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alrm)216 static int rk_timer_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
217 {
218 struct rk_timer_rtc *rk_timer_rtc = dev_get_drvdata(dev);
219 int ret;
220 u64 tick;
221
222 ret = rk_timer_rtc_read64(rk_timer_rtc, TIMER_LOAD_COUNT0, &tick);
223 if (ret)
224 return ret;
225
226 rtc_time64_to_tm(tick_to_time64(rk_timer_rtc, tick), &alrm->time);
227
228 dev_dbg(dev, "Read alarm: %4d-%02d-%02d(%d) %02d:%02d:%02d\n",
229 1900 + alrm->time.tm_year, alrm->time.tm_mon + 1,
230 alrm->time.tm_mday, alrm->time.tm_wday, alrm->time.tm_hour,
231 alrm->time.tm_min, alrm->time.tm_sec);
232
233 return rtc_valid_tm(&alrm->time);
234 }
235
rk_timer_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alrm)236 static int rk_timer_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
237 {
238 struct rk_timer_rtc *rk_timer_rtc = dev_get_drvdata(dev);
239 int ret;
240 u64 alarm_tick, alarm_threshold_tick, cur_tick;
241
242 dev_dbg(dev, "Set alarm:%4d-%02d-%02d(%d) %02d:%02d:%02d\n",
243 1900 + alrm->time.tm_year, alrm->time.tm_mon + 1,
244 alrm->time.tm_mday, alrm->time.tm_wday, alrm->time.tm_hour,
245 alrm->time.tm_min, alrm->time.tm_sec);
246
247 ret = rtc_valid_tm(&alrm->time);
248 if (ret)
249 return ret;
250
251 rk_timer_rtc->alarm_irq_enabled = false;
252
253 alarm_tick = time64_to_tick(rk_timer_rtc,
254 rtc_tm_to_time64(&alrm->time));
255
256 ret = rk_timer_rtc_read64(rk_timer_rtc, TIMER_CURRENT_VALUE0,
257 &cur_tick);
258 if (ret)
259 return ret;
260
261 /* Don't set an alarm in the past or about to pass */
262 alarm_threshold_tick = ms_to_tick(rk_timer_rtc,
263 TIMER_ALARM_THRESHOLD_MS);
264 if (alarm_tick <= (cur_tick + alarm_threshold_tick))
265 return -ETIME;
266
267 /*
268 * When the current value counts up to the load count, the timer will
269 * stop and generate an irq.
270 */
271 ret = rk_timer_rtc_write64(rk_timer_rtc, TIMER_LOAD_COUNT0, alarm_tick);
272 if (ret)
273 return ret;
274
275 dev_dbg(dev, "New alarm enabled:%d\n", alrm->enabled);
276 rk_timer_rtc->alarm_irq_enabled = alrm->enabled;
277
278 return 0;
279 }
280
rk_timer_rtc_alarm_irq_enable(struct device * dev,unsigned int enabled)281 static int rk_timer_rtc_alarm_irq_enable(struct device *dev,
282 unsigned int enabled)
283 {
284 struct rk_timer_rtc *rk_timer_rtc = dev_get_drvdata(dev);
285
286 dev_dbg(dev, "Set alarm irq enabled:%d\n", enabled);
287 rk_timer_rtc->alarm_irq_enabled = enabled;
288
289 return 0;
290 }
291
rk_timer_rtc_alarm_irq(int irq,void * data)292 static irqreturn_t rk_timer_rtc_alarm_irq(int irq, void *data)
293 {
294 struct device *dev = data;
295 struct rk_timer_rtc *rk_timer_rtc = dev_get_drvdata(dev);
296 int ret;
297
298 dev_dbg(dev, "Received timer irq, alarm_irq_enabled:%d\n",
299 rk_timer_rtc->alarm_irq_enabled);
300
301 /* The timer is stopped now, reset the load count to start it again */
302 ret = rk_timer_rtc_write64(rk_timer_rtc, TIMER_LOAD_COUNT0, UINT64_MAX);
303 if (ret)
304 dev_err(dev, "Failed to set load count:%d\n", ret);
305
306 ret = regmap_write(rk_timer_rtc->regmap, TIMER_INT_STATUS, 1);
307 if (ret)
308 dev_err(dev, "Failed to clear irq:%d\n", ret);
309
310 /* Only report rtc irq when alarm irq is enabled */
311 if (rk_timer_rtc->alarm_irq_enabled)
312 rtc_update_irq(rk_timer_rtc->rtc, 1, RTC_IRQF | RTC_AF);
313
314 return IRQ_HANDLED;
315 }
316
317 static const struct rtc_class_ops rk_timer_rtc_ops = {
318 .read_time = rk_timer_rtc_read_time,
319 .set_time = rk_timer_rtc_set_time,
320 .read_alarm = rk_timer_rtc_read_alarm,
321 .set_alarm = rk_timer_rtc_set_alarm,
322 .alarm_irq_enable = rk_timer_rtc_alarm_irq_enable,
323 };
324
325 static struct regmap_config rk_timer_regmap_config = {
326 .name = DRV_NAME,
327 .reg_bits = 32,
328 .val_bits = 32,
329 .reg_stride = 4,
330 };
331
332 static const struct of_device_id rk_timer_rtc_dt_match[];
333
rk_timer_rtc_probe(struct platform_device * pdev)334 static int rk_timer_rtc_probe(struct platform_device *pdev)
335 {
336 const struct of_device_id *match;
337 struct device *dev = &pdev->dev;
338 struct rk_timer_rtc *rk_timer_rtc;
339 void __iomem *base;
340 resource_size_t size;
341 int ret;
342
343 rk_timer_rtc = devm_kzalloc(dev, sizeof(*rk_timer_rtc), GFP_KERNEL);
344 if (!rk_timer_rtc)
345 return -ENOMEM;
346
347 match = of_match_node(rk_timer_rtc_dt_match, dev->of_node);
348 rk_timer_rtc->data = match->data;
349
350 platform_set_drvdata(pdev, rk_timer_rtc);
351
352 base = devm_of_iomap(dev, dev->of_node, 0, &size);
353 if (!base) {
354 dev_err(dev, "Failed to iomap\n");
355 return -EINVAL;
356 }
357
358 rk_timer_regmap_config.max_register = size - 4;
359 rk_timer_rtc->regmap = devm_regmap_init_mmio(dev, base,
360 &rk_timer_regmap_config);
361 if (IS_ERR(rk_timer_rtc->regmap)) {
362 ret = PTR_ERR(rk_timer_rtc->regmap);
363 dev_err(dev, "Failed to init regmap:%d\n", ret);
364 return ret;
365 }
366
367 rk_timer_rtc->irq = platform_get_irq(pdev, 0);
368 if (rk_timer_rtc->irq < 0) {
369 ret = rk_timer_rtc->irq;
370 dev_err(dev, "Failed to get irq:%d\n", ret);
371 return ret;
372 }
373
374 ret = devm_request_irq(dev, rk_timer_rtc->irq, rk_timer_rtc_alarm_irq,
375 0, dev_name(dev), dev);
376 if (ret) {
377 dev_err(dev, "Failed to request irq:%d\n", ret);
378 return ret;
379 }
380
381 rk_timer_rtc->pclk = devm_clk_get(dev, "pclk");
382 if (IS_ERR(rk_timer_rtc->pclk)) {
383 ret = PTR_ERR(rk_timer_rtc->pclk);
384 pr_err("Failed to get timer pclk:%d\n", ret);
385 return ret;
386 }
387
388 ret = clk_prepare_enable(rk_timer_rtc->pclk);
389 if (ret) {
390 dev_err(dev, "Failed to enable pclk:%d\n", ret);
391 return ret;
392 }
393
394 rk_timer_rtc->clk = devm_clk_get(dev, "timer");
395 if (IS_ERR(rk_timer_rtc->clk)) {
396 ret = PTR_ERR(rk_timer_rtc->clk);
397 pr_err("Failed to get timer clk:%d\n", ret);
398 goto err_disable_pclk;
399 }
400
401 ret = clk_prepare_enable(rk_timer_rtc->clk);
402 if (ret) {
403 dev_err(dev, "Failed to enable timer clk:%d\n", ret);
404 goto err_disable_pclk;
405 }
406
407 rk_timer_rtc->freq = clk_get_rate(rk_timer_rtc->clk);
408 dev_dbg(dev, "RTC timer freq:%d\n", rk_timer_rtc->freq);
409
410 ret = rk_timer_rtc_reset(rk_timer_rtc);
411 if (ret) {
412 dev_err(dev, "Failed to reset timer:%d\n", ret);
413 goto err_disable_clk;
414 }
415
416 ret = device_init_wakeup(dev, true);
417 if (ret) {
418 dev_err(dev, "Failed to init wakeup:%d\n", ret);
419 goto err_disable_irq;
420 }
421
422 rk_timer_rtc->rtc = devm_rtc_device_register(dev, DRV_NAME,
423 &rk_timer_rtc_ops,
424 THIS_MODULE);
425 if (IS_ERR(rk_timer_rtc->rtc)) {
426 ret = PTR_ERR(rk_timer_rtc->rtc);
427 dev_err(dev, "Failed to register rtc:%d\n", ret);
428 goto err_uninit_wakeup;
429 }
430
431 return 0;
432 err_uninit_wakeup:
433 device_init_wakeup(&pdev->dev, false);
434 err_disable_irq:
435 rk_timer_rtc_irq_enable(rk_timer_rtc, false);
436 err_disable_clk:
437 clk_disable_unprepare(rk_timer_rtc->clk);
438 err_disable_pclk:
439 clk_disable_unprepare(rk_timer_rtc->pclk);
440 return ret;
441 }
442
rk_timer_rtc_remove(struct platform_device * pdev)443 static int rk_timer_rtc_remove(struct platform_device *pdev)
444 {
445 struct rk_timer_rtc *rk_timer_rtc = dev_get_drvdata(&pdev->dev);
446
447 device_init_wakeup(&pdev->dev, false);
448 rk_timer_rtc_irq_enable(rk_timer_rtc, false);
449 clk_disable_unprepare(rk_timer_rtc->clk);
450 clk_disable_unprepare(rk_timer_rtc->pclk);
451
452 return 0;
453 }
454
455 #ifdef CONFIG_PM_SLEEP
rk_timer_rtc_suspend(struct device * dev)456 static int rk_timer_rtc_suspend(struct device *dev)
457 {
458 struct rk_timer_rtc *rk_timer_rtc = dev_get_drvdata(dev);
459
460 if (device_may_wakeup(dev))
461 enable_irq_wake(rk_timer_rtc->irq);
462
463 return 0;
464 }
465
rk_timer_rtc_resume(struct device * dev)466 static int rk_timer_rtc_resume(struct device *dev)
467 {
468 struct rk_timer_rtc *rk_timer_rtc = dev_get_drvdata(dev);
469
470 if (device_may_wakeup(dev))
471 disable_irq_wake(rk_timer_rtc->irq);
472
473 return 0;
474 }
475 #endif
476
477 static SIMPLE_DEV_PM_OPS(rk_timer_rtc_pm_ops, rk_timer_rtc_suspend,
478 rk_timer_rtc_resume);
479
480 static const struct rk_timer_rtc_data rk3288_timer_rtc_data = {
481 .ctrl_reg_offset = TIMER_CONTROL_REG3288,
482 };
483
484 static const struct of_device_id rk_timer_rtc_dt_match[] = {
485 {
486 .compatible = "rockchip,rk3308-timer-rtc",
487 .data = &rk3288_timer_rtc_data,
488 },
489 { /* sentinel */ }
490 };
491 MODULE_DEVICE_TABLE(platform, rk_timer_rtc_dt_match);
492
493 static struct platform_driver rk_timer_rtc_driver = {
494 .probe = rk_timer_rtc_probe,
495 .remove = rk_timer_rtc_remove,
496 .driver = {
497 .name = DRV_NAME,
498 .pm = &rk_timer_rtc_pm_ops,
499 .of_match_table = of_match_ptr(rk_timer_rtc_dt_match),
500 },
501 };
502
503 module_platform_driver(rk_timer_rtc_driver);
504
505 MODULE_DESCRIPTION("RTC driver for the rockchip timer");
506 MODULE_AUTHOR("Jeffy Chen <jeffy.chen@rock-chips.com>");
507 MODULE_LICENSE("GPL v2");
508 MODULE_ALIAS("platform:" DRV_NAME);
509