1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun /* Copyright (c) 2018 Rockchip Electronics Co. Ltd. */ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #ifndef _SFC_NOR_H 6*4882a593Smuzhiyun #define _SFC_NOR_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include "sfc.h" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define NOR_PAGE_SIZE 256 11*4882a593Smuzhiyun #define NOR_BLOCK_SIZE (64 * 1024) 12*4882a593Smuzhiyun #define NOR_SECS_BLK (NOR_BLOCK_SIZE / 512) 13*4882a593Smuzhiyun #define NOR_SECS_PAGE 8 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define FEA_READ_STATUE_MASK (0x3 << 0) 16*4882a593Smuzhiyun #define FEA_STATUE_MODE1 0 17*4882a593Smuzhiyun #define FEA_STATUE_MODE2 1 18*4882a593Smuzhiyun #define FEA_4BIT_READ BIT(2) 19*4882a593Smuzhiyun #define FEA_4BIT_PROG BIT(3) 20*4882a593Smuzhiyun #define FEA_4BYTE_ADDR BIT(4) 21*4882a593Smuzhiyun #define FEA_4BYTE_ADDR_MODE BIT(5) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /*Command Set*/ 24*4882a593Smuzhiyun #define CMD_READ_JEDECID (0x9F) 25*4882a593Smuzhiyun #define CMD_READ_DATA (0x03) 26*4882a593Smuzhiyun #define CMD_READ_STATUS (0x05) 27*4882a593Smuzhiyun #define CMD_WRITE_STATUS (0x01) 28*4882a593Smuzhiyun #define CMD_PAGE_PROG (0x02) 29*4882a593Smuzhiyun #define CMD_SECTOR_ERASE (0x20) 30*4882a593Smuzhiyun #define CMD_BLK64K_ERASE (0xD8) 31*4882a593Smuzhiyun #define CMD_BLK32K_ERASE (0x52) 32*4882a593Smuzhiyun #define CMD_CHIP_ERASE (0xC7) 33*4882a593Smuzhiyun #define CMD_WRITE_EN (0x06) 34*4882a593Smuzhiyun #define CMD_WRITE_DIS (0x04) 35*4882a593Smuzhiyun #define CMD_PAGE_READ (0x13) 36*4882a593Smuzhiyun #define CMD_PAGE_FASTREAD4B (0x0C) 37*4882a593Smuzhiyun #define CMD_GET_FEATURE (0x0F) 38*4882a593Smuzhiyun #define CMD_SET_FEATURE (0x1F) 39*4882a593Smuzhiyun #define CMD_PROG_LOAD (0x02) 40*4882a593Smuzhiyun #define CMD_PROG_EXEC (0x10) 41*4882a593Smuzhiyun #define CMD_BLOCK_ERASE (0xD8) 42*4882a593Smuzhiyun #define CMD_READ_DATA_X2 (0x3B) 43*4882a593Smuzhiyun #define CMD_READ_DATA_X4 (0x6B) 44*4882a593Smuzhiyun #define CMD_PROG_LOAD_X4 (0x32) 45*4882a593Smuzhiyun #define CMD_READ_STATUS2 (0x35) 46*4882a593Smuzhiyun #define CMD_READ_STATUS3 (0x15) 47*4882a593Smuzhiyun #define CMD_WRITE_STATUS2 (0x31) 48*4882a593Smuzhiyun #define CMD_WRITE_STATUS3 (0x11) 49*4882a593Smuzhiyun /* X1 cmd, X1 addr, X1 data */ 50*4882a593Smuzhiyun #define CMD_FAST_READ_X1 (0x0B) 51*4882a593Smuzhiyun /* X1 cmd, X1 addr, X2 data */ 52*4882a593Smuzhiyun #define CMD_FAST_READ_X2 (0x3B) 53*4882a593Smuzhiyun /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */ 54*4882a593Smuzhiyun #define CMD_FAST_READ_X4 (0x6B) 55*4882a593Smuzhiyun /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */ 56*4882a593Smuzhiyun #define CMD_FAST_4READ_X4 (0x6C) 57*4882a593Smuzhiyun /* X1 cmd, X4 addr, X4 data SUPPORT EON GD MARCONIX WINBOND */ 58*4882a593Smuzhiyun #define CMD_FAST_READ_A4 (0xEB) 59*4882a593Smuzhiyun /* X1 cmd, X1 addr, X4 data, SUPPORT GD WINBOND */ 60*4882a593Smuzhiyun #define CMD_PAGE_PROG_X4 (0x32) 61*4882a593Smuzhiyun /* X1 cmd, X4 addr, X4 data, SUPPORT MARCONIX */ 62*4882a593Smuzhiyun #define CMD_PAGE_PROG_A4 (0x38) 63*4882a593Smuzhiyun /* X1 cmd, X4 addr, X4 data, SUPPORT MARCONIX */ 64*4882a593Smuzhiyun #define CMD_PAGE_PROG_4PP (0x3E) 65*4882a593Smuzhiyun #define CMD_RESET_NAND (0xFF) 66*4882a593Smuzhiyun #define CMD_ENTER_4BYTE_MODE (0xB7) 67*4882a593Smuzhiyun #define CMD_EXIT_4BYTE_MODE (0xE9) 68*4882a593Smuzhiyun #define CMD_ENABLE_RESER (0x66) 69*4882a593Smuzhiyun #define CMD_RESET_DEVICE (0x99) 70*4882a593Smuzhiyun #define CMD_READ_PARAMETER (0x5A) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun enum NOR_ERASE_TYPE { 73*4882a593Smuzhiyun ERASE_SECTOR = 0, 74*4882a593Smuzhiyun ERASE_BLOCK64K, 75*4882a593Smuzhiyun ERASE_CHIP 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun enum SNOR_IO_MODE { 79*4882a593Smuzhiyun IO_MODE_SPI = 0, 80*4882a593Smuzhiyun IO_MODE_QPI 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun enum SNOR_READ_MODE { 84*4882a593Smuzhiyun READ_MODE_NOMAL = 0, 85*4882a593Smuzhiyun READ_MODE_FAST 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun enum SNOR_ADDR_MODE { 89*4882a593Smuzhiyun ADDR_MODE_3BYTE = 0, 90*4882a593Smuzhiyun ADDR_MODE_4BYTE 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun typedef int (*SNOR_WRITE_STATUS)(u32 reg_index, u8 status); 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun struct SFNOR_DEV { 96*4882a593Smuzhiyun u32 capacity; 97*4882a593Smuzhiyun u8 manufacturer; 98*4882a593Smuzhiyun u8 mem_type; 99*4882a593Smuzhiyun u16 page_size; 100*4882a593Smuzhiyun u32 blk_size; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun u8 read_cmd; 103*4882a593Smuzhiyun u8 prog_cmd; 104*4882a593Smuzhiyun u8 sec_erase_cmd; 105*4882a593Smuzhiyun u8 blk_erase_cmd; 106*4882a593Smuzhiyun u8 QE_bits; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun enum SNOR_READ_MODE read_mode; 109*4882a593Smuzhiyun enum SNOR_ADDR_MODE addr_mode; 110*4882a593Smuzhiyun enum SNOR_IO_MODE io_mode; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun enum SFC_DATA_LINES read_lines; 113*4882a593Smuzhiyun enum SFC_DATA_LINES prog_lines; 114*4882a593Smuzhiyun enum SFC_DATA_LINES prog_addr_lines; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun SNOR_WRITE_STATUS write_status; 117*4882a593Smuzhiyun u32 max_iosize; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun struct flash_info { 121*4882a593Smuzhiyun u32 id; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun u8 block_size; 124*4882a593Smuzhiyun u8 sector_size; 125*4882a593Smuzhiyun u8 read_cmd; 126*4882a593Smuzhiyun u8 prog_cmd; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun u8 read_cmd_4; 129*4882a593Smuzhiyun u8 prog_cmd_4; 130*4882a593Smuzhiyun u8 sector_erase_cmd; 131*4882a593Smuzhiyun u8 block_erase_cmd; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun u8 feature; 134*4882a593Smuzhiyun u8 density; /* (1 << density) sectors*/ 135*4882a593Smuzhiyun u8 QE_bits; 136*4882a593Smuzhiyun u8 reserved2; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* flash table packet for easy boot */ 140*4882a593Smuzhiyun #define SNOR_INFO_PACKET_ID 0x464E494E 141*4882a593Smuzhiyun #define SNOR_INFO_PACKET_HEAD_LEN 14 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #define SNOR_INFO_PACKET_SPI_MODE_RATE_SHIFT 25 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun struct snor_info_packet { 146*4882a593Smuzhiyun u32 id; 147*4882a593Smuzhiyun u32 head_hash; /*hash for head, check by bootrom.*/ 148*4882a593Smuzhiyun u16 head_len; /*320 - 16 bytes*/ 149*4882a593Smuzhiyun u16 version; 150*4882a593Smuzhiyun u8 read_cmd; 151*4882a593Smuzhiyun u8 prog_cmd; 152*4882a593Smuzhiyun u8 read_cmd_4; 153*4882a593Smuzhiyun u8 prog_cmd_4; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun u8 sector_erase_cmd; 156*4882a593Smuzhiyun u8 block_erase_cmd; 157*4882a593Smuzhiyun u8 feature; 158*4882a593Smuzhiyun u8 QE_bits; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun u32 spi_mode; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun int snor_init(struct SFNOR_DEV *p_dev); 164*4882a593Smuzhiyun u32 snor_get_capacity(struct SFNOR_DEV *p_dev); 165*4882a593Smuzhiyun int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data); 166*4882a593Smuzhiyun int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data); 167*4882a593Smuzhiyun int snor_erase(struct SFNOR_DEV *p_dev, 168*4882a593Smuzhiyun u32 addr, 169*4882a593Smuzhiyun enum NOR_ERASE_TYPE erase_type); 170*4882a593Smuzhiyun int snor_read_id(u8 *data); 171*4882a593Smuzhiyun int snor_prog_page(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size); 172*4882a593Smuzhiyun int snor_read_data(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size); 173*4882a593Smuzhiyun int snor_reset_device(void); 174*4882a593Smuzhiyun int snor_disable_QE(struct SFNOR_DEV *p_dev); 175*4882a593Smuzhiyun int snor_reinit_from_table_packet(struct SFNOR_DEV *p_dev, 176*4882a593Smuzhiyun struct snor_info_packet *packet); 177*4882a593Smuzhiyun #endif 178