1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2018 Rockchip Electronics Co. Ltd. */ 4 5 #ifndef _SFC_NOR_H 6 #define _SFC_NOR_H 7 8 #include "sfc.h" 9 10 #define NOR_PAGE_SIZE 256 11 #define NOR_BLOCK_SIZE (64 * 1024) 12 #define NOR_SECS_BLK (NOR_BLOCK_SIZE / 512) 13 #define NOR_SECS_PAGE 8 14 15 #define FEA_READ_STATUE_MASK (0x3 << 0) 16 #define FEA_STATUE_MODE1 0 17 #define FEA_STATUE_MODE2 1 18 #define FEA_4BIT_READ BIT(2) 19 #define FEA_4BIT_PROG BIT(3) 20 #define FEA_4BYTE_ADDR BIT(4) 21 #define FEA_4BYTE_ADDR_MODE BIT(5) 22 23 /*Command Set*/ 24 #define CMD_READ_JEDECID (0x9F) 25 #define CMD_READ_DATA (0x03) 26 #define CMD_READ_STATUS (0x05) 27 #define CMD_WRITE_STATUS (0x01) 28 #define CMD_PAGE_PROG (0x02) 29 #define CMD_SECTOR_ERASE (0x20) 30 #define CMD_BLK64K_ERASE (0xD8) 31 #define CMD_BLK32K_ERASE (0x52) 32 #define CMD_CHIP_ERASE (0xC7) 33 #define CMD_WRITE_EN (0x06) 34 #define CMD_WRITE_DIS (0x04) 35 #define CMD_PAGE_READ (0x13) 36 #define CMD_PAGE_FASTREAD4B (0x0C) 37 #define CMD_GET_FEATURE (0x0F) 38 #define CMD_SET_FEATURE (0x1F) 39 #define CMD_PROG_LOAD (0x02) 40 #define CMD_PROG_EXEC (0x10) 41 #define CMD_BLOCK_ERASE (0xD8) 42 #define CMD_READ_DATA_X2 (0x3B) 43 #define CMD_READ_DATA_X4 (0x6B) 44 #define CMD_PROG_LOAD_X4 (0x32) 45 #define CMD_READ_STATUS2 (0x35) 46 #define CMD_READ_STATUS3 (0x15) 47 #define CMD_WRITE_STATUS2 (0x31) 48 #define CMD_WRITE_STATUS3 (0x11) 49 /* X1 cmd, X1 addr, X1 data */ 50 #define CMD_FAST_READ_X1 (0x0B) 51 /* X1 cmd, X1 addr, X2 data */ 52 #define CMD_FAST_READ_X2 (0x3B) 53 /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */ 54 #define CMD_FAST_READ_X4 (0x6B) 55 /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */ 56 #define CMD_FAST_4READ_X4 (0x6C) 57 /* X1 cmd, X4 addr, X4 data SUPPORT EON GD MARCONIX WINBOND */ 58 #define CMD_FAST_READ_A4 (0xEB) 59 /* X1 cmd, X1 addr, X4 data, SUPPORT GD WINBOND */ 60 #define CMD_PAGE_PROG_X4 (0x32) 61 /* X1 cmd, X4 addr, X4 data, SUPPORT MARCONIX */ 62 #define CMD_PAGE_PROG_A4 (0x38) 63 /* X1 cmd, X4 addr, X4 data, SUPPORT MARCONIX */ 64 #define CMD_PAGE_PROG_4PP (0x3E) 65 #define CMD_RESET_NAND (0xFF) 66 #define CMD_ENTER_4BYTE_MODE (0xB7) 67 #define CMD_EXIT_4BYTE_MODE (0xE9) 68 #define CMD_ENABLE_RESER (0x66) 69 #define CMD_RESET_DEVICE (0x99) 70 #define CMD_READ_PARAMETER (0x5A) 71 72 enum NOR_ERASE_TYPE { 73 ERASE_SECTOR = 0, 74 ERASE_BLOCK64K, 75 ERASE_CHIP 76 }; 77 78 enum SNOR_IO_MODE { 79 IO_MODE_SPI = 0, 80 IO_MODE_QPI 81 }; 82 83 enum SNOR_READ_MODE { 84 READ_MODE_NOMAL = 0, 85 READ_MODE_FAST 86 }; 87 88 enum SNOR_ADDR_MODE { 89 ADDR_MODE_3BYTE = 0, 90 ADDR_MODE_4BYTE 91 }; 92 93 typedef int (*SNOR_WRITE_STATUS)(u32 reg_index, u8 status); 94 95 struct SFNOR_DEV { 96 u32 capacity; 97 u8 manufacturer; 98 u8 mem_type; 99 u16 page_size; 100 u32 blk_size; 101 102 u8 read_cmd; 103 u8 prog_cmd; 104 u8 sec_erase_cmd; 105 u8 blk_erase_cmd; 106 u8 QE_bits; 107 108 enum SNOR_READ_MODE read_mode; 109 enum SNOR_ADDR_MODE addr_mode; 110 enum SNOR_IO_MODE io_mode; 111 112 enum SFC_DATA_LINES read_lines; 113 enum SFC_DATA_LINES prog_lines; 114 enum SFC_DATA_LINES prog_addr_lines; 115 116 SNOR_WRITE_STATUS write_status; 117 u32 max_iosize; 118 }; 119 120 struct flash_info { 121 u32 id; 122 123 u8 block_size; 124 u8 sector_size; 125 u8 read_cmd; 126 u8 prog_cmd; 127 128 u8 read_cmd_4; 129 u8 prog_cmd_4; 130 u8 sector_erase_cmd; 131 u8 block_erase_cmd; 132 133 u8 feature; 134 u8 density; /* (1 << density) sectors*/ 135 u8 QE_bits; 136 u8 reserved2; 137 }; 138 139 /* flash table packet for easy boot */ 140 #define SNOR_INFO_PACKET_ID 0x464E494E 141 #define SNOR_INFO_PACKET_HEAD_LEN 14 142 143 #define SNOR_INFO_PACKET_SPI_MODE_RATE_SHIFT 25 144 145 struct snor_info_packet { 146 u32 id; 147 u32 head_hash; /*hash for head, check by bootrom.*/ 148 u16 head_len; /*320 - 16 bytes*/ 149 u16 version; 150 u8 read_cmd; 151 u8 prog_cmd; 152 u8 read_cmd_4; 153 u8 prog_cmd_4; 154 155 u8 sector_erase_cmd; 156 u8 block_erase_cmd; 157 u8 feature; 158 u8 QE_bits; 159 160 u32 spi_mode; 161 }; 162 163 int snor_init(struct SFNOR_DEV *p_dev); 164 u32 snor_get_capacity(struct SFNOR_DEV *p_dev); 165 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data); 166 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data); 167 int snor_erase(struct SFNOR_DEV *p_dev, 168 u32 addr, 169 enum NOR_ERASE_TYPE erase_type); 170 int snor_read_id(u8 *data); 171 int snor_prog_page(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size); 172 int snor_read_data(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size); 173 int snor_reset_device(void); 174 int snor_disable_QE(struct SFNOR_DEV *p_dev); 175 int snor_reinit_from_table_packet(struct SFNOR_DEV *p_dev, 176 struct snor_info_packet *packet); 177 #endif 178