1 // SPDX-License-Identifier: GPL-2.0
2
3 /* Copyright (c) 2018 Rockchip Electronics Co. Ltd. */
4
5 #define pr_fmt(fmt) "sfc_nor: " fmt
6
7 #include <linux/bug.h>
8 #include <linux/delay.h>
9 #include <linux/kernel.h>
10 #include <asm/string.h>
11
12 #include "rkflash_debug.h"
13 #include "sfc_nor.h"
14
15 static struct flash_info spi_flash_tbl[] = {
16 /* GD25Q32B */
17 { 0xc84016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 },
18 /* GD25Q64B */
19 { 0xc84017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 },
20 /* GD25Q127C and GD25Q128C/E */
21 { 0xc84018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
22 /* GD25Q256B/C/D/E */
23 { 0xc84019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 16, 6, 0 },
24 /* GD25Q512MC */
25 { 0xc84020, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 17, 6, 0 },
26 /* GD25LQ64C */
27 { 0xc86017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 },
28 /* GD25LQ32E */
29 { 0xc86016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 },
30 /* GD25B512MEYIG */
31 { 0xc8471A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 17, 0, 0 },
32
33 /* W25Q32JV */
34 { 0xef4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 },
35 /* W25Q64JVSSIQ */
36 { 0xef4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
37 /* W25Q128FV and W25Q128JV*/
38 { 0xef4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
39 /* W25Q256F/J */
40 { 0xef4019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 },
41 /* W25Q32JW */
42 { 0xef6016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 },
43 /* W25Q64FWSSIG */
44 { 0xef6017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
45 /* W25Q128JWSQ */
46 { 0xef6018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
47 /* W25Q256JWEQ*/
48 { 0xef6019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 },
49 /* W25Q128JVSIM */
50 { 0xef7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
51 /* W25Q256JVEM */
52 { 0xef7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 9, 0 },
53
54 /* MX25L3233FM2I-08G */
55 { 0xc22016, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 13, 6, 0 },
56 /* MX25L6433F */
57 { 0xc22017, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 14, 6, 0 },
58 /* MX25L12835E/F MX25L12833FMI-10G */
59 { 0xc22018, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 15, 6, 0 },
60 /* MX25L25635E/F MX25L25645G MX25L25645GMI-08G */
61 { 0xc22019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 16, 6, 0 },
62 /* MX25L51245GMI */
63 { 0xc2201a, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 17, 6, 0 },
64 /* MX25U51245G */
65 { 0xc2253a, 128, 8, 0x0C, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 17, 6, 0 },
66 /* MX25U3232F */
67 { 0xc22536, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 13, 6, 0 },
68 /* MX25U6432F */
69 { 0xc22537, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 14, 6, 0 },
70 /* MX25U12832F */
71 { 0xc22538, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 15, 6, 0 },
72 /* MX25U25645GZ4I-00 */
73 { 0xc22539, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 16, 6, 0 },
74
75 /* XM25QH32C */
76 { 0x204016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 },
77 /* XM25QH64B */
78 { 0x206017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 6, 0 },
79 /* XM25QH128B */
80 { 0x206018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 6, 0 },
81 /* XM25QH(QU)256B */
82 { 0x206019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1D, 16, 6, 0 },
83 /* XM25QH64A */
84 { 0x207017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 },
85
86 /* XT25F128A XM25QH128A */
87 { 0x207018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 },
88 /* XT25F64BSSIGU-5 XT25F64F */
89 { 0x0b4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 },
90 /* XT25F128BSSIGU */
91 { 0x0b4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 },
92 /* XT25F256BSFIGU */
93 { 0x0b4019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 },
94 /* XT25F32BS */
95 { 0x0b4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 },
96 /* XT25F16BS */
97 { 0x0b4015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 },
98
99 /* EN25QH64A */
100 { 0x1c7017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 },
101 /* EN25QH128A */
102 { 0x1c7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 },
103 /* EN25QH32B */
104 { 0x1c7016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 },
105 /* EN25S32A */
106 { 0x1c3816, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 },
107 /* EN25S64A */
108 { 0x1c3817, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 },
109 /* EN25QH256A */
110 { 0x1c7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 0, 0 },
111
112 /* P25Q64H */
113 { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
114 /* P25Q128H */
115 { 0x856018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
116 /* P25Q16H-SUH-IT */
117 { 0x856015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 },
118 /* FM25Q64A */
119 { 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 },
120 /* FM25M64C */
121 { 0xf84317, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 },
122 /* P25Q32SL */
123 { 0x856016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 },
124
125 /* ZB25VQ64 */
126 { 0x5e4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
127 /* ZB25VQ128 */
128 { 0x5e4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
129 /* ZB25LQ128 */
130 { 0x5e5018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
131
132 /* BH25Q128AS */
133 { 0x684018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
134 /* BH25Q64BS */
135 { 0x684017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
136
137 /* P25Q64H */
138 { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
139 /* P25Q32SH-SSH-IT */
140 { 0x856016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 },
141
142 /* FM25Q128A */
143 { 0xA14018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
144 /* FM25Q64-SOB-T-G */
145 { 0xA14017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
146
147 /* FM25Q64A */
148 { 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 },
149 /* FM25M4AA */
150 { 0xf84218, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 },
151 /* DS25M4AB-1AIB4 */
152 { 0xe54218, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
153
154 /* GM25Q128A */
155 { 0x1c4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
156 };
157
snor_write_en(void)158 static int snor_write_en(void)
159 {
160 int ret;
161 struct rk_sfc_op op;
162
163 op.sfcmd.d32 = 0;
164 op.sfcmd.b.cmd = CMD_WRITE_EN;
165
166 op.sfctrl.d32 = 0;
167
168 ret = sfc_request(&op, 0, NULL, 0);
169
170 return ret;
171 }
172
snor_reset_device(void)173 int snor_reset_device(void)
174 {
175 struct rk_sfc_op op;
176
177 op.sfcmd.d32 = 0;
178 op.sfcmd.b.cmd = CMD_ENABLE_RESER;
179
180 op.sfctrl.d32 = 0;
181 sfc_request(&op, 0, NULL, 0);
182
183 op.sfcmd.d32 = 0;
184 op.sfcmd.b.cmd = CMD_RESET_DEVICE;
185
186 op.sfctrl.d32 = 0;
187 sfc_request(&op, 0, NULL, 0);
188 /* tRST=30us , delay 1ms here */
189 sfc_delay(1000);
190
191 return SFC_OK;
192 }
193
snor_enter_4byte_mode(void)194 static int snor_enter_4byte_mode(void)
195 {
196 int ret;
197 struct rk_sfc_op op;
198
199 op.sfcmd.d32 = 0;
200 op.sfcmd.b.cmd = CMD_ENTER_4BYTE_MODE;
201
202 op.sfctrl.d32 = 0;
203
204 ret = sfc_request(&op, 0, NULL, 0);
205 return ret;
206 }
207
snor_read_status(u32 reg_index,u8 * status)208 static int snor_read_status(u32 reg_index, u8 *status)
209 {
210 int ret;
211 struct rk_sfc_op op;
212 u8 read_stat_cmd[] = {CMD_READ_STATUS,
213 CMD_READ_STATUS2, CMD_READ_STATUS3};
214 op.sfcmd.d32 = 0;
215 op.sfcmd.b.cmd = read_stat_cmd[reg_index];
216
217 op.sfctrl.d32 = 0;
218 ret = sfc_request(&op, 0, status, 1);
219
220 return ret;
221 }
222
snor_wait_busy(int timeout)223 static int snor_wait_busy(int timeout)
224 {
225 int ret;
226 struct rk_sfc_op op;
227 int i;
228 u32 status;
229
230 op.sfcmd.d32 = 0;
231 op.sfcmd.b.cmd = CMD_READ_STATUS;
232
233 op.sfctrl.d32 = 0;
234
235 for (i = 0; i < timeout; i++) {
236 ret = sfc_request(&op, 0, &status, 1);
237 if (ret != SFC_OK)
238 return ret;
239
240 if ((status & 0x01) == 0)
241 return SFC_OK;
242
243 sfc_delay(1);
244 }
245 rkflash_print_error("%s error %x\n", __func__, timeout);
246
247 return SFC_BUSY_TIMEOUT;
248 }
249
snor_write_status2(u32 reg_index,u8 status)250 static int snor_write_status2(u32 reg_index, u8 status)
251 {
252 int ret;
253 struct rk_sfc_op op;
254 u8 status2[2];
255
256 status2[reg_index] = status;
257 if (reg_index == 0)
258 ret = snor_read_status(2, &status2[1]);
259 else
260 ret = snor_read_status(0, &status2[0]);
261 if (ret != SFC_OK)
262 return ret;
263
264 snor_write_en();
265
266 op.sfcmd.d32 = 0;
267 op.sfcmd.b.cmd = CMD_WRITE_STATUS;
268 op.sfcmd.b.rw = SFC_WRITE;
269
270 op.sfctrl.d32 = 0;
271
272 ret = sfc_request(&op, 0, &status2[0], 2);
273 if (ret != SFC_OK)
274 return ret;
275
276 ret = snor_wait_busy(10000); /* 10ms */
277
278 return ret;
279 }
280
snor_write_status1(u32 reg_index,u8 status)281 static int snor_write_status1(u32 reg_index, u8 status)
282 {
283 int ret;
284 struct rk_sfc_op op;
285 u8 status2[2];
286 u8 read_index;
287
288 status2[reg_index] = status;
289 read_index = (reg_index == 0) ? 1 : 0;
290 ret = snor_read_status(read_index, &status2[read_index]);
291 if (ret != SFC_OK)
292 return ret;
293
294 snor_write_en();
295
296 op.sfcmd.d32 = 0;
297 op.sfcmd.b.cmd = CMD_WRITE_STATUS;
298 op.sfcmd.b.rw = SFC_WRITE;
299
300 op.sfctrl.d32 = 0;
301
302 ret = sfc_request(&op, 0, &status2[0], 2);
303 if (ret != SFC_OK)
304 return ret;
305
306 ret = snor_wait_busy(10000); /* 10ms */
307
308 return ret;
309 }
310
snor_write_status(u32 reg_index,u8 status)311 static int snor_write_status(u32 reg_index, u8 status)
312 {
313 int ret;
314 struct rk_sfc_op op;
315 u8 write_stat_cmd[] = {CMD_WRITE_STATUS,
316 CMD_WRITE_STATUS2, CMD_WRITE_STATUS3};
317 snor_write_en();
318 op.sfcmd.d32 = 0;
319 op.sfcmd.b.cmd = write_stat_cmd[reg_index];
320 op.sfcmd.b.rw = SFC_WRITE;
321
322 op.sfctrl.d32 = 0;
323
324 ret = sfc_request(&op, 0, &status, 1);
325 if (ret != SFC_OK)
326 return ret;
327
328 ret = snor_wait_busy(10000); /* 10ms */
329
330 return ret;
331 }
332
snor_erase(struct SFNOR_DEV * p_dev,u32 addr,enum NOR_ERASE_TYPE erase_type)333 int snor_erase(struct SFNOR_DEV *p_dev,
334 u32 addr,
335 enum NOR_ERASE_TYPE erase_type)
336 {
337 int ret;
338 struct rk_sfc_op op;
339 int timeout[] = {400, 2000, 40000}; /* ms */
340
341 rkflash_print_dio("%s %x %x\n", __func__, addr, erase_type);
342
343 if (erase_type > ERASE_CHIP)
344 return SFC_PARAM_ERR;
345
346 op.sfcmd.d32 = 0;
347 if (erase_type == ERASE_BLOCK64K)
348 op.sfcmd.b.cmd = p_dev->blk_erase_cmd;
349 else if (erase_type == ERASE_SECTOR)
350 op.sfcmd.b.cmd = p_dev->sec_erase_cmd;
351 else
352 op.sfcmd.b.cmd = CMD_CHIP_ERASE;
353
354 op.sfcmd.b.addrbits = (erase_type != ERASE_CHIP) ?
355 SFC_ADDR_24BITS : SFC_ADDR_0BITS;
356 if (p_dev->addr_mode == ADDR_MODE_4BYTE && erase_type != ERASE_CHIP)
357 op.sfcmd.b.addrbits = SFC_ADDR_32BITS;
358 op.sfcmd.b.rw = SFC_WRITE;
359
360 op.sfctrl.d32 = 0;
361
362 snor_write_en();
363
364 ret = sfc_request(&op, addr, NULL, 0);
365 if (ret != SFC_OK)
366 return ret;
367
368 ret = snor_wait_busy(timeout[erase_type] * 1000);
369 return ret;
370 }
371
snor_prog_page(struct SFNOR_DEV * p_dev,u32 addr,void * p_data,u32 size)372 int snor_prog_page(struct SFNOR_DEV *p_dev,
373 u32 addr,
374 void *p_data,
375 u32 size)
376 {
377 int ret;
378 struct rk_sfc_op op;
379
380 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data));
381
382 op.sfcmd.d32 = 0;
383 op.sfcmd.b.cmd = p_dev->prog_cmd;
384 op.sfcmd.b.addrbits = SFC_ADDR_24BITS;
385 op.sfcmd.b.rw = SFC_WRITE;
386
387 op.sfctrl.d32 = 0;
388 op.sfctrl.b.datalines = p_dev->prog_lines;
389 op.sfctrl.b.enbledma = 1;
390 op.sfctrl.b.addrlines = p_dev->prog_addr_lines;
391
392 if (p_dev->addr_mode == ADDR_MODE_4BYTE)
393 op.sfcmd.b.addrbits = SFC_ADDR_32BITS;
394
395 snor_write_en();
396
397 ret = sfc_request(&op, addr, p_data, size);
398 if (ret != SFC_OK)
399 return ret;
400
401 ret = snor_wait_busy(10000);
402
403 return ret;
404 }
405
snor_prog(struct SFNOR_DEV * p_dev,u32 addr,void * p_data,u32 size)406 static int snor_prog(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size)
407 {
408 int ret = SFC_OK;
409 u32 page_size, len;
410 u8 *p_buf = (u8 *)p_data;
411
412 page_size = NOR_PAGE_SIZE;
413 while (size) {
414 len = page_size < size ? page_size : size;
415 ret = snor_prog_page(p_dev, addr, p_buf, len);
416 if (ret != SFC_OK)
417 return ret;
418
419 size -= len;
420 addr += len;
421 p_buf += len;
422 }
423
424 return ret;
425 }
426
snor_enable_QE(struct SFNOR_DEV * p_dev)427 static int snor_enable_QE(struct SFNOR_DEV *p_dev)
428 {
429 int ret = SFC_OK;
430 int reg_index;
431 int bit_offset;
432 u8 status;
433
434 reg_index = p_dev->QE_bits >> 3;
435 bit_offset = p_dev->QE_bits & 0x7;
436 ret = snor_read_status(reg_index, &status);
437 if (ret != SFC_OK)
438 return ret;
439
440 if (status & (1 << bit_offset)) /* is QE bit set */
441 return SFC_OK;
442
443 status |= (1 << bit_offset);
444
445 return p_dev->write_status(reg_index, status);
446 }
447
snor_disable_QE(struct SFNOR_DEV * p_dev)448 int snor_disable_QE(struct SFNOR_DEV *p_dev)
449 {
450 int ret = SFC_OK;
451 int reg_index;
452 int bit_offset;
453 u8 status;
454
455 reg_index = p_dev->QE_bits >> 3;
456 bit_offset = p_dev->QE_bits & 0x7;
457 ret = snor_read_status(reg_index, &status);
458 if (ret != SFC_OK)
459 return ret;
460
461 if (!(status & (1 << bit_offset)))
462 return SFC_OK;
463
464 status &= ~(1 << bit_offset);
465
466 return p_dev->write_status(reg_index, status);
467 }
468
snor_read_data(struct SFNOR_DEV * p_dev,u32 addr,void * p_data,u32 size)469 int snor_read_data(struct SFNOR_DEV *p_dev,
470 u32 addr,
471 void *p_data,
472 u32 size)
473 {
474 int ret;
475 struct rk_sfc_op op;
476
477 op.sfcmd.d32 = 0;
478 op.sfcmd.b.cmd = p_dev->read_cmd;
479 op.sfcmd.b.addrbits = SFC_ADDR_24BITS;
480
481 op.sfctrl.d32 = 0;
482 op.sfctrl.b.datalines = p_dev->read_lines;
483 if (!(size & 0x3) && size >= 4)
484 op.sfctrl.b.enbledma = 1;
485
486 if (p_dev->read_cmd == CMD_FAST_READ_X1 ||
487 p_dev->read_cmd == CMD_PAGE_FASTREAD4B ||
488 p_dev->read_cmd == CMD_FAST_READ_X4 ||
489 p_dev->read_cmd == CMD_FAST_READ_X2 ||
490 p_dev->read_cmd == CMD_FAST_4READ_X4) {
491 op.sfcmd.b.dummybits = 8;
492 } else if (p_dev->read_cmd == CMD_FAST_READ_A4) {
493 op.sfcmd.b.addrbits = SFC_ADDR_32BITS;
494 addr = (addr << 8) | 0xFF; /* Set M[7:0] = 0xFF */
495 op.sfcmd.b.dummybits = 4;
496 op.sfctrl.b.addrlines = SFC_4BITS_LINE;
497 }
498
499 if (p_dev->addr_mode == ADDR_MODE_4BYTE)
500 op.sfcmd.b.addrbits = SFC_ADDR_32BITS;
501
502 ret = sfc_request(&op, addr, p_data, size);
503 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data));
504
505 return ret;
506 }
507
snor_read(struct SFNOR_DEV * p_dev,u32 sec,u32 n_sec,void * p_data)508 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data)
509 {
510 int ret = SFC_OK;
511 u32 addr, size, len;
512 u8 *p_buf = (u8 *)p_data;
513
514 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec);
515
516 if ((sec + n_sec) > p_dev->capacity)
517 return SFC_PARAM_ERR;
518
519 addr = sec << 9;
520 size = n_sec << 9;
521 while (size) {
522 len = size < p_dev->max_iosize ? size : p_dev->max_iosize;
523 ret = snor_read_data(p_dev, addr, p_buf, len);
524 if (ret != SFC_OK) {
525 rkflash_print_error("snor_read_data %x ret= %x\n",
526 addr >> 9, ret);
527 goto out;
528 }
529
530 size -= len;
531 addr += len;
532 p_buf += len;
533 }
534 out:
535 if (!ret)
536 ret = n_sec;
537
538 return ret;
539 }
540
snor_write(struct SFNOR_DEV * p_dev,u32 sec,u32 n_sec,void * p_data)541 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data)
542 {
543 int ret = SFC_OK;
544 u32 len, blk_size, offset;
545 u8 *p_buf = (u8 *)p_data;
546 u32 total_sec = n_sec;
547
548 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec);
549
550 if ((sec + n_sec) > p_dev->capacity)
551 return SFC_PARAM_ERR;
552
553 while (n_sec) {
554 if (sec < 512 || sec >= p_dev->capacity - 512)
555 blk_size = 8;
556 else
557 blk_size = p_dev->blk_size;
558
559 offset = (sec & (blk_size - 1));
560 if (!offset) {
561 ret = snor_erase(p_dev, sec << 9, (blk_size == 8) ?
562 ERASE_SECTOR : ERASE_BLOCK64K);
563 if (ret != SFC_OK) {
564 rkflash_print_error("snor_erase %x ret= %x\n",
565 sec, ret);
566 goto out;
567 }
568 }
569 len = (blk_size - offset) < n_sec ?
570 (blk_size - offset) : n_sec;
571 ret = snor_prog(p_dev, sec << 9, p_buf, len << 9);
572 if (ret != SFC_OK) {
573 rkflash_print_error("snor_prog %x ret= %x\n", sec, ret);
574 goto out;
575 }
576 n_sec -= len;
577 sec += len;
578 p_buf += len << 9;
579 }
580 out:
581 if (!ret)
582 ret = total_sec;
583
584 return ret;
585 }
586
snor_read_id(u8 * data)587 int snor_read_id(u8 *data)
588 {
589 int ret;
590 struct rk_sfc_op op;
591
592 op.sfcmd.d32 = 0;
593 op.sfcmd.b.cmd = CMD_READ_JEDECID;
594
595 op.sfctrl.d32 = 0;
596
597 ret = sfc_request(&op, 0, data, 3);
598
599 return ret;
600 }
601
snor_read_parameter(u32 addr,u8 * data)602 static int snor_read_parameter(u32 addr, u8 *data)
603 {
604 int ret;
605 struct rk_sfc_op op;
606
607 op.sfcmd.d32 = 0;
608 op.sfcmd.b.cmd = CMD_READ_PARAMETER;
609 op.sfcmd.b.addrbits = SFC_ADDR_24BITS;
610 op.sfcmd.b.dummybits = 8;
611
612 op.sfctrl.d32 = 0;
613
614 ret = sfc_request(&op, addr, data, 1);
615
616 return ret;
617 }
618
snor_get_capacity(struct SFNOR_DEV * p_dev)619 u32 snor_get_capacity(struct SFNOR_DEV *p_dev)
620 {
621 return p_dev->capacity;
622 }
623
snor_get_flash_info(u8 * flash_id)624 static struct flash_info *snor_get_flash_info(u8 *flash_id)
625 {
626 u32 i;
627 u32 id = (flash_id[0] << 16) | (flash_id[1] << 8) | (flash_id[2] << 0);
628
629 for (i = 0; i < ARRAY_SIZE(spi_flash_tbl); i++) {
630 if (spi_flash_tbl[i].id == id)
631 return &spi_flash_tbl[i];
632 }
633 return NULL;
634 }
635
636 /* Adjust flash info in ram base on parameter */
snor_flash_info_adjust(struct flash_info * spi_flash_info)637 static void *snor_flash_info_adjust(struct flash_info *spi_flash_info)
638 {
639 u32 addr;
640 u8 para_version;
641
642 if (spi_flash_info->id == 0xc84019) {
643 addr = 0x09;
644 snor_read_parameter(addr, ¶_version);
645 if (para_version == 0x06) {
646 spi_flash_info->QE_bits = 9;
647 spi_flash_info->prog_cmd_4 = 0x34;
648 }
649 }
650 return 0;
651 }
652
snor_parse_flash_table(struct SFNOR_DEV * p_dev,struct flash_info * g_spi_flash_info)653 static int snor_parse_flash_table(struct SFNOR_DEV *p_dev,
654 struct flash_info *g_spi_flash_info)
655 {
656 int i, ret;
657
658 if (g_spi_flash_info) {
659 snor_flash_info_adjust(g_spi_flash_info);
660 p_dev->manufacturer = (g_spi_flash_info->id >> 16) & 0xFF;
661 p_dev->mem_type = (g_spi_flash_info->id >> 8) & 0xFF;
662 p_dev->capacity = 1 << g_spi_flash_info->density;
663 p_dev->blk_size = g_spi_flash_info->block_size;
664 p_dev->page_size = NOR_SECS_PAGE;
665 p_dev->read_cmd = g_spi_flash_info->read_cmd;
666 p_dev->prog_cmd = g_spi_flash_info->prog_cmd;
667 p_dev->sec_erase_cmd = g_spi_flash_info->sector_erase_cmd;
668 p_dev->blk_erase_cmd = g_spi_flash_info->block_erase_cmd;
669 p_dev->prog_lines = DATA_LINES_X1;
670 p_dev->read_lines = DATA_LINES_X1;
671 p_dev->QE_bits = g_spi_flash_info->QE_bits;
672 p_dev->addr_mode = ADDR_MODE_3BYTE;
673
674 i = g_spi_flash_info->feature & FEA_READ_STATUE_MASK;
675 if (i == 0)
676 p_dev->write_status = snor_write_status;
677 else if (i == 1)
678 p_dev->write_status = snor_write_status1;
679 else if (i == 2)
680 p_dev->write_status = snor_write_status2;
681
682 if (g_spi_flash_info->feature & FEA_4BIT_READ) {
683 ret = SFC_OK;
684 if (g_spi_flash_info->QE_bits)
685 ret = snor_enable_QE(p_dev);
686 if (ret == SFC_OK) {
687 p_dev->read_lines = DATA_LINES_X4;
688 p_dev->read_cmd = g_spi_flash_info->read_cmd_4;
689 }
690 }
691 if (g_spi_flash_info->feature & FEA_4BIT_PROG &&
692 p_dev->read_lines == DATA_LINES_X4) {
693 p_dev->prog_lines = DATA_LINES_X4;
694 p_dev->prog_cmd = g_spi_flash_info->prog_cmd_4;
695 if ((p_dev->manufacturer == MID_MACRONIX) &&
696 (p_dev->prog_cmd == CMD_PAGE_PROG_A4 ||
697 p_dev->prog_cmd == CMD_PAGE_PROG_4PP))
698 p_dev->prog_addr_lines = DATA_LINES_X4;
699 }
700
701 if (g_spi_flash_info->feature & FEA_4BYTE_ADDR)
702 p_dev->addr_mode = ADDR_MODE_4BYTE;
703
704 if ((g_spi_flash_info->feature & FEA_4BYTE_ADDR_MODE))
705 snor_enter_4byte_mode();
706 }
707
708 return SFC_OK;
709 }
710
snor_init(struct SFNOR_DEV * p_dev)711 int snor_init(struct SFNOR_DEV *p_dev)
712 {
713 struct flash_info *g_spi_flash_info;
714 u8 id_byte[5];
715
716 if (!p_dev)
717 return SFC_PARAM_ERR;
718
719 memset((void *)p_dev, 0, sizeof(struct SFNOR_DEV));
720 p_dev->max_iosize = sfc_get_max_iosize();
721
722 snor_read_id(id_byte);
723 rkflash_print_error("sfc nor id: %x %x %x\n",
724 id_byte[0], id_byte[1], id_byte[2]);
725 if (0xFF == id_byte[0] || 0x00 == id_byte[0])
726 return SFC_ERROR;
727
728 g_spi_flash_info = snor_get_flash_info(id_byte);
729 if (g_spi_flash_info) {
730 snor_parse_flash_table(p_dev, g_spi_flash_info);
731 } else {
732 pr_err("The device not support yet!\n");
733
734 p_dev->manufacturer = id_byte[0];
735 p_dev->mem_type = id_byte[1];
736 p_dev->capacity = 1 << (id_byte[2] - 9);
737 p_dev->QE_bits = 0;
738 p_dev->blk_size = NOR_SECS_BLK;
739 p_dev->page_size = NOR_SECS_PAGE;
740 p_dev->read_cmd = CMD_READ_DATA;
741 p_dev->prog_cmd = CMD_PAGE_PROG;
742 p_dev->sec_erase_cmd = CMD_SECTOR_ERASE;
743 p_dev->blk_erase_cmd = CMD_BLOCK_ERASE;
744 p_dev->prog_lines = DATA_LINES_X1;
745 p_dev->prog_addr_lines = DATA_LINES_X1;
746 p_dev->read_lines = DATA_LINES_X1;
747 p_dev->write_status = snor_write_status;
748 snor_reset_device();
749 }
750
751 rkflash_print_info("addr_mode: %x\n", p_dev->addr_mode);
752 rkflash_print_info("read_lines: %x\n", p_dev->read_lines);
753 rkflash_print_info("prog_lines: %x\n", p_dev->prog_lines);
754 rkflash_print_info("read_cmd: %x\n", p_dev->read_cmd);
755 rkflash_print_info("prog_cmd: %x\n", p_dev->prog_cmd);
756 rkflash_print_info("blk_erase_cmd: %x\n", p_dev->blk_erase_cmd);
757 rkflash_print_info("sec_erase_cmd: %x\n", p_dev->sec_erase_cmd);
758 rkflash_print_info("capacity: %x\n", p_dev->capacity);
759
760 return SFC_OK;
761 }
762
snor_reinit_from_table_packet(struct SFNOR_DEV * p_dev,struct snor_info_packet * packet)763 int snor_reinit_from_table_packet(struct SFNOR_DEV *p_dev,
764 struct snor_info_packet *packet)
765 {
766 struct flash_info g_spi_flash_info;
767 u8 id_byte[5];
768 int ret;
769
770 if (!p_dev || packet->id != SNOR_INFO_PACKET_ID)
771 return SFC_PARAM_ERR;
772
773 snor_read_id(id_byte);
774 if (0xFF == id_byte[0] || 0x00 == id_byte[0])
775 return SFC_ERROR;
776
777 g_spi_flash_info.id = id_byte[0] << 16 | id_byte[1] << 8 | id_byte[2];
778 g_spi_flash_info.block_size = NOR_SECS_BLK;
779 g_spi_flash_info.sector_size = NOR_SECS_PAGE;
780 g_spi_flash_info.read_cmd = packet->read_cmd;
781 g_spi_flash_info.prog_cmd = packet->prog_cmd;
782 g_spi_flash_info.read_cmd_4 = packet->read_cmd_4;
783 g_spi_flash_info.prog_cmd_4 = packet->prog_cmd_4;
784 if (id_byte[2] >= 0x19)
785 g_spi_flash_info.read_cmd_4 = CMD_FAST_4READ_X4;
786 g_spi_flash_info.sector_erase_cmd = packet->sector_erase_cmd;
787 g_spi_flash_info.block_erase_cmd = packet->block_erase_cmd;
788 g_spi_flash_info.feature = packet->feature;
789 g_spi_flash_info.density = id_byte[2] - 9;
790 g_spi_flash_info.QE_bits = packet->QE_bits;
791
792 ret = snor_parse_flash_table(p_dev, &g_spi_flash_info);
793
794 return ret;
795 }
796
797