1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2018 Rockchip Electronics Co. Ltd. */ 4 5 #ifndef __SFC_NAND_H 6 #define __SFC_NAND_H 7 8 #include "flash_com.h" 9 #include "sfc.h" 10 11 #define SFC_NAND_WAIT_TIME_OUT 3 12 #define SFC_NAND_PROG_ERASE_ERROR 2 13 #define SFC_NAND_HW_ERROR 1 14 #define SFC_NAND_ECC_ERROR NAND_ERROR 15 #define SFC_NAND_ECC_REFRESH NAND_STS_REFRESH 16 #define SFC_NAND_ECC_OK NAND_STS_OK 17 18 #define SFC_NAND_PAGE_MAX_SIZE 4224 19 #define SFC_NAND_SECTOR_FULL_SIZE 528 20 #define SFC_NAND_SECTOR_SIZE 512 21 22 #define FEA_READ_STATUE_MASK (0x3 << 0) 23 #define FEA_STATUE_MODE1 0 24 #define FEA_STATUE_MODE2 1 25 #define FEA_4BIT_READ BIT(2) 26 #define FEA_4BIT_PROG BIT(3) 27 #define FEA_4BYTE_ADDR BIT(4) 28 #define FEA_4BYTE_ADDR_MODE BIT(5) 29 #define FEA_SOFT_QOP_BIT BIT(6) 30 31 /* Command Set */ 32 #define CMD_READ_JEDECID (0x9F) 33 #define CMD_READ_DATA (0x03) 34 #define CMD_READ_STATUS (0x05) 35 #define CMD_WRITE_STATUS (0x01) 36 #define CMD_PAGE_PROG (0x02) 37 #define CMD_SECTOR_ERASE (0x20) 38 #define CMD_BLK64K_ERASE (0xD8) 39 #define CMD_BLK32K_ERASE (0x52) 40 #define CMD_CHIP_ERASE (0xC7) 41 #define CMD_WRITE_EN (0x06) 42 #define CMD_WRITE_DIS (0x04) 43 #define CMD_PAGE_READ (0x13) 44 #define CMD_GET_FEATURE (0x0F) 45 #define CMD_SET_FEATURE (0x1F) 46 #define CMD_PROG_LOAD (0x02) 47 #define CMD_PROG_EXEC (0x10) 48 #define CMD_BLOCK_ERASE (0xD8) 49 #define CMD_READ_DATA_X2 (0x3B) 50 #define CMD_READ_DATA_X4 (0x6B) 51 #define CMD_PROG_LOAD_X4 (0x32) 52 #define CMD_READ_STATUS2 (0x35) 53 #define CMD_READ_STATUS3 (0x15) 54 #define CMD_WRITE_STATUS2 (0x31) 55 #define CMD_WRITE_STATUS3 (0x11) 56 #define CMD_FAST_READ_X1 (0x0B) /* X1 cmd, X1 addr, X1 data */ 57 #define CMD_FAST_READ_X2 (0x3B) /* X1 cmd, X1 addr, X2 data */ 58 /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */ 59 #define CMD_FAST_READ_X4 (0x6B) 60 /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */ 61 #define CMD_FAST_4READ_X4 (0x6C) 62 /* X1 cmd, X4 addr, X4 data SUPPORT EON GD MARCONIX WINBOND */ 63 #define CMD_FAST_READ_A4 (0xEB) 64 /* X1 cmd, X1 addr, X4 data, SUPPORT GD WINBOND */ 65 #define CMD_PAGE_PROG_X4 (0x32) 66 /* X1 cmd, X4 addr, X4 data, SUPPORT MARCONIX */ 67 #define CMD_PAGE_PROG_A4 (0x38) 68 #define CMD_RESET_NAND (0xFF) 69 70 #define CMD_ENTER_4BYTE_MODE (0xB7) 71 #define CMD_EXIT_4BYTE_MODE (0xE9) 72 #define CMD_ENABLE_RESER (0x66) 73 #define CMD_RESET_DEVICE (0x99) 74 75 struct SFNAND_DEV { 76 u32 capacity; 77 u32 block_size; 78 u16 page_size; 79 u8 manufacturer; 80 u8 mem_type; 81 u8 read_lines; 82 u8 prog_lines; 83 u8 page_read_cmd; 84 u8 page_prog_cmd; 85 u8 *recheck_buffer; 86 }; 87 88 struct nand_mega_area { 89 u8 off0; 90 u8 off1; 91 u8 off2; 92 u8 off3; 93 }; 94 95 struct nand_info { 96 u8 id0; 97 u8 id1; 98 u8 id2; 99 100 u16 sec_per_page; 101 u16 page_per_blk; 102 u16 plane_per_die; 103 u16 blk_per_plane; 104 105 u8 feature; 106 107 u8 density; /* (1 << density) sectors*/ 108 u8 max_ecc_bits; 109 u8 has_qe_bits; 110 111 struct nand_mega_area meta; 112 u32 (*ecc_status)(void); 113 }; 114 115 extern struct nand_phy_info g_nand_phy_info; 116 extern struct nand_ops g_nand_ops; 117 118 u32 sfc_nand_init(void); 119 void sfc_nand_deinit(void); 120 int sfc_nand_read_id(u8 *buf); 121 u32 sfc_nand_erase_block(u8 cs, u32 addr); 122 u32 sfc_nand_prog_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare); 123 u32 sfc_nand_read_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare); 124 u32 sfc_nand_prog_page_raw(u8 cs, u32 addr, u32 *p_page_buf); 125 u32 sfc_nand_read_page_raw(u8 cs, u32 addr, u32 *p_page_buf); 126 u32 sfc_nand_check_bad_block(u8 cs, u32 addr); 127 u32 sfc_nand_mark_bad_block(u8 cs, u32 addr); 128 void sfc_nand_ftl_ops_init(void); 129 struct SFNAND_DEV *sfc_nand_get_private_dev(void); 130 struct nand_info *sfc_nand_get_nand_info(void); 131 u32 sfc_nand_read(u32 row, u32 *p_page_buf, u32 column, u32 len); 132 133 #endif 134