1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2018 Rockchip Electronics Co. Ltd. */ 4 5 #ifndef __FLASH_H 6 #define __FLASH_H 7 8 #ifndef BIT 9 #define BIT(nr) (1 << (nr)) 10 #endif 11 12 #define MAX_FLASH_NUM 2 13 #define MAX_IDB_RESERVED_BLOCK 12 14 15 #define NAND_CACHE_READ_EN BIT(0) 16 #define NAND_CACHE_RANDOM_READ_EN BIT(1) 17 #define NAND_CACHE_PROG_EN BIT(2) 18 #define NAND_MULTI_READ_EN BIT(3) 19 20 #define NAND_MULTI_PROG_EN BIT(4) 21 #define NAND_INTERLEAVE_EN BIT(5) 22 #define NAND_READ_RETRY_EN BIT(6) 23 #define NAND_RANDOMIZER_EN BIT(7) 24 25 #define NAND_INTER_MODE_OFFSET (0x8) 26 #define NAND_INTER_MODE_MARK (0x07) 27 #define NAND_INTER_SDR_EN BIT(0) 28 #define NAND_INTER_ONFI_EN BIT(1) 29 #define NAND_INTER_TOGGLE_EN BIT(2) 30 31 #define NAND_SDR_EN BIT(8) 32 #define NAND_ONFI_EN BIT(9) 33 #define NAND_TOGGLE_EN BIT(10) 34 #define NAND_UNIQUE_ID_EN BIT(11) 35 36 #define RESET_CMD 0xff 37 #define READ_ID_CMD 0x90 38 #define READ_STATUS_CMD 0x70 39 #define PAGE_PROG_CMD 0x8010 40 #define BLOCK_ERASE_CMD 0x60d0 41 #define READ_CMD 0x0030 42 #define READ_DP_OUT_CMD 0x05E0 43 #define READ_ECC_STATUS_CMD 0x7A 44 45 #define SAMSUNG 0x00 /* SAMSUNG */ 46 #define TOSHIBA 0x01 /* TOSHIBA */ 47 #define HYNIX 0x02 /* HYNIX */ 48 #define INFINEON 0x03 /* INFINEON */ 49 #define MICRON 0x04 /* MICRON */ 50 #define RENESAS 0x05 /* RENESAS */ 51 #define ST 0x06 /* ST */ 52 #define INTEL 0x07 /* intel */ 53 #define Sandisk 0x08 /* Sandisk */ 54 55 #define RR_NONE 0x00 56 #define RR_HY_1 0x01 /* hynix H27UCG8T2M */ 57 #define RR_HY_2 0x02 /* hynix H27UBG08U0B */ 58 #define RR_HY_3 0x03 /* hynix H27UCG08U0B H27UBG08U0C */ 59 #define RR_HY_4 0x04 /* hynix H27UCG8T2A */ 60 #define RR_HY_5 0x05 /* hynix H27UCG8T2E */ 61 #define RR_HY_6 0x06 /* hynix H27QCG8T2F5R-BCG */ 62 #define RR_MT_1 0x11 /* micron */ 63 #define RR_MT_2 0x12 /* micron L94C L95B */ 64 #define RR_TH_1 0x21 /* toshiba */ 65 #define RR_TH_2 0x22 /* toshiba */ 66 #define RR_TH_3 0x23 /* toshiba */ 67 #define RR_SS_1 0x31 /* samsung */ 68 #define RR_SD_1 0x41 /* Sandisk */ 69 #define RR_SD_2 0x42 /* Sandisk */ 70 #define RR_SD_3 0x43 /* Sandisk */ 71 #define RR_SD_4 0x44 /* Sandisk */ 72 73 /* 0 1 2 3 4 5 6 7 8 9 slc */ 74 #define LSB_0 0 75 /* 0 1 2 3 6 7 A B E F hynix, micron 74A */ 76 #define LSB_1 1 77 /* 0 1 3 5 7 9 B D toshiba samsung sandisk */ 78 #define LSB_2 2 79 /* 0 1 2 3 4 5 8 9 C D 10 11 micron 84A */ 80 #define LSB_3 3 81 /* 0 1 2 3 4 5 7 8 A B E F micron L95B */ 82 #define LSB_4 4 83 /* 0 1 2 3 4 5 8 9 14 15 20 21 26 27 micron B74A TLC */ 84 #define LSB_6 6 85 /* 0 3 6 9 C F 12 15 18 15 1B 1E 21 24 K9ABGD8U0C TLC */ 86 #define LSB_7 7 87 88 /* BadBlockFlagMode */ 89 /* first spare @ first page of each blocks */ 90 #define BBF_1 1 91 /* first spare @ last page of each blocks */ 92 #define BBF_2 2 93 /* first spare @ first and last page of each blocks */ 94 #define BBF_11 3 95 /* sandisk 15nm flash prog first page without data and check status */ 96 #define BBF_3 4 97 98 #define MPM_0 0 /* block 0 ~ 1 */ 99 #define MPM_1 1 /* block 0 ~ 2048... */ 100 101 struct NAND_PARA_INFO_T { 102 u8 id_bytes; 103 u8 nand_id[6]; 104 u8 vendor; 105 u8 die_per_chip; 106 u8 sec_per_page; 107 u16 page_per_blk; 108 u8 cell; /* 1 slc , 2 mlc , 3 tlc */ 109 u8 plane_per_die; 110 u16 blk_per_plane; 111 u16 operation_opt; 112 u8 lsb_mode; 113 u8 read_retry_mode; 114 u8 ecc_bits; 115 u8 access_freq; 116 u8 opt_mode; 117 u8 die_gap; 118 u8 bad_block_mode; 119 u8 multi_plane_mode; 120 u8 reversd2[6]; /* 32 bytes */ 121 }; 122 123 extern struct nand_phy_info g_nand_phy_info; 124 extern struct nand_ops g_nand_ops; 125 extern void __iomem *nandc_base; 126 127 void nandc_flash_get_id(u8 cs, void *buf); 128 void nandc_flash_reset(u8 chip_sel); 129 u32 nandc_flash_init(void __iomem *nandc_addr); 130 u32 nandc_flash_deinit(void); 131 132 #endif 133