1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.
4 *
5 * Copyright (c) 2013 MundoReader S.L.
6 * Author: Heiko Stuebner <heiko@sntech.de>
7 *
8 * With some ideas taken from pinctrl-samsung:
9 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
10 * http://www.samsung.com
11 * Copyright (c) 2012 Linaro Ltd
12 * https://www.linaro.org
13 *
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 */
17
18 #ifndef _PINCTRL_ROCKCHIP_H
19 #define _PINCTRL_ROCKCHIP_H
20
21 #define RK_GPIO0_A0 0
22 #define RK_GPIO0_A1 1
23 #define RK_GPIO0_A2 2
24 #define RK_GPIO0_A3 3
25 #define RK_GPIO0_A4 4
26 #define RK_GPIO0_A5 5
27 #define RK_GPIO0_A6 6
28 #define RK_GPIO0_A7 7
29 #define RK_GPIO0_B0 8
30 #define RK_GPIO0_B1 9
31 #define RK_GPIO0_B2 10
32 #define RK_GPIO0_B3 11
33 #define RK_GPIO0_B4 12
34 #define RK_GPIO0_B5 13
35 #define RK_GPIO0_B6 14
36 #define RK_GPIO0_B7 15
37 #define RK_GPIO0_C0 16
38 #define RK_GPIO0_C1 17
39 #define RK_GPIO0_C2 18
40 #define RK_GPIO0_C3 19
41 #define RK_GPIO0_C4 20
42 #define RK_GPIO0_C5 21
43 #define RK_GPIO0_C6 22
44 #define RK_GPIO0_C7 23
45 #define RK_GPIO0_D0 24
46 #define RK_GPIO0_D1 25
47 #define RK_GPIO0_D2 26
48 #define RK_GPIO0_D3 27
49 #define RK_GPIO0_D4 28
50 #define RK_GPIO0_D5 29
51 #define RK_GPIO0_D6 30
52 #define RK_GPIO0_D7 31
53
54 #define RK_GPIO1_A0 32
55 #define RK_GPIO1_A1 33
56 #define RK_GPIO1_A2 34
57 #define RK_GPIO1_A3 35
58 #define RK_GPIO1_A4 36
59 #define RK_GPIO1_A5 37
60 #define RK_GPIO1_A6 38
61 #define RK_GPIO1_A7 39
62 #define RK_GPIO1_B0 40
63 #define RK_GPIO1_B1 41
64 #define RK_GPIO1_B2 42
65 #define RK_GPIO1_B3 43
66 #define RK_GPIO1_B4 44
67 #define RK_GPIO1_B5 45
68 #define RK_GPIO1_B6 46
69 #define RK_GPIO1_B7 47
70 #define RK_GPIO1_C0 48
71 #define RK_GPIO1_C1 49
72 #define RK_GPIO1_C2 50
73 #define RK_GPIO1_C3 51
74 #define RK_GPIO1_C4 52
75 #define RK_GPIO1_C5 53
76 #define RK_GPIO1_C6 54
77 #define RK_GPIO1_C7 55
78 #define RK_GPIO1_D0 56
79 #define RK_GPIO1_D1 57
80 #define RK_GPIO1_D2 58
81 #define RK_GPIO1_D3 59
82 #define RK_GPIO1_D4 60
83 #define RK_GPIO1_D5 61
84 #define RK_GPIO1_D6 62
85 #define RK_GPIO1_D7 63
86
87 #define RK_GPIO2_A0 64
88 #define RK_GPIO2_A1 65
89 #define RK_GPIO2_A2 66
90 #define RK_GPIO2_A3 67
91 #define RK_GPIO2_A4 68
92 #define RK_GPIO2_A5 69
93 #define RK_GPIO2_A6 70
94 #define RK_GPIO2_A7 71
95 #define RK_GPIO2_B0 72
96 #define RK_GPIO2_B1 73
97 #define RK_GPIO2_B2 74
98 #define RK_GPIO2_B3 75
99 #define RK_GPIO2_B4 76
100 #define RK_GPIO2_B5 77
101 #define RK_GPIO2_B6 78
102 #define RK_GPIO2_B7 79
103 #define RK_GPIO2_C0 80
104 #define RK_GPIO2_C1 81
105 #define RK_GPIO2_C2 82
106 #define RK_GPIO2_C3 83
107 #define RK_GPIO2_C4 84
108 #define RK_GPIO2_C5 85
109 #define RK_GPIO2_C6 86
110 #define RK_GPIO2_C7 87
111 #define RK_GPIO2_D0 88
112 #define RK_GPIO2_D1 89
113 #define RK_GPIO2_D2 90
114 #define RK_GPIO2_D3 91
115 #define RK_GPIO2_D4 92
116 #define RK_GPIO2_D5 93
117 #define RK_GPIO2_D6 94
118 #define RK_GPIO2_D7 95
119
120 #define RK_GPIO3_A0 96
121 #define RK_GPIO3_A1 97
122 #define RK_GPIO3_A2 98
123 #define RK_GPIO3_A3 99
124 #define RK_GPIO3_A4 100
125 #define RK_GPIO3_A5 101
126 #define RK_GPIO3_A6 102
127 #define RK_GPIO3_A7 103
128 #define RK_GPIO3_B0 104
129 #define RK_GPIO3_B1 105
130 #define RK_GPIO3_B2 106
131 #define RK_GPIO3_B3 107
132 #define RK_GPIO3_B4 108
133 #define RK_GPIO3_B5 109
134 #define RK_GPIO3_B6 110
135 #define RK_GPIO3_B7 111
136 #define RK_GPIO3_C0 112
137 #define RK_GPIO3_C1 113
138 #define RK_GPIO3_C2 114
139 #define RK_GPIO3_C3 115
140 #define RK_GPIO3_C4 116
141 #define RK_GPIO3_C5 117
142 #define RK_GPIO3_C6 118
143 #define RK_GPIO3_C7 119
144 #define RK_GPIO3_D0 120
145 #define RK_GPIO3_D1 121
146 #define RK_GPIO3_D2 122
147 #define RK_GPIO3_D3 123
148 #define RK_GPIO3_D4 124
149 #define RK_GPIO3_D5 125
150 #define RK_GPIO3_D6 126
151 #define RK_GPIO3_D7 127
152
153 #define RK_GPIO4_A0 128
154 #define RK_GPIO4_A1 129
155 #define RK_GPIO4_A2 130
156 #define RK_GPIO4_A3 131
157 #define RK_GPIO4_A4 132
158 #define RK_GPIO4_A5 133
159 #define RK_GPIO4_A6 134
160 #define RK_GPIO4_A7 135
161 #define RK_GPIO4_B0 136
162 #define RK_GPIO4_B1 137
163 #define RK_GPIO4_B2 138
164 #define RK_GPIO4_B3 139
165 #define RK_GPIO4_B4 140
166 #define RK_GPIO4_B5 141
167 #define RK_GPIO4_B6 142
168 #define RK_GPIO4_B7 143
169 #define RK_GPIO4_C0 144
170 #define RK_GPIO4_C1 145
171 #define RK_GPIO4_C2 146
172 #define RK_GPIO4_C3 147
173 #define RK_GPIO4_C4 148
174 #define RK_GPIO4_C5 149
175 #define RK_GPIO4_C6 150
176 #define RK_GPIO4_C7 151
177 #define RK_GPIO4_D0 152
178 #define RK_GPIO4_D1 153
179 #define RK_GPIO4_D2 154
180 #define RK_GPIO4_D3 155
181 #define RK_GPIO4_D4 156
182 #define RK_GPIO4_D5 157
183 #define RK_GPIO4_D6 158
184 #define RK_GPIO4_D7 159
185
186 enum rockchip_pinctrl_type {
187 PX30,
188 RV1106,
189 RV1108,
190 RV1126,
191 RK1808,
192 RK2928,
193 RK3066B,
194 RK3128,
195 RK3188,
196 RK3288,
197 RK3308,
198 RK3368,
199 RK3399,
200 RK3528,
201 RK3562,
202 RK3568,
203 RK3588,
204 };
205
206 /**
207 * struct rockchip_gpio_regs
208 * @port_dr: data register
209 * @port_ddr: data direction register
210 * @int_en: interrupt enable
211 * @int_mask: interrupt mask
212 * @int_type: interrupt trigger type, such as high, low, edge trriger type.
213 * @int_polarity: interrupt polarity enable register
214 * @int_bothedge: interrupt bothedge enable register
215 * @int_status: interrupt status register
216 * @int_rawstatus: int_status = int_rawstatus & int_mask
217 * @debounce: enable debounce for interrupt signal
218 * @dbclk_div_en: enable divider for debounce clock
219 * @dbclk_div_con: setting for divider of debounce clock
220 * @port_eoi: end of interrupt of the port
221 * @ext_port: port data from external
222 * @version_id: controller version register
223 */
224 struct rockchip_gpio_regs {
225 u32 port_dr;
226 u32 port_ddr;
227 u32 int_en;
228 u32 int_mask;
229 u32 int_type;
230 u32 int_polarity;
231 u32 int_bothedge;
232 u32 int_status;
233 u32 int_rawstatus;
234 u32 debounce;
235 u32 dbclk_div_en;
236 u32 dbclk_div_con;
237 u32 port_eoi;
238 u32 ext_port;
239 u32 version_id;
240 };
241
242 /**
243 * struct rockchip_iomux
244 * @type: iomux variant using IOMUX_* constants
245 * @offset: if initialized to -1 it will be autocalculated, by specifying
246 * an initial offset value the relevant source offset can be reset
247 * to a new value for autocalculating the following iomux registers.
248 */
249 struct rockchip_iomux {
250 int type;
251 int offset;
252 };
253
254 /*
255 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
256 */
257 enum rockchip_pin_drv_type {
258 DRV_TYPE_IO_DEFAULT = 0,
259 DRV_TYPE_IO_1V8_OR_3V0,
260 DRV_TYPE_IO_1V8_ONLY,
261 DRV_TYPE_IO_1V8_3V0_AUTO,
262 DRV_TYPE_IO_3V3_ONLY,
263 DRV_TYPE_IO_SMIC,
264 DRV_TYPE_MAX
265 };
266
267 /*
268 * enum type index corresponding to rockchip_pull_list arrays index.
269 */
270 enum rockchip_pin_pull_type {
271 PULL_TYPE_IO_DEFAULT = 0,
272 PULL_TYPE_IO_1V8_ONLY,
273 PULL_TYPE_MAX
274 };
275
276 /**
277 * struct rockchip_drv
278 * @drv_type: drive strength variant using rockchip_perpin_drv_type
279 * @offset: if initialized to -1 it will be autocalculated, by specifying
280 * an initial offset value the relevant source offset can be reset
281 * to a new value for autocalculating the following drive strength
282 * registers. if used chips own cal_drv func instead to calculate
283 * registers offset, the variant could be ignored.
284 */
285 struct rockchip_drv {
286 enum rockchip_pin_drv_type drv_type;
287 int offset;
288 };
289
290 /**
291 * struct rockchip_pin_bank
292 * @dev: the pinctrl device bind to the bank
293 * @reg_base: register base of the gpio bank
294 * @regmap_pull: optional separate register for additional pull settings
295 * @clk: clock of the gpio bank
296 * @db_clk: clock of the gpio debounce
297 * @irq: interrupt of the gpio bank
298 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
299 * @pin_base: first pin number
300 * @nr_pins: number of pins in this bank
301 * @name: name of the bank
302 * @bank_num: number of the bank, to account for holes
303 * @iomux: array describing the 4 iomux sources of the bank
304 * @drv: array describing the 4 drive strength sources of the bank
305 * @pull_type: array describing the 4 pull type sources of the bank
306 * @valid: is all necessary information present
307 * @of_node: dt node of this bank
308 * @drvdata: common pinctrl basedata
309 * @domain: irqdomain of the gpio bank
310 * @gpio_chip: gpiolib chip
311 * @grange: gpio range
312 * @slock: spinlock for the gpio bank
313 * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
314 * @recalced_mask: bit mask to indicate a need to recalulate the mask
315 * @route_mask: bits describing the routing pins of per bank
316 * @deferred_output: gpio output settings to be done after gpio bank probed
317 * @deferred_lock: mutex for the deferred_output shared btw gpio and pinctrl
318 */
319 struct rockchip_pin_bank {
320 struct device *dev;
321 void __iomem *reg_base;
322 struct regmap *regmap_pull;
323 struct clk *clk;
324 struct clk *db_clk;
325 int irq;
326 u32 saved_masks;
327 u32 pin_base;
328 u8 nr_pins;
329 char *name;
330 u8 bank_num;
331 struct rockchip_iomux iomux[4];
332 struct rockchip_drv drv[4];
333 enum rockchip_pin_pull_type pull_type[4];
334 bool valid;
335 struct device_node *of_node;
336 struct rockchip_pinctrl *drvdata;
337 struct irq_domain *domain;
338 struct gpio_chip gpio_chip;
339 struct pinctrl_gpio_range grange;
340 raw_spinlock_t slock;
341 const struct rockchip_gpio_regs *gpio_regs;
342 u32 gpio_type;
343 u32 toggle_edge_mode;
344 u32 recalced_mask;
345 u32 route_mask;
346 struct list_head deferred_pins;
347 struct mutex deferred_lock;
348 };
349
350 /**
351 * struct rockchip_mux_recalced_data: represent a pin iomux data.
352 * @num: bank number.
353 * @pin: pin number.
354 * @bit: index at register.
355 * @reg: register offset.
356 * @mask: mask bit
357 */
358 struct rockchip_mux_recalced_data {
359 u8 num;
360 u8 pin;
361 u32 reg;
362 u8 bit;
363 u8 mask;
364 };
365
366 enum rockchip_mux_route_location {
367 ROCKCHIP_ROUTE_SAME = 0,
368 ROCKCHIP_ROUTE_PMU,
369 ROCKCHIP_ROUTE_GRF,
370 };
371
372 /**
373 * struct rockchip_mux_recalced_data: represent a pin iomux data.
374 * @bank_num: bank number.
375 * @pin: index at register or used to calc index.
376 * @func: the min pin.
377 * @route_location: the mux route location (same, pmu, grf).
378 * @route_offset: the max pin.
379 * @route_val: the register offset.
380 */
381 struct rockchip_mux_route_data {
382 u8 bank_num;
383 u8 pin;
384 u8 func;
385 enum rockchip_mux_route_location route_location;
386 u32 route_offset;
387 u32 route_val;
388 };
389
390 struct rockchip_pin_ctrl {
391 struct rockchip_pin_bank *pin_banks;
392 u32 nr_banks;
393 u32 nr_pins;
394 char *label;
395 enum rockchip_pinctrl_type type;
396 int grf_mux_offset;
397 int pmu_mux_offset;
398 int grf_drv_offset;
399 int pmu_drv_offset;
400 struct rockchip_mux_recalced_data *iomux_recalced;
401 u32 niomux_recalced;
402 struct rockchip_mux_route_data *iomux_routes;
403 u32 niomux_routes;
404
405 int (*pull_calc_reg)(struct rockchip_pin_bank *bank,
406 int pin_num, struct regmap **regmap,
407 int *reg, u8 *bit);
408 int (*drv_calc_reg)(struct rockchip_pin_bank *bank,
409 int pin_num, struct regmap **regmap,
410 int *reg, u8 *bit);
411 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
412 int pin_num, struct regmap **regmap,
413 int *reg, u8 *bit);
414 int (*slew_rate_calc_reg)(struct rockchip_pin_bank *bank,
415 int pin_num, struct regmap **regmap,
416 int *reg, u8 *bit);
417 };
418
419 struct rockchip_pin_config {
420 unsigned int func;
421 unsigned long *configs;
422 unsigned int nconfigs;
423 };
424
425 enum pin_config_param;
426
427 struct rockchip_pin_deferred {
428 struct list_head head;
429 unsigned int pin;
430 enum pin_config_param param;
431 u32 arg;
432 };
433
434 /**
435 * struct rockchip_pin_group: represent group of pins of a pinmux function.
436 * @name: name of the pin group, used to lookup the group.
437 * @pins: the pins included in this group.
438 * @npins: number of pins included in this group.
439 * @data: local pin configuration
440 */
441 struct rockchip_pin_group {
442 const char *name;
443 unsigned int npins;
444 unsigned int *pins;
445 struct rockchip_pin_config *data;
446 };
447
448 /**
449 * struct rockchip_pmx_func: represent a pin function.
450 * @name: name of the pin function, used to lookup the function.
451 * @groups: one or more names of pin groups that provide this function.
452 * @ngroups: number of groups included in @groups.
453 */
454 struct rockchip_pmx_func {
455 const char *name;
456 const char **groups;
457 u8 ngroups;
458 };
459
460 struct rockchip_pinctrl {
461 struct regmap *regmap_base;
462 int reg_size;
463 struct regmap *regmap_pull;
464 struct regmap *regmap_pmu;
465 struct device *dev;
466 struct rockchip_pin_ctrl *ctrl;
467 struct pinctrl_desc pctl;
468 struct pinctrl_dev *pctl_dev;
469 struct rockchip_pin_group *groups;
470 unsigned int ngroups;
471 struct rockchip_pmx_func *functions;
472 unsigned int nfunctions;
473 };
474
475 #if IS_ENABLED(CONFIG_PINCTRL_ROCKCHIP)
476 int rk_iomux_set(int bank, int pin, int mux);
477 int rk_iomux_get(int bank, int pin, int *mux);
478 #else
rk_iomux_set(int bank,int pin,int mux)479 static inline int rk_iomux_set(int bank, int pin, int mux)
480 {
481 return -EINVAL;
482 }
483
rk_iomux_get(int bank,int pin,int * mux)484 static inline int rk_iomux_get(int bank, int pin, int *mux)
485 {
486 return -EINVAL;
487 }
488 #endif
489
490 #endif
491