1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Pinctrl driver for Rockchip RK628
4 *
5 * Copyright (c) 2019, Fuzhou Rockchip Electronics Co., Ltd
6 *
7 * Author: Weixin Zhou <zwx@rock-chips.com>
8 *
9 * Based on the pinctrl-rk805/pinctrl-rockchip driver
10 */
11
12 #include <linux/gpio/driver.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_device.h>
17 #include <linux/platform_device.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/pinctrl/machine.h>
20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/pinctrl/pinconf-generic.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/pm.h>
25 #include <linux/slab.h>
26 #include <linux/clk.h>
27 #include <linux/interrupt.h>
28 #include <linux/regmap.h>
29 #include <linux/mfd/rk628.h>
30
31 #include "core.h"
32 #include "pinconf.h"
33 #include "pinctrl-utils.h"
34
35 #define GPIO0_BASE 0xD0000
36 #define GPIO1_BASE 0xE0000
37 #define GPIO2_BASE 0xF0000
38 #define GPIO3_BASE 0x100000
39 #define GPIO_MAX_REGISTER (GPIO3_BASE + GPIO_VER_ID)
40
41 /* GPIO control registers */
42 #define GPIO_SWPORT_DR_L 0x00
43 #define GPIO_SWPORT_DR_H 0x04
44 #define GPIO_SWPORT_DDR_L 0x08
45 #define GPIO_SWPORT_DDR_H 0x0c
46 #define GPIO_INTEN_L 0x10
47 #define GPIO_INTEN_H 0x14
48 #define GPIO_INTMASK_L 0x18
49 #define GPIO_INTMASK_H 0x1c
50 #define GPIO_INTTYPE_L 0x20
51 #define GPIO_INTTYPE_H 0x24
52 #define GPIO_INT_POLARITY_L 0x28
53 #define GPIO_INT_POLARITY_H 0x2c
54 #define GPIO_INT_BOTHEDGE_L 0x30
55 #define GPIO_INT_BOTHEDGE_H 0x34
56 #define GPIO_DEBOUNCE_L 0x38
57 #define GPIO_DEBOUNCE_H 0x3c
58 #define GPIO_DBCLK_DIV_EN_L 0x40
59 #define GPIO_DBCLK_DIV_EN_H 0x44
60 #define GPIO_INT_STATUS 0x50
61 #define GPIO_INT_RAWSTATUS 0x58
62 #define GPIO_PORTS_EOI_L 0x60
63 #define GPIO_PORTS_EOI_H 0x64
64 #define GPIO_EXT_PORT 0x70
65 #define GPIO_VER_ID 0x78
66
67 #define GPIO_REG_LOW 0x0
68 #define GPIO_REG_HIGH 0x1
69
70 /* GPIO control registers */
71 #define GPIO_INTMASK 0x34
72 #define GPIO_PORTS_EOI 0x4c
73
74 #define BANK_OFFSET 32
75
76 #define IRQ_CHIP(fname) \
77 [IRQCHIP_##fname] = { \
78 .name = "rk628-"#fname, \
79 .irq_bus_lock = rk628_irq_lock, \
80 .irq_bus_sync_unlock = rk628_irq_sync_unlock,\
81 .irq_disable = rk628_irq_disable, \
82 .irq_enable = rk628_irq_enable, \
83 .irq_set_type = rk628_irq_set_type, \
84 }
85
86 struct rk628_pin_function {
87 const char *name;
88 const char **groups;
89 unsigned int ngroups;
90 int mux_option;
91 };
92
93 struct rk628_pin_group {
94 const char *name;
95 const unsigned int pins[1];
96 unsigned int npins;
97 int iomux_base;
98 };
99
100 struct rk628_pin_bank {
101 char *name;
102 u32 reg_base;
103 u32 nr_pins;
104 struct device_node *of_node;
105 struct pinctrl_gpio_range grange;
106 struct gpio_chip gpio_chip;
107 struct clk *clk;
108 struct rk628_pctrl_info *pci;
109
110 struct irq_chip irq_chip;
111 struct irq_domain *domain;
112 int irq;
113 struct mutex lock;
114 unsigned int mask_regs[2];
115 unsigned int polarity_regs[2];
116 unsigned int level_regs[2];
117 unsigned int bothedge_regs[2];
118 };
119
120 struct rk628_pctrl_info {
121 struct device *dev;
122 struct pinctrl_dev *pctl;
123 struct pinctrl_desc pinctrl_desc;
124 const struct rk628_pin_function *functions;
125 unsigned int num_functions;
126 const struct rk628_pin_group *groups;
127 int num_groups;
128 const struct pinctrl_pin_desc *pins;
129 unsigned int num_pins;
130 struct regmap *regmap;
131 struct regmap *grf_regmap;
132 struct rk628_pin_bank *pin_banks;
133 u32 nr_banks;
134 };
135
136 enum rk628_pinmux_option {
137 PINMUX_FUNC0,
138 PINMUX_FUNC1,
139 };
140
141 #define PINCTRL_GROUP(a, b, c, d) { .name = a, .pins = b, .npins = c, .iomux_base = d}
142 #define PINCTRL_BANK(a, b, c) { .name = a, .reg_base = b, .nr_pins = c}
143
144 enum rk628_functions {
145 MUX_GPIO,
146 };
147
148 static const char *gpio_groups[] = {
149 "gpio0a0", "gpio0a1", "gpio0a2", "gpio0a3", "gpio0a4", "gpio0a5",
150 "gpio0a6", "gpio0a7", "gpio0b0", "gpio0b1", "gpio0b2", "gpio0b3",
151 "gpio1a0", "gpio1a1", "gpio1a2", "gpio1a3", "gpio1a4", "gpio1a5",
152 "gpio1a6", "gpio1a7", "gpio1b0", "gpio1b1", "gpio1b2", "gpio1b3",
153 "gpio1b4", "gpio1b5",
154 "gpio2a0", "gpio2a1", "gpio2a2", "gpio2a3", "gpio2a4", "gpio2a5",
155 "gpio2a6", "gpio2a7", "gpio2b0", "gpio2b1", "gpio2b2", "gpio2b3",
156 "gpio2b4", "gpio2b5", "gpio2b6", "gpio2b7", "gpio2c0", "gpio2c1",
157 "gpio2c3", "gpio2c4", "gpio2c5", "gpio2c6", "gpio2c7", "gpio1a0",
158 "gpio3a1", "gpio3a2", "gpio3a3", "gpio3a4", "gpio3a5", "gpio3a6",
159 "gpio3a7", "gpio3b0", "gpio3b1", "gpio3b2", "gpio3b3", "gpio3b4",
160 };
161
162 static struct rk628_pin_function rk628_functions[] = {
163 {
164 .name = "gpio",
165 .groups = gpio_groups,
166 .ngroups = ARRAY_SIZE(gpio_groups),
167 },
168 };
169
170 enum {
171 GPIO_HIGH_Z,
172 GPIO_PULL_UP,
173 GPIO_PULL_DOWN,
174 };
175
176 enum {
177 GPIO0_A0 = BANK_OFFSET * 0,
178 GPIO0_A1,
179 GPIO0_A2,
180 GPIO0_A3,
181 GPIO0_A4,
182 GPIO0_A5,
183 GPIO0_A6,
184 GPIO0_A7,
185 GPIO0_B0,
186 GPIO0_B1,
187 GPIO0_B2,
188 GPIO0_B3,
189 GPIO1_A0 = BANK_OFFSET * 1,
190 GPIO1_A1,
191 GPIO1_A2,
192 GPIO1_A3,
193 GPIO1_A4,
194 GPIO1_A5,
195 GPIO1_A6,
196 GPIO1_A7,
197 GPIO1_B0,
198 GPIO1_B1,
199 GPIO1_B2,
200 GPIO1_B3,
201 GPIO1_B4,
202 GPIO1_B5,
203 GPIO2_A0 = BANK_OFFSET * 2,
204 GPIO2_A1,
205 GPIO2_A2,
206 GPIO2_A3,
207 GPIO2_A4,
208 GPIO2_A5,
209 GPIO2_A6,
210 GPIO2_A7,
211 GPIO2_B0,
212 GPIO2_B1,
213 GPIO2_B2,
214 GPIO2_B3,
215 GPIO2_B4,
216 GPIO2_B5,
217 GPIO2_B6,
218 GPIO2_B7,
219 GPIO2_C0,
220 GPIO2_C1,
221 GPIO2_C2,
222 GPIO2_C3,
223 GPIO2_C4,
224 GPIO2_C5,
225 GPIO2_C6,
226 GPIO2_C7,
227 GPIO3_A0 = BANK_OFFSET * 3,
228 GPIO3_A1,
229 GPIO3_A2,
230 GPIO3_A3,
231 GPIO3_A4,
232 GPIO3_A5,
233 GPIO3_A6,
234 GPIO3_A7,
235 GPIO3_B0,
236 GPIO3_B1,
237 GPIO3_B2,
238 GPIO3_B3,
239 GPIO3_B4,
240 I2SM_SCK = BANK_OFFSET * 4 + 2,
241 I2SM_D,
242 I2SM_LR,
243 RXDDC_SCL,
244 RXDDC_SDA,
245 HDMIRX_CE,
246 };
247
248 static struct pinctrl_pin_desc rk628_pins_desc[] = {
249 PINCTRL_PIN(GPIO0_A0, "gpio0a0"),
250 PINCTRL_PIN(GPIO0_A1, "gpio0a1"),
251 PINCTRL_PIN(GPIO0_A2, "gpio0a2"),
252 PINCTRL_PIN(GPIO0_A3, "gpio0a3"),
253 PINCTRL_PIN(GPIO0_A4, "gpio0a4"),
254 PINCTRL_PIN(GPIO0_A5, "gpio0a5"),
255 PINCTRL_PIN(GPIO0_A6, "gpio0a6"),
256 PINCTRL_PIN(GPIO0_A7, "gpio0a7"),
257 PINCTRL_PIN(GPIO0_B0, "gpio0b0"),
258 PINCTRL_PIN(GPIO0_B1, "gpio0b1"),
259 PINCTRL_PIN(GPIO0_B2, "gpio0b2"),
260 PINCTRL_PIN(GPIO0_B3, "gpio0b3"),
261
262 PINCTRL_PIN(GPIO1_A0, "gpio1a0"),
263 PINCTRL_PIN(GPIO1_A1, "gpio1a1"),
264 PINCTRL_PIN(GPIO1_A2, "gpio1a2"),
265 PINCTRL_PIN(GPIO1_A3, "gpio1a3"),
266 PINCTRL_PIN(GPIO1_A4, "gpio1a4"),
267 PINCTRL_PIN(GPIO1_A5, "gpio1a5"),
268 PINCTRL_PIN(GPIO1_A6, "gpio1a6"),
269 PINCTRL_PIN(GPIO1_A7, "gpio1a7"),
270 PINCTRL_PIN(GPIO1_B0, "gpio1b0"),
271 PINCTRL_PIN(GPIO1_B1, "gpio1b1"),
272 PINCTRL_PIN(GPIO1_B2, "gpio1b2"),
273 PINCTRL_PIN(GPIO1_B3, "gpio1b3"),
274 PINCTRL_PIN(GPIO1_B4, "gpio1b4"),
275 PINCTRL_PIN(GPIO1_B5, "gpio1b5"),
276
277 PINCTRL_PIN(GPIO2_A0, "gpio2a0"),
278 PINCTRL_PIN(GPIO2_A1, "gpio2a1"),
279 PINCTRL_PIN(GPIO2_A2, "gpio2a2"),
280 PINCTRL_PIN(GPIO2_A3, "gpio2a3"),
281 PINCTRL_PIN(GPIO2_A4, "gpio2a4"),
282 PINCTRL_PIN(GPIO2_A5, "gpio2a5"),
283 PINCTRL_PIN(GPIO2_A6, "gpio2a6"),
284 PINCTRL_PIN(GPIO2_A7, "gpio2a7"),
285 PINCTRL_PIN(GPIO2_B0, "gpio2b0"),
286 PINCTRL_PIN(GPIO2_B1, "gpio2b1"),
287 PINCTRL_PIN(GPIO2_B2, "gpio2b2"),
288 PINCTRL_PIN(GPIO2_B3, "gpio2b3"),
289 PINCTRL_PIN(GPIO2_B4, "gpio2b4"),
290 PINCTRL_PIN(GPIO2_B5, "gpio2b5"),
291 PINCTRL_PIN(GPIO2_B6, "gpio2b6"),
292 PINCTRL_PIN(GPIO2_B7, "gpio2b7"),
293 PINCTRL_PIN(GPIO2_C0, "gpio2c0"),
294 PINCTRL_PIN(GPIO2_C1, "gpio2c1"),
295 PINCTRL_PIN(GPIO2_C2, "gpio2c2"),
296 PINCTRL_PIN(GPIO2_C3, "gpio2c3"),
297 PINCTRL_PIN(GPIO2_C4, "gpio2c4"),
298 PINCTRL_PIN(GPIO2_C5, "gpio2c5"),
299 PINCTRL_PIN(GPIO2_C6, "gpio2c6"),
300 PINCTRL_PIN(GPIO2_C7, "gpio2c7"),
301
302 PINCTRL_PIN(GPIO3_A0, "gpio3a0"),
303 PINCTRL_PIN(GPIO3_A1, "gpio3a1"),
304 PINCTRL_PIN(GPIO3_A2, "gpio3a2"),
305 PINCTRL_PIN(GPIO3_A3, "gpio3a3"),
306 PINCTRL_PIN(GPIO3_A4, "gpio3a4"),
307 PINCTRL_PIN(GPIO3_A5, "gpio3a5"),
308 PINCTRL_PIN(GPIO3_A6, "gpio3a6"),
309 PINCTRL_PIN(GPIO3_A7, "gpio3a7"),
310 PINCTRL_PIN(GPIO3_B0, "gpio3b0"),
311 PINCTRL_PIN(GPIO3_B1, "gpio3b1"),
312 PINCTRL_PIN(GPIO3_B2, "gpio3b2"),
313 PINCTRL_PIN(GPIO3_B3, "gpio3b3"),
314 PINCTRL_PIN(GPIO3_B4, "gpio3b4"),
315
316 PINCTRL_PIN(I2SM_SCK, "i2sm_sck"),
317 PINCTRL_PIN(I2SM_D, "i2sm_d"),
318 PINCTRL_PIN(I2SM_LR, "i2sm_lr"),
319 PINCTRL_PIN(RXDDC_SCL, "rxddc_scl"),
320 PINCTRL_PIN(RXDDC_SDA, "rxddc_sda"),
321 PINCTRL_PIN(HDMIRX_CE, "hdmirx_cec"),
322 };
323
324 static const struct rk628_pin_group rk628_pin_groups[] = {
325 PINCTRL_GROUP("gpio0a0", { GPIO0_A0 }, 1, GRF_GPIO0AB_SEL_CON),
326 PINCTRL_GROUP("gpio0a1", { GPIO0_A1 }, 1, GRF_GPIO0AB_SEL_CON),
327 PINCTRL_GROUP("gpio0a2", { GPIO0_A2 }, 1, GRF_GPIO0AB_SEL_CON),
328 PINCTRL_GROUP("gpio0a3", { GPIO0_A3 }, 1, GRF_GPIO0AB_SEL_CON),
329 PINCTRL_GROUP("gpio0a4", { GPIO0_A4 }, 1, GRF_GPIO0AB_SEL_CON),
330 PINCTRL_GROUP("gpio0a5", { GPIO0_A5 }, 1, GRF_GPIO0AB_SEL_CON),
331 PINCTRL_GROUP("gpio0a6", { GPIO0_A6 }, 1, GRF_GPIO0AB_SEL_CON),
332 PINCTRL_GROUP("gpio0a7", { GPIO0_A7 }, 1, GRF_GPIO0AB_SEL_CON),
333 PINCTRL_GROUP("gpio0b0", { GPIO0_B0 }, 1, GRF_GPIO0AB_SEL_CON),
334 PINCTRL_GROUP("gpio0b1", { GPIO0_B1 }, 1, GRF_GPIO0AB_SEL_CON),
335 PINCTRL_GROUP("gpio0b2", { GPIO0_B2 }, 1, GRF_GPIO0AB_SEL_CON),
336 PINCTRL_GROUP("gpio0b3", { GPIO0_B3 }, 1, GRF_GPIO0AB_SEL_CON),
337
338 PINCTRL_GROUP("gpio1a0", { GPIO1_A0 }, 1, GRF_GPIO1AB_SEL_CON),
339 PINCTRL_GROUP("gpio1a1", { GPIO1_A1 }, 1, GRF_GPIO1AB_SEL_CON),
340 PINCTRL_GROUP("gpio1a2", { GPIO1_A2 }, 1, GRF_GPIO1AB_SEL_CON),
341 PINCTRL_GROUP("gpio1a3", { GPIO1_A3 }, 1, GRF_GPIO1AB_SEL_CON),
342 PINCTRL_GROUP("gpio1a4", { GPIO1_A4 }, 1, GRF_GPIO1AB_SEL_CON),
343 PINCTRL_GROUP("gpio1a5", { GPIO1_A5 }, 1, GRF_GPIO1AB_SEL_CON),
344 PINCTRL_GROUP("gpio1a6", { GPIO1_A6 }, 1, GRF_GPIO1AB_SEL_CON),
345 PINCTRL_GROUP("gpio1a7", { GPIO1_A7 }, 1, GRF_GPIO1AB_SEL_CON),
346 PINCTRL_GROUP("gpio1b0", { GPIO1_B0 }, 1, GRF_GPIO1AB_SEL_CON),
347 PINCTRL_GROUP("gpio1b1", { GPIO1_B1 }, 1, GRF_GPIO1AB_SEL_CON),
348 PINCTRL_GROUP("gpio1b2", { GPIO1_B2 }, 1, GRF_GPIO1AB_SEL_CON),
349 PINCTRL_GROUP("gpio1b3", { GPIO1_B3 }, 1, GRF_GPIO1AB_SEL_CON),
350 PINCTRL_GROUP("gpio1b4", { GPIO1_B4 }, 1, GRF_GPIO1AB_SEL_CON),
351 PINCTRL_GROUP("gpio1b5", { GPIO1_B5 }, 1, GRF_GPIO1AB_SEL_CON),
352
353 PINCTRL_GROUP("gpio2a0", { GPIO2_A0 }, 1, GRF_GPIO2AB_SEL_CON),
354 PINCTRL_GROUP("gpio2a1", { GPIO2_A1 }, 1, GRF_GPIO2AB_SEL_CON),
355 PINCTRL_GROUP("gpio2a2", { GPIO2_A2 }, 1, GRF_GPIO2AB_SEL_CON),
356 PINCTRL_GROUP("gpio2a3", { GPIO2_A3 }, 1, GRF_GPIO2AB_SEL_CON),
357 PINCTRL_GROUP("gpio2a4", { GPIO2_A4 }, 1, GRF_GPIO2AB_SEL_CON),
358 PINCTRL_GROUP("gpio2a5", { GPIO2_A5 }, 1, GRF_GPIO2AB_SEL_CON),
359 PINCTRL_GROUP("gpio2a6", { GPIO2_A6 }, 1, GRF_GPIO2AB_SEL_CON),
360 PINCTRL_GROUP("gpio2a7", { GPIO2_A7 }, 1, GRF_GPIO2AB_SEL_CON),
361 PINCTRL_GROUP("gpio2b0", { GPIO2_B0 }, 1, GRF_GPIO2AB_SEL_CON),
362 PINCTRL_GROUP("gpio2b1", { GPIO2_B1 }, 1, GRF_GPIO2AB_SEL_CON),
363 PINCTRL_GROUP("gpio2b2", { GPIO2_B2 }, 1, GRF_GPIO2AB_SEL_CON),
364 PINCTRL_GROUP("gpio2b3", { GPIO2_B3 }, 1, GRF_GPIO2AB_SEL_CON),
365 PINCTRL_GROUP("gpio2b4", { GPIO2_B4 }, 1, GRF_GPIO2AB_SEL_CON),
366 PINCTRL_GROUP("gpio2b5", { GPIO2_B5 }, 1, GRF_GPIO2AB_SEL_CON),
367 PINCTRL_GROUP("gpio2b6", { GPIO2_B6 }, 1, GRF_GPIO2AB_SEL_CON),
368 PINCTRL_GROUP("gpio2b7", { GPIO2_B7 }, 1, GRF_GPIO2AB_SEL_CON),
369 PINCTRL_GROUP("gpio2c0", { GPIO2_C0 }, 1, GRF_GPIO2C_SEL_CON),
370 PINCTRL_GROUP("gpio2c1", { GPIO2_C1 }, 1, GRF_GPIO2C_SEL_CON),
371 PINCTRL_GROUP("gpio2c2", { GPIO2_C2 }, 1, GRF_GPIO2C_SEL_CON),
372 PINCTRL_GROUP("gpio2c3", { GPIO2_C3 }, 1, GRF_GPIO2C_SEL_CON),
373 PINCTRL_GROUP("gpio2c4", { GPIO2_C4 }, 1, GRF_GPIO2C_SEL_CON),
374 PINCTRL_GROUP("gpio2c5", { GPIO2_C5 }, 1, GRF_GPIO2C_SEL_CON),
375 PINCTRL_GROUP("gpio2c6", { GPIO2_C6 }, 1, GRF_GPIO2C_SEL_CON),
376 PINCTRL_GROUP("gpio2c7", { GPIO2_C7 }, 1, GRF_GPIO2C_SEL_CON),
377
378 PINCTRL_GROUP("gpio3a0", { GPIO3_A0 }, 1, GRF_GPIO3AB_SEL_CON),
379 PINCTRL_GROUP("gpio3a1", { GPIO3_A1 }, 1, GRF_GPIO3AB_SEL_CON),
380 PINCTRL_GROUP("gpio3a2", { GPIO3_A2 }, 1, GRF_GPIO3AB_SEL_CON),
381 PINCTRL_GROUP("gpio3a3", { GPIO3_A3 }, 1, GRF_GPIO3AB_SEL_CON),
382 PINCTRL_GROUP("gpio3a4", { GPIO3_A4 }, 1, GRF_GPIO3AB_SEL_CON),
383 PINCTRL_GROUP("gpio3a5", { GPIO3_A5 }, 1, GRF_GPIO3AB_SEL_CON),
384 PINCTRL_GROUP("gpio3a6", { GPIO3_A6 }, 1, GRF_GPIO3AB_SEL_CON),
385 PINCTRL_GROUP("gpio3a7", { GPIO3_A7 }, 1, GRF_GPIO3AB_SEL_CON),
386 PINCTRL_GROUP("gpio3b0", { GPIO3_B0 }, 1, GRF_GPIO3AB_SEL_CON),
387 PINCTRL_GROUP("gpio3b1", { GPIO3_B1 }, 1, GRF_GPIO3AB_SEL_CON),
388 PINCTRL_GROUP("gpio3b2", { GPIO3_B2 }, 1, GRF_GPIO3AB_SEL_CON),
389 PINCTRL_GROUP("gpio3b3", { GPIO3_B3 }, 1, GRF_GPIO3AB_SEL_CON),
390 PINCTRL_GROUP("gpio3b4", { GPIO3_B4 }, 1, GRF_GPIO3AB_SEL_CON),
391
392 PINCTRL_GROUP("i2sm_sck", { I2SM_SCK }, 1, GRF_SYSTEM_CON3),
393 PINCTRL_GROUP("i2sm_d", { I2SM_D }, 1, GRF_SYSTEM_CON3),
394 PINCTRL_GROUP("i2sm_lr", { I2SM_LR }, 1, GRF_SYSTEM_CON3),
395 PINCTRL_GROUP("rxddc_scl", { RXDDC_SCL }, 1, GRF_SYSTEM_CON3),
396 PINCTRL_GROUP("rxddc_sda", { RXDDC_SDA }, 1, GRF_SYSTEM_CON3),
397 PINCTRL_GROUP("hdmirx_cec", { HDMIRX_CE }, 1, GRF_SYSTEM_CON3),
398 };
399
400 static struct rk628_pin_bank rk628_pin_banks[] = {
401 PINCTRL_BANK("rk628-gpio0", GPIO0_BASE, 12),
402 PINCTRL_BANK("rk628-gpio1", GPIO1_BASE, 14),
403 PINCTRL_BANK("rk628-gpio2", GPIO2_BASE, 24),
404 PINCTRL_BANK("rk628-gpio3", GPIO3_BASE, 13),
405 };
406
407 /* generic gpio chip */
rk628_gpio_get(struct gpio_chip * chip,unsigned int offset)408 static int rk628_gpio_get(struct gpio_chip *chip, unsigned int offset)
409 {
410 struct rk628_pin_bank *bank = gpiochip_get_data(chip);
411 struct rk628_pctrl_info *pci = bank->pci;
412 int data_reg, val, ret;
413
414 data_reg = bank->reg_base + GPIO_EXT_PORT;
415
416 clk_enable(bank->clk);
417 ret = regmap_read(pci->regmap, data_reg, &val);
418 if (ret)
419 dev_err(pci->dev, "%s: regmap read failed!\n", __func__);
420 clk_disable(bank->clk);
421
422 val >>= offset;
423 val &= 1;
424 dev_dbg(pci->dev, "%s bank->name=%s dir_reg=0x%x offset=%x value=%x\n",
425 __func__, bank->name, data_reg, offset, val);
426
427 return val;
428 }
429
rk628_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)430 static void rk628_gpio_set(struct gpio_chip *chip,
431 unsigned int offset,
432 int value)
433 {
434 struct rk628_pin_bank *bank = gpiochip_get_data(chip);
435 struct rk628_pctrl_info *pci = bank->pci;
436 int data_reg, val, ret;
437
438 if (offset / 16) {
439 data_reg = bank->reg_base + GPIO_SWPORT_DR_H;
440 offset -= 16;
441 } else {
442 data_reg = bank->reg_base + GPIO_SWPORT_DR_L;
443 }
444 if (value)
445 val = BIT(offset + 16) | BIT(offset);
446 else
447 val = BIT(offset + 16) | (0xffff & ~BIT(offset));
448
449 clk_enable(bank->clk);
450 ret = regmap_write(pci->regmap, data_reg, val);
451 if (ret)
452 pr_err("%s: regmap write failed! bank->name=%s data_reg=0x%x offset=%d\n",
453 __func__, bank->name, data_reg, offset);
454 clk_disable(bank->clk);
455 }
456
rk628_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)457 static int rk628_gpio_direction_input(struct gpio_chip *chip,
458 unsigned int offset)
459 {
460 return pinctrl_gpio_direction_input(chip->base + offset);
461 }
462
rk628_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)463 static int rk628_gpio_direction_output(struct gpio_chip *chip,
464 unsigned int offset,
465 int value)
466 {
467 rk628_gpio_set(chip, offset, value);
468 return pinctrl_gpio_direction_output(chip->base + offset);
469 }
470
rk628_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)471 static int rk628_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
472 {
473 struct rk628_pin_bank *bank = gpiochip_get_data(chip);
474 struct rk628_pctrl_info *pci = bank->pci;
475 int dir_reg, val, ret;
476
477 if (offset / 16) {
478 dir_reg = bank->reg_base + GPIO_SWPORT_DDR_H;
479 offset -= 16;
480 } else {
481 dir_reg = bank->reg_base + GPIO_SWPORT_DDR_L;
482 }
483
484 clk_enable(bank->clk);
485 ret = regmap_read(pci->regmap, dir_reg, &val);
486 if (ret)
487 dev_err(pci->dev, "%s: regmap read failed!\n", __func__);
488 clk_disable(bank->clk);
489
490 val = BIT(offset) & val;
491
492 return !val;
493 }
494
rk628_gpio_to_irq(struct gpio_chip * gc,unsigned offset)495 static int rk628_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
496 {
497 struct rk628_pin_bank *bank = gpiochip_get_data(gc);
498 int virq;
499
500 if (!bank->domain)
501 return -ENXIO;
502
503 virq = irq_create_mapping(bank->domain, offset);
504 if (!virq)
505 pr_err("map interruptr fail, bank->irq=%d\n", bank->irq);
506
507 return (virq) ? : -ENXIO;
508 }
509
510 static struct gpio_chip rk628_gpiolib_chip = {
511 .label = "rk628-gpio",
512 .request = gpiochip_generic_request,
513 .free = gpiochip_generic_free,
514 .get_direction = rk628_gpio_get_direction,
515 .get = rk628_gpio_get,
516 .set = rk628_gpio_set,
517 .direction_input = rk628_gpio_direction_input,
518 .direction_output = rk628_gpio_direction_output,
519 .to_irq = rk628_gpio_to_irq,
520 .can_sleep = true,
521 .base = -1,
522 .owner = THIS_MODULE,
523 };
524
525 /* generic pinctrl */
rk628_pinctrl_get_groups_count(struct pinctrl_dev * pctldev)526 static int rk628_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
527 {
528 struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
529
530 return pci->num_groups;
531 }
532
rk628_pinctrl_get_group_name(struct pinctrl_dev * pctldev,unsigned int group)533 static const char *rk628_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
534 unsigned int group)
535 {
536 struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
537
538 return pci->groups[group].name;
539 }
540
rk628_pinctrl_get_group_pins(struct pinctrl_dev * pctldev,unsigned int group,const unsigned int ** pins,unsigned int * num_pins)541 static int rk628_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
542 unsigned int group,
543 const unsigned int **pins,
544 unsigned int *num_pins)
545 {
546 struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
547
548 *pins = pci->groups[group].pins;
549 *num_pins = pci->groups[group].npins;
550
551 return 0;
552 }
553
554 static const struct pinctrl_ops rk628_pinctrl_ops = {
555 .get_groups_count = rk628_pinctrl_get_groups_count,
556 .get_group_name = rk628_pinctrl_get_group_name,
557 .get_group_pins = rk628_pinctrl_get_group_pins,
558 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
559 .dt_free_map = pinctrl_utils_free_map,
560 };
561
rk628_pinctrl_get_funcs_count(struct pinctrl_dev * pctldev)562 static int rk628_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
563 {
564 struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
565
566 return pci->num_functions;
567 }
568
rk628_pinctrl_get_func_name(struct pinctrl_dev * pctldev,unsigned int function)569 static const char *rk628_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
570 unsigned int function)
571 {
572 struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
573
574 return pci->functions[function].name;
575 }
576
rk628_pinctrl_get_func_groups(struct pinctrl_dev * pctldev,unsigned int function,const char * const ** groups,unsigned int * const num_groups)577 static int rk628_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
578 unsigned int function,
579 const char *const **groups,
580 unsigned int *const num_groups)
581 {
582 struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
583
584 *groups = pci->functions[function].groups;
585 *num_groups = pci->functions[function].ngroups;
586
587 return 0;
588 }
589
rk628_calc_mux_offset(struct rk628_pctrl_info * pci,int mux,int reg,int offset)590 static int rk628_calc_mux_offset(struct rk628_pctrl_info *pci, int mux, int reg, int offset)
591 {
592 int val = 0, orig;
593
594 switch (reg) {
595 case GRF_SYSTEM_CON3:
596 regmap_read(pci->grf_regmap, reg, &orig);
597 if (mux)
598 val = BIT(offset) | orig;
599 else
600 val = ~BIT(offset) & orig;
601 break;
602 case GRF_GPIO0AB_SEL_CON:
603 if (offset >= 4 && offset < 8) {
604 offset += offset - 4;
605 val = 0x3 << (offset + 16) | (mux ? BIT(offset) : 0);
606 } else if (offset > 7) {
607 offset += 4;
608 val = BIT(offset + 16) | (mux ? BIT(offset) : 0);
609 } else {
610 val = BIT(offset + 16) | (mux ? BIT(offset) : 0);
611 }
612 break;
613 case GRF_GPIO1AB_SEL_CON:
614 if (offset == 13)
615 offset++;
616 if (offset > 11)
617 val = 0x3 << (offset + 16) | (mux ? BIT(offset) : 0);
618 else
619 val = BIT(offset + 16) | (mux ? BIT(offset) : 0);
620 break;
621 case GRF_GPIO2AB_SEL_CON:
622 val = BIT(offset + 16) | (mux ? BIT(offset) : 0);
623 break;
624 case GRF_GPIO2C_SEL_CON:
625 offset -= 16;
626 val = 0x3 << ((offset*2) + 16) | (mux ? BIT(offset*2) : 0);
627 break;
628 case GRF_GPIO3AB_SEL_CON:
629 if (offset > 11)
630 val = 0x3 << (offset + 16) | (mux ? BIT(offset) : 0);
631 else
632 val = BIT(offset + 16) | (mux ? BIT(offset) : 0);
633 break;
634 default:
635 break;
636 }
637
638 return val;
639 }
640
rk628_pinctrl_set_mux(struct pinctrl_dev * pctldev,unsigned int func_selector,unsigned int group_selector)641 static int rk628_pinctrl_set_mux(struct pinctrl_dev *pctldev,
642 unsigned int func_selector,
643 unsigned int group_selector)
644 {
645 struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
646 int ret, val;
647 int mux = pci->functions[func_selector].mux_option;
648 int offset = pci->groups[group_selector].pins[0] % BANK_OFFSET;
649 int reg = pci->groups[group_selector].iomux_base;
650
651 dev_dbg(pci->dev, "functions[%d]:%s mux=%s\n",
652 func_selector, pci->functions[func_selector].name,
653 mux ? "func" : "gpio");
654
655 val = rk628_calc_mux_offset(pci, mux, reg, offset);
656
657 dev_dbg(pci->dev, "groups[%d]:%s pin-number=%d reg=0x%x write-val=0x%8x\n",
658 group_selector,
659 pci->groups[group_selector].name,
660 pci->groups[group_selector].pins[0],
661 reg, val);
662
663 ret = regmap_write(pci->grf_regmap, reg, val);
664 if (ret)
665 dev_err(pci->dev, "%s regmap write failed!\n", __func__);
666
667 return ret;
668 }
669
rk628_pmx_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset,bool input)670 static int rk628_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
671 struct pinctrl_gpio_range *range,
672 unsigned int offset, bool input)
673 {
674 struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
675 struct gpio_chip *chip;
676 struct rk628_pin_bank *bank;
677 int pin_offset, dir_reg, val, ret;
678
679 chip = range->gc;
680 bank = gpiochip_get_data(chip);
681 pin_offset = offset - range->pin_base;
682
683 if (pin_offset / 16) {
684 dir_reg = bank->reg_base + GPIO_SWPORT_DDR_H;
685 pin_offset -= 16;
686 } else {
687 dir_reg = bank->reg_base + GPIO_SWPORT_DDR_L;
688 }
689 if (input)
690 val = BIT(pin_offset + 16) | (0xffff & ~BIT(pin_offset));
691 else
692 val = BIT(pin_offset + 16) | BIT(pin_offset);
693
694 clk_enable(bank->clk);
695 ret = regmap_write(pci->regmap, dir_reg, val);
696 if (ret)
697 dev_err(pci->dev, "regmap update failed!\n");
698 clk_disable(bank->clk);
699
700 return 0;
701 }
702
703 static const struct pinmux_ops rk628_pinmux_ops = {
704 .get_functions_count = rk628_pinctrl_get_funcs_count,
705 .get_function_name = rk628_pinctrl_get_func_name,
706 .get_function_groups = rk628_pinctrl_get_func_groups,
707 .set_mux = rk628_pinctrl_set_mux,
708 .gpio_set_direction = rk628_pmx_gpio_set_direction,
709 };
710
rk628_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)711 static int rk628_pinconf_get(struct pinctrl_dev *pctldev,
712 unsigned int pin, unsigned long *config)
713 {
714 struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
715 enum pin_config_param param = pinconf_to_config_param(*config);
716 u32 arg = 0;
717
718 pr_err("no support %s\n", __func__);
719
720 switch (param) {
721 case PIN_CONFIG_OUTPUT:
722 break;
723 default:
724 dev_err(pci->dev, "Properties not supported\n");
725 return -ENOTSUPP;
726 }
727
728 *config = pinconf_to_config_packed(param, (u16)arg);
729
730 return 0;
731 }
732
rk628_set_slew_rate(struct rk628_pctrl_info * pci,int pin,int speed)733 static int rk628_set_slew_rate(struct rk628_pctrl_info *pci, int pin, int speed)
734 {
735 int gpio = pin;
736
737 /* gpio0b_sl(0-3) gpio1b_sl(0-3 -5) gpio3a_sl(4-7)*/
738 char valid_gpio[] = {
739 8,
740 9,
741 10,
742 11,
743 32 + 8,
744 32 + 9,
745 32 + 10,
746 32 + 11,
747 32 + 12,
748 32 + 13,
749 -1, -1,
750 96 + 4,
751 96 + 5,
752 96 + 6,
753 96 + 7
754 };
755
756
757 int val, ret, offset = 0xff;
758 u32 i;
759
760 for (i = 0; i < sizeof(valid_gpio); i++) {
761 if (gpio == valid_gpio[i]) {
762 offset = i;
763 break;
764 }
765 }
766
767 if (offset == 0xff) {
768 dev_err(pci->dev, "pin%u don't support set slew rate\n", pin);
769 return -EINVAL;
770 }
771
772 if (speed)
773 val = BIT(offset + 16) | BIT(offset);
774 else
775 val = BIT(offset + 16);
776
777 dev_dbg(pci->dev, " offset=%d 0x%x\n", offset, val);
778
779 ret = regmap_write(pci->grf_regmap, GRF_GPIO_SR_CON, val);
780 if (ret)
781 dev_err(pci->dev, "%s:regmap write failed! pin%u\n",
782 __func__, pin);
783
784 return ret;
785 }
786
rk628_calc_pull_reg_and_value(struct rk628_pctrl_info * pci,int pin,int pull,int * reg,int * val)787 static int rk628_calc_pull_reg_and_value(struct rk628_pctrl_info *pci,
788 int pin,
789 int pull,
790 int *reg,
791 int *val)
792 {
793 struct pinctrl_gpio_range *range = pinctrl_find_gpio_range_from_pin(pci->pctl, pin);
794 int gpio2_regs[] = { GRF_GPIO2A_P_CON, GRF_GPIO2B_P_CON, GRF_GPIO2C_P_CON };
795 int gpio3_regs[] = { GRF_GPIO3A_P_CON, GRF_GPIO3B_P_CON };
796 int valid_pinnum[] = { 8, 8, 24, 13 };
797 int offset = pin - range->pin_base;
798
799 switch (range->id) {
800 case 0:
801 if (pull == GPIO_PULL_UP) {
802 dev_err(pci->dev, "pin%u don't support pull up!\n",
803 pin);
804 return -EINVAL;
805 }
806
807 if (offset == 2) {
808 dev_err(pci->dev, "pin%u don't support pull!\n",
809 pin);
810 return -EINVAL;
811 }
812
813 if (offset < valid_pinnum[range->id]) {
814 *val = 0x3 << (2 * offset + 16) | pull << (2 * offset);
815 *reg = GRF_GPIO0A_P_CON;
816 dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
817 pin, *reg, *val);
818 return 0;
819 }
820 break;
821 case 1:
822 if (pull == GPIO_PULL_UP) {
823 dev_err(pci->dev, "pin%u don't support pull up!\n",
824 pin);
825 return -EINVAL;
826 }
827
828 if (offset == 2) {
829 dev_err(pci->dev, "pin%u don't support pull!\n",
830 pin);
831 return -EINVAL;
832 }
833
834 if (offset < valid_pinnum[range->id]) {
835 *val = 0x3 << (2 * offset + 16) | pull << (2 * offset);
836 *reg = GRF_GPIO1A_P_CON;
837 dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
838 pin, *reg, *val);
839 return 0;
840 }
841 break;
842 case 2:
843 if (pull == GPIO_PULL_UP)
844 pull = GPIO_PULL_DOWN;
845 else if (pull == GPIO_PULL_DOWN)
846 pull = GPIO_PULL_UP;
847
848 if (offset < valid_pinnum[range->id]) {
849 *reg = gpio2_regs[offset / 8];
850 offset = offset % 8;
851 *val = 0x3 << (2 * offset + 16) | pull << (2 * offset);
852 dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
853 pin, *reg, *val);
854 return 0;
855 }
856 break;
857 case 3:
858 if (pull == GPIO_PULL_UP && (offset == 2 || offset == 11 || offset == 12)) {
859 dev_err(pci->dev, "pin%u don't support pull up!\n",
860 pin);
861 return -EINVAL;
862 } else if (pull == GPIO_PULL_DOWN && (offset == 9 || offset == 10)) {
863 dev_err(pci->dev, "pin%u don't support pull down!\n",
864 pin);
865 return -EINVAL;
866 }
867
868 if (offset == 0 || offset == 1 || offset == 3 || offset == 8) {
869 if (pull == GPIO_PULL_UP)
870 pull = GPIO_PULL_DOWN;
871 else if (pull == GPIO_PULL_DOWN)
872 pull = GPIO_PULL_UP;
873 }
874
875 if ((offset > 7 && offset < valid_pinnum[range->id]) || offset < 4) {
876 *reg = gpio3_regs[offset / 8];
877 offset = offset % 8;
878 *val = 0x3 << (2 * offset + 16) | pull << (2 * offset);
879 dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
880 pin, *reg, *val);
881 return 0;
882 }
883 break;
884 default:
885 break;
886 }
887
888 return -EINVAL;
889 }
890
rk628_calc_strength_reg_and_value(struct rk628_pctrl_info * pci,int pin,int strength,int * reg,int * val)891 static int rk628_calc_strength_reg_and_value(struct rk628_pctrl_info *pci,
892 int pin,
893 int strength,
894 int *reg,
895 int *val)
896 {
897 struct pinctrl_gpio_range *range = pinctrl_find_gpio_range_from_pin(pci->pctl, pin);
898 int valid_pinnum[] = { 8, 8, 24, 9 };
899 int gpio_regs[][6] = {
900 { GRF_GPIO0B_D_CON
901 },
902 { GRF_GPIO1B_D_CON
903 },
904 {
905 GRF_GPIO2A_D0_CON, GRF_GPIO2A_D1_CON,
906 GRF_GPIO2B_D0_CON, GRF_GPIO2B_D1_CON,
907 GRF_GPIO2C_D0_CON, GRF_GPIO2C_D1_CON
908 },
909 {
910 GRF_GPIO3A_D0_CON, GRF_GPIO3A_D1_CON,
911 GRF_GPIO3B_D_CON
912 }
913 };
914 int offset = pin - range->pin_base;
915
916 switch (range->id) {
917 case 0:
918 case 1:
919 if (offset < valid_pinnum[range->id]) {
920 dev_err(pci->dev, "pin%u don't support driver strength settings!\n",
921 pin);
922 return -EINVAL;
923 }
924
925 offset -= valid_pinnum[range->id];
926
927 *val = 0x3 << (2 * offset + 16) | strength << (2 * offset);
928 *reg = gpio_regs[range->id][0];
929 dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
930 pin, *reg, *val);
931 return 0;
932 case 2:
933 case 3:
934 if (offset < valid_pinnum[range->id]) {
935 *reg = gpio_regs[range->id][offset / 4];
936 offset = offset % 4;
937 *val = 0x7 << (4 * offset + 16) | strength << (4 * offset);
938 dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
939 pin, *reg, *val);
940 return 0;
941 }
942 break;
943 default:
944 break;
945 }
946
947 return -EINVAL;
948 }
949
rk628_calc_schmitt_reg_and_value(struct rk628_pctrl_info * pci,int pin,int enable,int * reg,int * val)950 static int rk628_calc_schmitt_reg_and_value(struct rk628_pctrl_info *pci,
951 int pin,
952 int enable,
953 int *reg,
954 int *val)
955 {
956 struct pinctrl_gpio_range *range = pinctrl_find_gpio_range_from_pin(pci->pctl, pin);
957 int gpio2_regs[] = {GRF_GPIO2A_SMT, GRF_GPIO2B_SMT, GRF_GPIO2C_SMT};
958 int gpio3_reg = GRF_GPIO3AB_SMT;
959 int valid_pinnum[] = { 0, 0, 24, 9 };
960 int offset = pin - range->pin_base;
961
962 switch (range->id) {
963 case 0:
964 case 1:
965 break;
966 case 2:
967 if (offset < valid_pinnum[range->id]) {
968 *reg = gpio2_regs[offset / 8];
969 offset = offset % 8;
970 *val = BIT(offset + 16) | enable << (offset);
971 dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
972 pin, *reg, *val);
973 return 0;
974 }
975 break;
976 case 3:
977 if (offset == 0 || offset == 1 || offset == 3 || offset == 8) {
978 *reg = gpio3_reg;
979 *val = BIT(offset + 16) | enable << (offset);
980 dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
981 pin, *reg, *val);
982 return 0;
983 }
984 break;
985 default:
986 break;
987 }
988
989 dev_err(pci->dev, "pin%u don't support schmitt settings!\n",
990 pin);
991
992 return -ENOTSUPP;
993 }
994
rk628_set_pull(struct rk628_pctrl_info * pci,int pin,int pull)995 static int rk628_set_pull(struct rk628_pctrl_info *pci, int pin, int pull)
996 {
997 int ret, reg, val;
998
999 ret = rk628_calc_pull_reg_and_value(pci, pin, pull, ®, &val);
1000 if (ret) {
1001 dev_err(pci->dev, "pin%u can not find reg or not support!\n", pin);
1002 return ret;
1003 }
1004
1005 ret = regmap_write(pci->grf_regmap, reg, val);
1006
1007 if (ret)
1008 dev_err(pci->dev, "%s:regmap write failed! pin%u\n",
1009 __func__, pin);
1010
1011 return ret;
1012 }
1013
rk628_set_drive_perpin(struct rk628_pctrl_info * pci,int pin,int strength)1014 static int rk628_set_drive_perpin(struct rk628_pctrl_info *pci, int pin, int strength)
1015 {
1016 int ret, reg, val;
1017
1018 ret = rk628_calc_strength_reg_and_value(pci, pin, strength, ®, &val);
1019 if (ret) {
1020 dev_err(pci->dev, "pin%u can not find reg or not support!\n", pin);
1021 return ret;
1022 }
1023
1024 ret = regmap_write(pci->grf_regmap, reg, val);
1025
1026 if (ret)
1027 dev_err(pci->dev, "%s:regmap write failed! pin%u\n",
1028 __func__, pin);
1029
1030 return ret;
1031 }
1032
rk628_set_schmitt(struct rk628_pctrl_info * pci,int pin,int enable)1033 static int rk628_set_schmitt(struct rk628_pctrl_info *pci, int pin, int enable)
1034 {
1035 int ret, reg, val;
1036
1037 ret = rk628_calc_schmitt_reg_and_value(pci, pin, enable, ®, &val);
1038 if (ret) {
1039 dev_err(pci->dev, "pin%u can not find reg or not support!\n", pin);
1040 return ret;
1041 }
1042
1043 ret = regmap_write(pci->grf_regmap, reg, val);
1044
1045 if (ret)
1046 dev_err(pci->dev, "%s:regmap write failed! pin%u\n",
1047 __func__, pin);
1048
1049 return ret;
1050 }
1051
rk628_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)1052 static int rk628_pinconf_set(struct pinctrl_dev *pctldev,
1053 unsigned int pin, unsigned long *configs,
1054 unsigned int num_configs)
1055 {
1056 struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
1057 enum pin_config_param param;
1058 u32 i, arg = 0;
1059
1060 for (i = 0; i < num_configs; i++) {
1061 param = pinconf_to_config_param(configs[i]);
1062 arg = pinconf_to_config_argument(configs[i]);
1063
1064 switch (param) {
1065 case PIN_CONFIG_DRIVE_STRENGTH:
1066 rk628_set_drive_perpin(pci, pin, arg);
1067 break;
1068 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1069 rk628_set_pull(pci, pin, GPIO_HIGH_Z);
1070 break;
1071 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1072 dev_err(pci->dev,
1073 "PIN_CONFIG_BIAS_PULL_PIN_DEFAULT not supported\n");
1074 break;
1075 case PIN_CONFIG_BIAS_PULL_UP:
1076 rk628_set_pull(pci, pin, GPIO_PULL_UP);
1077 break;
1078 case PIN_CONFIG_BIAS_PULL_DOWN:
1079 rk628_set_pull(pci, pin, GPIO_PULL_DOWN);
1080 break;
1081 case PIN_CONFIG_SLEW_RATE:
1082 rk628_set_slew_rate(pci, pin, arg);
1083 break;
1084 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1085 rk628_set_schmitt(pci, pin, arg);
1086 break;
1087 case PIN_CONFIG_OUTPUT:
1088 {
1089 struct pinctrl_gpio_range *range = pinctrl_find_gpio_range_from_pin(pci->pctl, pin);
1090
1091 rk628_gpio_direction_output(range->gc, pin - range->pin_base, arg);
1092 break;
1093 }
1094 default:
1095 dev_err(pci->dev, "Properties not supported param=%d\n", param);
1096 break;
1097 }
1098 }
1099
1100 return 0;
1101 }
1102
1103 static const struct pinconf_ops rk628_pinconf_ops = {
1104 .pin_config_get = rk628_pinconf_get,
1105 .pin_config_set = rk628_pinconf_set,
1106 };
1107
1108 static struct pinctrl_desc rk628_pinctrl_desc = {
1109 .name = "rk628-pinctrl",
1110 .pctlops = &rk628_pinctrl_ops,
1111 .pmxops = &rk628_pinmux_ops,
1112 .confops = &rk628_pinconf_ops,
1113 .owner = THIS_MODULE,
1114 };
1115
rk628_pinctrl_create_function(struct device * dev,struct rk628_pctrl_info * pci,struct device_node * func_np,struct rk628_pin_function * func)1116 static int rk628_pinctrl_create_function(struct device *dev,
1117 struct rk628_pctrl_info *pci,
1118 struct device_node *func_np,
1119 struct rk628_pin_function *func)
1120 {
1121 int npins;
1122 int ret;
1123 int i;
1124 char *func_sel[6] = {
1125 "vop_dclk0", "i2sm0_input", "rxdcc_input0", "hdmirx_cec0",
1126 "force_jtag_dis", "uart_iomux_dis",
1127 };
1128
1129 if (of_property_read_string(func_np, "function", &func->name))
1130 return -1;
1131
1132 func->mux_option = PINMUX_FUNC1;
1133 /* for signals input select */
1134 for (i = 0; i < 6; i++) {
1135 if (!strcmp(func_sel[i], func->name))
1136 func->mux_option = PINMUX_FUNC0;
1137 }
1138
1139 dev_dbg(dev, "%s func->name=%s\n", __func__, func->name);
1140 npins = of_property_count_strings(func_np, "pins");
1141 if (npins < 1) {
1142 dev_err(dev, "invalid pin list in %s node", func_np->name);
1143 return -EINVAL;
1144 }
1145
1146 func->groups = devm_kzalloc(dev, npins * sizeof(char *), GFP_KERNEL);
1147 if (!func->groups)
1148 return -ENOMEM;
1149
1150 for (i = 0; i < npins; ++i) {
1151 const char *gname;
1152
1153 ret = of_property_read_string_index(func_np,
1154 "pins", i, &gname);
1155 if (ret) {
1156 dev_err(dev,
1157 "failed to read pin name %d from %s node\n",
1158 i, func_np->name);
1159 return ret;
1160 }
1161 dev_dbg(dev, "%s func->groups[%d]=%s\n", __func__, i, gname);
1162
1163 func->groups[i] = gname;
1164 }
1165
1166 func->ngroups = npins;
1167 return 0;
1168 }
1169
rk628_pinctrl_parse_gpiobank(struct device * dev,struct rk628_pctrl_info * pci)1170 static int rk628_pinctrl_parse_gpiobank(struct device *dev,
1171 struct rk628_pctrl_info *pci)
1172 {
1173 struct device_node *dev_np = dev->of_node;
1174 struct device_node *cfg_np;
1175 struct rk628_pin_bank *bank;
1176 u32 i, count = 0;
1177
1178 for_each_child_of_node(dev_np, cfg_np) {
1179 if (of_get_child_count(cfg_np))
1180 continue;
1181 if (!of_find_property(cfg_np, "gpio-controller", NULL))
1182 continue;
1183 bank = pci->pin_banks;
1184 for (i = 0; i < pci->nr_banks; ++i, ++bank) {
1185 if (strcmp(bank->name, cfg_np->name))
1186 continue;
1187 bank->of_node = cfg_np;
1188 count++;
1189 bank->clk = devm_get_clk_from_child(dev,
1190 bank->of_node,
1191 "pclk");
1192 if (IS_ERR(bank->clk))
1193 return PTR_ERR(bank->clk);
1194 clk_prepare(bank->clk);
1195 break;
1196 }
1197 if (count == pci->nr_banks)
1198 break;
1199 }
1200
1201 return 0;
1202 }
1203
1204 static struct rk628_pin_function *
rk628_pinctrl_create_functions(struct device * dev,struct rk628_pctrl_info * pci,unsigned int * cnt)1205 rk628_pinctrl_create_functions(struct device *dev,
1206 struct rk628_pctrl_info *pci,
1207 unsigned int *cnt)
1208 {
1209 struct rk628_pin_function *functions, *func;
1210 struct device_node *dev_np = dev->of_node;
1211 struct device_node *cfg_np;
1212 unsigned int func_cnt = 0;
1213 const char *func_name;
1214 int ret;
1215
1216 /*
1217 * Iterate over all the child nodes of the pin controller node
1218 * and create pin groups and pin function lists.
1219 */
1220 for_each_child_of_node(dev_np, cfg_np) {
1221 if (!of_get_child_count(cfg_np)) {
1222 if (!of_find_property(cfg_np, "function", NULL))
1223 continue;
1224 if (!of_property_read_string(cfg_np,
1225 "function", &func_name)) {
1226 if (!strncmp("gpio", func_name, 4))
1227 continue;
1228 }
1229 dev_dbg(dev, "%s: count=%d %s\n",
1230 __func__, func_cnt, func_name);
1231 ++func_cnt;
1232 continue;
1233 }
1234 }
1235
1236 ++func_cnt;
1237 dev_dbg(dev, "total_count=%d, count %d for gpio function.\n",
1238 func_cnt, func_cnt - 1);
1239 functions = devm_kzalloc(dev, func_cnt * sizeof(*functions),
1240 GFP_KERNEL);
1241 if (!functions)
1242 return ERR_PTR(-ENOMEM);
1243
1244 func = functions;
1245
1246 /*
1247 * Iterate over all the child nodes of the pin controller node
1248 * and create pin groups and pin function lists.
1249 */
1250 func_cnt = 0;
1251 for_each_child_of_node(dev_np, cfg_np) {
1252 if (!of_get_child_count(cfg_np)) {
1253 if (!of_property_read_string(cfg_np,
1254 "function", &func_name)) {
1255 if (!strncmp("gpio", func_name, 4))
1256 continue;
1257 }
1258 ret = rk628_pinctrl_create_function(dev, pci,
1259 cfg_np, func);
1260 if (!ret) {
1261 ++func;
1262 ++func_cnt;
1263 }
1264 continue;
1265 }
1266 }
1267
1268 /* init gpio func */
1269 *(func) = rk628_functions[MUX_GPIO];
1270 func->mux_option = PINMUX_FUNC0;
1271
1272 dev_dbg(dev, "count %d is for %s function\n", func_cnt, func->name);
1273 ++func;
1274 ++func_cnt;
1275 *cnt = func_cnt;
1276 return functions;
1277 }
1278
rk628_pinctrl_parse_dt(struct platform_device * pdev,struct rk628_pctrl_info * pci)1279 static int rk628_pinctrl_parse_dt(struct platform_device *pdev,
1280 struct rk628_pctrl_info *pci)
1281 {
1282 struct device *dev = &pdev->dev;
1283 struct rk628_pin_function *functions;
1284 unsigned int func_cnt = 0;
1285 int ret;
1286
1287 ret = rk628_pinctrl_parse_gpiobank(dev, pci);
1288 if (ret)
1289 return ret;
1290
1291 functions = rk628_pinctrl_create_functions(dev, pci, &func_cnt);
1292 if (IS_ERR(functions)) {
1293 dev_err(dev, "failed to parse pin functions\n");
1294 return PTR_ERR(functions);
1295 }
1296
1297 pci->functions = functions;
1298 pci->num_functions = func_cnt;
1299 return 0;
1300 }
1301
1302 static const struct regmap_range rk628_pinctrl_readable_ranges[] = {
1303 regmap_reg_range(GPIO0_BASE, GPIO0_BASE + GPIO_VER_ID),
1304 regmap_reg_range(GPIO1_BASE, GPIO1_BASE + GPIO_VER_ID),
1305 regmap_reg_range(GPIO2_BASE, GPIO2_BASE + GPIO_VER_ID),
1306 regmap_reg_range(GPIO3_BASE, GPIO3_BASE + GPIO_VER_ID),
1307 };
1308
1309 static const struct regmap_access_table rk628_pinctrl_readable_table = {
1310 .yes_ranges = rk628_pinctrl_readable_ranges,
1311 .n_yes_ranges = ARRAY_SIZE(rk628_pinctrl_readable_ranges),
1312 };
1313
1314 static const struct regmap_config rk628_pinctrl_regmap_config = {
1315 .name = "pinctrl",
1316 .reg_bits = 32,
1317 .val_bits = 32,
1318 .reg_stride = 4,
1319 .max_register = GPIO_MAX_REGISTER,
1320 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
1321 .val_format_endian = REGMAP_ENDIAN_LITTLE,
1322 .rd_table = &rk628_pinctrl_readable_table,
1323 };
1324
rk628_irq_enable(struct irq_data * d)1325 static void rk628_irq_enable(struct irq_data *d)
1326 {
1327 struct rk628_pin_bank *bank = irq_data_get_irq_chip_data(d);
1328 unsigned long hwirq = d->hwirq;
1329 u32 offset;
1330
1331 if (hwirq / 16) {
1332 hwirq = hwirq - 16;
1333 offset = GPIO_REG_HIGH;
1334 } else {
1335 offset = GPIO_REG_LOW;
1336 }
1337
1338 bank->mask_regs[offset] |= BIT(hwirq);
1339 }
1340
rk628_irq_disable(struct irq_data * d)1341 static void rk628_irq_disable(struct irq_data *d)
1342 {
1343 struct rk628_pin_bank *bank = irq_data_get_irq_chip_data(d);
1344 unsigned long hwirq = d->hwirq;
1345 u32 offset;
1346
1347 if (hwirq / 16) {
1348 hwirq = hwirq - 16;
1349 offset = GPIO_REG_HIGH;
1350 } else {
1351 offset = GPIO_REG_LOW;
1352 }
1353
1354 bank->mask_regs[offset] &= ~BIT(hwirq);
1355 }
1356
rk628_irq_set_type(struct irq_data * d,unsigned int type)1357 static int rk628_irq_set_type(struct irq_data *d, unsigned int type)
1358 {
1359 struct rk628_pin_bank *bank = irq_data_get_irq_chip_data(d);
1360 struct rk628_pctrl_info *pci = bank->pci;
1361 unsigned long hwirq = d->hwirq;
1362 u32 offset;
1363
1364 if (hwirq / 16) {
1365 hwirq = hwirq - 16;
1366 offset = GPIO_REG_HIGH;
1367 } else {
1368 offset = GPIO_REG_LOW;
1369 }
1370
1371 switch (type) {
1372 case IRQ_TYPE_EDGE_BOTH:
1373 bank->bothedge_regs[offset] |= BIT(hwirq);
1374 break;
1375 case IRQ_TYPE_EDGE_RISING:
1376 bank->bothedge_regs[offset] &= ~BIT(hwirq);
1377 bank->level_regs[offset] |= BIT(hwirq);
1378 bank->polarity_regs[offset] |= BIT(hwirq);
1379 break;
1380 case IRQ_TYPE_EDGE_FALLING:
1381 bank->bothedge_regs[offset] &= ~BIT(hwirq);
1382 bank->level_regs[offset] |= BIT(hwirq);
1383 bank->polarity_regs[offset] &= ~BIT(hwirq);
1384 break;
1385 case IRQ_TYPE_LEVEL_HIGH:
1386 bank->bothedge_regs[offset] &= ~BIT(hwirq);
1387 bank->level_regs[offset] &= ~BIT(hwirq);
1388 bank->polarity_regs[offset] |= BIT(hwirq);
1389 break;
1390 case IRQ_TYPE_LEVEL_LOW:
1391 bank->bothedge_regs[offset] &= ~BIT(hwirq);
1392 bank->level_regs[offset] &= ~BIT(hwirq);
1393 bank->polarity_regs[offset] &= ~BIT(hwirq);
1394 break;
1395 default:
1396 dev_err(pci->dev, "irq type invalid!\n");
1397 return -EINVAL;
1398 }
1399
1400 return 0;
1401 }
1402
rk628_irq_lock(struct irq_data * d)1403 static void rk628_irq_lock(struct irq_data *d)
1404 {
1405 struct rk628_pin_bank *bank = irq_data_get_irq_chip_data(d);
1406
1407 mutex_lock(&bank->lock);
1408 clk_enable(bank->clk);
1409 }
1410
rk628_irq_sync_unlock(struct irq_data * d)1411 static void rk628_irq_sync_unlock(struct irq_data *d)
1412 {
1413 struct rk628_pin_bank *bank = irq_data_get_irq_chip_data(d);
1414 struct rk628_pctrl_info *pci = bank->pci;
1415 int ret;
1416 unsigned long hwirq = d->hwirq;
1417 u32 offset, inten, level, polarity, bothedge;
1418
1419 if (hwirq / 16) {
1420 hwirq = hwirq - 16;
1421 offset = GPIO_REG_HIGH;
1422 } else {
1423 offset = GPIO_REG_LOW;
1424 }
1425
1426 inten = (bank->reg_base + GPIO_INTEN_L + ((offset) * 4));
1427 level = (bank->reg_base + GPIO_INTTYPE_L + ((offset) * 4));
1428 polarity = (bank->reg_base + GPIO_INT_POLARITY_L + ((offset) * 4));
1429 bothedge = (bank->reg_base + GPIO_INT_BOTHEDGE_L + ((offset) * 4));
1430
1431 ret = regmap_write(pci->regmap, level,
1432 bank->level_regs[offset] | BIT(hwirq + 16));
1433 if (ret)
1434 dev_err(pci->dev, "regmap read failed! reg=0x%x irq=%d\n",
1435 level, d->irq);
1436
1437 ret = regmap_write(pci->regmap, polarity,
1438 bank->polarity_regs[offset] | BIT(hwirq + 16));
1439 if (ret)
1440 dev_err(pci->dev, "regmap read failed! reg=0x%x irq=%d\n",
1441 polarity, d->irq);
1442
1443 ret = regmap_write(pci->regmap, bothedge,
1444 bank->bothedge_regs[offset] | BIT(hwirq + 16));
1445 if (ret)
1446 dev_err(pci->dev, "regmap read failed! reg=0x%x irq=%d\n",
1447 bothedge, d->irq);
1448
1449 ret = regmap_write(pci->regmap, inten,
1450 bank->mask_regs[offset] | BIT(hwirq + 16));
1451 if (ret)
1452 dev_err(pci->dev, "regmap read failed! reg=0x%x irq=%d\n",
1453 inten, d->irq);
1454
1455 clk_disable(bank->clk);
1456 mutex_unlock(&bank->lock);
1457 }
1458
1459 enum rk628_irqchip {
1460 IRQCHIP_gpio0,
1461 IRQCHIP_gpio1,
1462 IRQCHIP_gpio2,
1463 IRQCHIP_gpio3,
1464 };
1465
1466 static const struct irq_chip rk628_irq_chip[] = {
1467 IRQ_CHIP(gpio0),
1468 IRQ_CHIP(gpio1),
1469 IRQ_CHIP(gpio2),
1470 IRQ_CHIP(gpio3),
1471 };
1472
rk628_irq_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)1473 static int rk628_irq_map(struct irq_domain *h, unsigned int virq,
1474 irq_hw_number_t hw)
1475 {
1476 struct rk628_pin_bank *bank = h->host_data;
1477
1478 irq_set_chip_data(virq, bank);
1479 irq_set_chip(virq, &bank->irq_chip);
1480 irq_set_nested_thread(virq, 1);
1481 irq_set_noprobe(virq);
1482
1483 return 0;
1484 }
1485
1486 static const struct irq_domain_ops rk628_domain_ops = {
1487 .map = rk628_irq_map,
1488 .xlate = irq_domain_xlate_twocell,
1489 };
1490
rk628_irq_demux_thread(int irq,void * d)1491 static irqreturn_t rk628_irq_demux_thread(int irq, void *d)
1492 {
1493 struct rk628_pin_bank *bank = d;
1494 struct rk628_pctrl_info *pci = bank->pci;
1495 int ret;
1496 u32 pend, low_bit, high_bit;
1497
1498 clk_enable(bank->clk);
1499
1500 ret = regmap_read(pci->regmap, bank->reg_base + GPIO_INT_STATUS, &pend);
1501 if (ret)
1502 dev_err(pci->dev, "regmap read failed! line=%d\n", __LINE__);
1503
1504 low_bit = pend & 0x0000ffff;
1505 high_bit = (pend >> 16);
1506 ret = regmap_write(pci->regmap, bank->reg_base + GPIO_PORTS_EOI_L,
1507 (low_bit << 16) | low_bit);
1508 if (ret)
1509 dev_err(pci->dev, "regmap read failed! line=%d\n", __LINE__);
1510
1511 ret = regmap_write(pci->regmap, bank->reg_base + GPIO_PORTS_EOI_H,
1512 (high_bit << 16) | high_bit);
1513 if (ret)
1514 dev_err(pci->dev, "regmap read failed! line=%d\n", __LINE__);
1515
1516 while (pend) {
1517 unsigned int irq, virq;
1518
1519 irq = __ffs(pend);
1520 pend &= ~BIT(irq);
1521 virq = irq_linear_revmap(bank->domain, irq);
1522
1523 if (!virq) {
1524 dev_err(pci->dev, "unmapped irq %d\n", irq);
1525 continue;
1526 }
1527
1528 handle_nested_irq(virq);
1529 }
1530 clk_disable(bank->clk);
1531
1532 return IRQ_HANDLED;
1533 }
1534
rk628_interrupts_register(struct platform_device * pdev,struct rk628_pctrl_info * pci)1535 static int rk628_interrupts_register(struct platform_device *pdev,
1536 struct rk628_pctrl_info *pci)
1537 {
1538 struct rk628_pin_bank *bank = pci->pin_banks;
1539 int ret;
1540 u32 i;
1541
1542 for (i = 0; i < pci->nr_banks; ++i, ++bank) {
1543 mutex_init(&bank->lock);
1544 ret = clk_enable(bank->clk);
1545 if (ret) {
1546 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
1547 bank->name);
1548 continue;
1549 }
1550
1551 bank->irq = platform_get_irq(pdev, i);
1552 bank->irq_chip = rk628_irq_chip[i];
1553 bank->domain = irq_domain_add_linear(bank->of_node,
1554 bank->nr_pins,
1555 &rk628_domain_ops,
1556 bank);
1557 if (!bank->domain) {
1558 dev_warn(&pdev->dev,
1559 "could not initialize irq domain for bank %s\n",
1560 bank->name);
1561 clk_disable(bank->clk);
1562 continue;
1563 }
1564
1565 ret = request_threaded_irq(bank->irq, NULL,
1566 rk628_irq_demux_thread,
1567 IRQF_ONESHOT,
1568 bank->name, bank);
1569 if (ret != 0) {
1570 dev_err(&pdev->dev,
1571 "Failed to request IRQ %d for %s: %d\n",
1572 bank->irq, bank->name, ret);
1573 }
1574
1575 clk_disable(bank->clk);
1576 }
1577
1578 return 0;
1579 }
1580
rk628_gpiolib_register(struct platform_device * pdev,struct rk628_pctrl_info * pci)1581 static int rk628_gpiolib_register(struct platform_device *pdev,
1582 struct rk628_pctrl_info *pci)
1583 {
1584 struct rk628_pin_bank *bank = pci->pin_banks;
1585 struct gpio_chip *gc;
1586 int ret = 0, i;
1587
1588 for (i = 0; i < pci->nr_banks; ++i, ++bank) {
1589 bank->gpio_chip = rk628_gpiolib_chip;
1590 bank->pci = pci;
1591 gc = &bank->gpio_chip;
1592 gc->base = -1;
1593 gc->ngpio = bank->nr_pins;
1594 gc->parent = &pdev->dev;
1595 gc->of_node = bank->of_node;
1596 gc->label = bank->name;
1597
1598 ret = devm_gpiochip_add_data(&pdev->dev, gc, bank);
1599 if (ret) {
1600 dev_err(&pdev->dev,
1601 "failed to register gpio_chip %s, error code: %d\n",
1602 gc->label, ret);
1603 }
1604 }
1605
1606 return ret;
1607 }
1608
rk628_pinctrl_probe(struct platform_device * pdev)1609 static int rk628_pinctrl_probe(struct platform_device *pdev)
1610 {
1611 struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
1612 struct device *dev = &pdev->dev;
1613 struct rk628_pctrl_info *pci;
1614 int ret;
1615 u32 bank;
1616 struct rk628_pin_bank *pin_bank;
1617
1618 pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL);
1619 if (!pci)
1620 return -ENOMEM;
1621
1622 pci->dev = &pdev->dev;
1623 pci->grf_regmap = rk628->grf;
1624
1625 pci->pinctrl_desc = rk628_pinctrl_desc;
1626 pci->groups = rk628_pin_groups;
1627 pci->num_groups = ARRAY_SIZE(rk628_pin_groups);
1628 pci->pinctrl_desc.pins = rk628_pins_desc;
1629 pci->pinctrl_desc.npins = ARRAY_SIZE(rk628_pins_desc);
1630 pci->pin_banks = rk628_pin_banks;
1631 pci->nr_banks = ARRAY_SIZE(rk628_pin_banks),
1632
1633 platform_set_drvdata(pdev, pci);
1634
1635 ret = rk628_pinctrl_parse_dt(pdev, pci);
1636 if (ret < 0)
1637 return ret;
1638
1639 pci->regmap = devm_regmap_init_i2c(rk628->client,
1640 &rk628_pinctrl_regmap_config);
1641 if (IS_ERR(pci->regmap)) {
1642 ret = PTR_ERR(pci->regmap);
1643 dev_err(dev, "failed to allocate register map: %d\n", ret);
1644 return ret;
1645 }
1646
1647 /* Add gpiochip */
1648 ret = rk628_gpiolib_register(pdev, pci);
1649 if (ret < 0) {
1650 dev_err(&pdev->dev, "Couldn't add gpiochip\n");
1651 return ret;
1652 }
1653
1654 /* Add pinctrl */
1655 pci->pctl = devm_pinctrl_register(&pdev->dev, &pci->pinctrl_desc, pci);
1656 if (IS_ERR(pci->pctl)) {
1657 dev_err(&pdev->dev, "Couldn't add pinctrl\n");
1658 return PTR_ERR(pci->pctl);
1659 }
1660
1661 for (bank = 0; bank < pci->nr_banks; ++bank) {
1662 pin_bank = &pci->pin_banks[bank];
1663 pin_bank->grange.name = pin_bank->name;
1664 pin_bank->grange.id = bank;
1665 pin_bank->grange.pin_base = BANK_OFFSET * bank;
1666 pin_bank->grange.base = pin_bank->gpio_chip.base;
1667 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1668 pin_bank->grange.gc = &pin_bank->gpio_chip;
1669 pinctrl_add_gpio_range(pci->pctl, &pin_bank->grange);
1670 }
1671
1672 rk628_interrupts_register(pdev, pci);
1673
1674 return 0;
1675 }
1676
1677 static const struct of_device_id rk628_pinctrl_dt_match[] = {
1678 { .compatible = "rockchip,rk628-pinctrl" },
1679 {},
1680 };
1681
1682 MODULE_DEVICE_TABLE(of, rk628_pinctrl_dt_match);
1683
1684 static struct platform_driver rk628_pinctrl_driver = {
1685 .probe = rk628_pinctrl_probe,
1686 .driver = {
1687 .name = "rk628-pinctrl",
1688 .of_match_table = of_match_ptr(rk628_pinctrl_dt_match),
1689 },
1690 };
1691
1692 module_platform_driver(rk628_pinctrl_driver);
1693
1694 MODULE_DESCRIPTION("RK628 pin control and GPIO driver");
1695 MODULE_AUTHOR("Weixin Zhou <zwx@rock-chips.com>");
1696 MODULE_LICENSE("GPL v2");
1697