1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Maxim max96755f pin control driver.
4 *
5 * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
6 */
7
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/pinctrl/pinctrl.h>
11 #include <linux/pinctrl/pinconf-generic.h>
12 #include <linux/pinctrl/pinconf.h>
13 #include <linux/pinctrl/pinmux.h>
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
16 #include <linux/mfd/max96755f.h>
17
18 #include "core.h"
19 #include "pinconf.h"
20 #include "pinmux.h"
21
22 struct max96755f_pinctrl {
23 struct device *dev;
24 struct pinctrl_dev *pctl;
25 struct regmap *regmap;
26 };
27
28 struct config_desc {
29 u16 reg;
30 u8 mask;
31 u8 val;
32 };
33
34 struct max96755f_group_data {
35 const struct config_desc *configs;
36 int num_configs;
37 };
38
39 struct max96755f_function_data {
40 u8 gpio_out_dis:1;
41 u8 gpio_tx_en:1;
42 u8 gpio_rx_en:1;
43 u8 gpio_tx_id;
44 u8 gpio_rx_id;
45 };
46
max96755f_pinmux_set_mux(struct pinctrl_dev * pctldev,unsigned int function,unsigned int group)47 static int max96755f_pinmux_set_mux(struct pinctrl_dev *pctldev,
48 unsigned int function, unsigned int group)
49 {
50 struct max96755f_pinctrl *mpctl = pinctrl_dev_get_drvdata(pctldev);
51 struct function_desc *func;
52 struct group_desc *grp;
53 int i;
54
55 func = pinmux_generic_get_function(pctldev, function);
56 if (!func)
57 return -EINVAL;
58
59 grp = pinctrl_generic_get_group(pctldev, group);
60 if (!grp)
61 return -EINVAL;
62
63 if (func->data) {
64 struct max96755f_function_data *fdata = func->data;
65
66 for (i = 0; i < grp->num_pins; i++) {
67 regmap_update_bits(mpctl->regmap, GPIO_A_REG(grp->pins[i]),
68 GPIO_OUT_DIS | GPIO_RX_EN | GPIO_TX_EN,
69 FIELD_PREP(GPIO_OUT_DIS, fdata->gpio_out_dis) |
70 FIELD_PREP(GPIO_RX_EN, fdata->gpio_rx_en) |
71 FIELD_PREP(GPIO_TX_EN, fdata->gpio_tx_en));
72
73 if (fdata->gpio_tx_en)
74 regmap_update_bits(mpctl->regmap, GPIO_B_REG(grp->pins[i]),
75 GPIO_TX_ID,
76 FIELD_PREP(GPIO_TX_ID, fdata->gpio_tx_id));
77
78 if (fdata->gpio_rx_en)
79 regmap_update_bits(mpctl->regmap, GPIO_C_REG(grp->pins[i]),
80 GPIO_RX_ID,
81 FIELD_PREP(GPIO_RX_ID, fdata->gpio_rx_id));
82 }
83 }
84
85 if (grp->data) {
86 struct max96755f_group_data *gdata = grp->data;
87
88 for (i = 0; i < gdata->num_configs; i++) {
89 const struct config_desc *config = &gdata->configs[i];
90
91 regmap_update_bits(mpctl->regmap, config->reg,
92 config->mask, config->val);
93 }
94 }
95
96 return 0;
97 }
98
max96755f_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)99 static int max96755f_pinconf_get(struct pinctrl_dev *pctldev,
100 unsigned int pin, unsigned long *config)
101 {
102 struct max96755f_pinctrl *mpctl = pinctrl_dev_get_drvdata(pctldev);
103 enum pin_config_param param = pinconf_to_config_param(*config);
104 unsigned int gpio_a_reg, gpio_b_reg;
105 u16 arg = 0;
106
107 regmap_read(mpctl->regmap, GPIO_A_REG(pin), &gpio_a_reg);
108 regmap_read(mpctl->regmap, GPIO_B_REG(pin), &gpio_b_reg);
109
110 switch (param) {
111 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
112 if (FIELD_GET(OUT_TYPE, gpio_b_reg))
113 return -EINVAL;
114 break;
115 case PIN_CONFIG_DRIVE_PUSH_PULL:
116 if (!FIELD_GET(OUT_TYPE, gpio_b_reg))
117 return -EINVAL;
118 break;
119 case PIN_CONFIG_BIAS_DISABLE:
120 if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 0)
121 return -EINVAL;
122 break;
123 case PIN_CONFIG_BIAS_PULL_UP:
124 if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 1)
125 return -EINVAL;
126 switch (FIELD_GET(RES_CFG, gpio_a_reg)) {
127 case 0:
128 arg = 40000;
129 break;
130 case 1:
131 arg = 10000;
132 break;
133 }
134 break;
135 case PIN_CONFIG_BIAS_PULL_DOWN:
136 if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 2)
137 return -EINVAL;
138 switch (FIELD_GET(RES_CFG, gpio_a_reg)) {
139 case 0:
140 arg = 40000;
141 break;
142 case 1:
143 arg = 10000;
144 break;
145 }
146 break;
147 case PIN_CONFIG_OUTPUT:
148 if (FIELD_GET(GPIO_OUT_DIS, gpio_a_reg))
149 return -EINVAL;
150
151 arg = FIELD_GET(GPIO_OUT, gpio_a_reg);
152 break;
153 default:
154 return -ENOTSUPP;
155 }
156
157 *config = pinconf_to_config_packed(param, arg);
158
159 return 0;
160 }
161
max96755f_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)162 static int max96755f_pinconf_set(struct pinctrl_dev *pctldev,
163 unsigned int pin, unsigned long *configs,
164 unsigned int num_configs)
165 {
166 struct max96755f_pinctrl *mpctl = pinctrl_dev_get_drvdata(pctldev);
167 enum pin_config_param param;
168 u32 arg;
169 u8 res_cfg;
170 int i;
171
172 for (i = 0; i < num_configs; i++) {
173 param = pinconf_to_config_param(configs[i]);
174 arg = pinconf_to_config_argument(configs[i]);
175
176 switch (param) {
177 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
178 regmap_update_bits(mpctl->regmap, GPIO_B_REG(pin),
179 OUT_TYPE, FIELD_PREP(OUT_TYPE, 0));
180 break;
181 case PIN_CONFIG_DRIVE_PUSH_PULL:
182 regmap_update_bits(mpctl->regmap, GPIO_B_REG(pin),
183 OUT_TYPE, FIELD_PREP(OUT_TYPE, 1));
184 break;
185 case PIN_CONFIG_BIAS_DISABLE:
186 regmap_update_bits(mpctl->regmap, GPIO_C_REG(pin),
187 PULL_UPDN_SEL,
188 FIELD_PREP(PULL_UPDN_SEL, 0));
189 break;
190 case PIN_CONFIG_BIAS_PULL_UP:
191 switch (arg) {
192 case 40000:
193 res_cfg = 0;
194 break;
195 case 1000000:
196 res_cfg = 1;
197 break;
198 default:
199 return -EINVAL;
200 }
201
202 regmap_update_bits(mpctl->regmap, GPIO_A_REG(pin),
203 RES_CFG, FIELD_PREP(RES_CFG, res_cfg));
204 regmap_update_bits(mpctl->regmap, GPIO_C_REG(pin),
205 PULL_UPDN_SEL,
206 FIELD_PREP(PULL_UPDN_SEL, 1));
207 break;
208 case PIN_CONFIG_BIAS_PULL_DOWN:
209 switch (arg) {
210 case 40000:
211 res_cfg = 0;
212 break;
213 case 1000000:
214 res_cfg = 1;
215 break;
216 default:
217 return -EINVAL;
218 }
219
220 regmap_update_bits(mpctl->regmap, GPIO_A_REG(pin),
221 RES_CFG, FIELD_PREP(RES_CFG, res_cfg));
222 regmap_update_bits(mpctl->regmap, GPIO_C_REG(pin),
223 PULL_UPDN_SEL,
224 FIELD_PREP(PULL_UPDN_SEL, 2));
225 break;
226 case PIN_CONFIG_OUTPUT:
227 regmap_update_bits(mpctl->regmap, GPIO_A_REG(pin),
228 GPIO_OUT_DIS | GPIO_OUT,
229 FIELD_PREP(GPIO_OUT_DIS, 0) |
230 FIELD_PREP(GPIO_OUT, arg));
231 break;
232 default:
233 return -ENOTSUPP;
234 }
235 }
236
237 return 0;
238 }
239
240 static const struct pinconf_ops max96755f_pinconf_ops = {
241 .pin_config_get = max96755f_pinconf_get,
242 .pin_config_set = max96755f_pinconf_set,
243 };
244
245 static const struct pinmux_ops max96755f_pinmux_ops = {
246 .get_functions_count = pinmux_generic_get_function_count,
247 .get_function_name = pinmux_generic_get_function_name,
248 .get_function_groups = pinmux_generic_get_function_groups,
249 .set_mux = max96755f_pinmux_set_mux,
250 };
251
252 static const struct pinctrl_ops max96755f_pinctrl_ops = {
253 .get_groups_count = pinctrl_generic_get_group_count,
254 .get_group_name = pinctrl_generic_get_group_name,
255 .get_group_pins = pinctrl_generic_get_group_pins,
256 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
257 .dt_free_map = pinconf_generic_dt_free_map,
258 };
259
260 static const struct pinctrl_pin_desc max96755f_pins_desc[] = {
261 PINCTRL_PIN(0, "MFP0"),
262 PINCTRL_PIN(1, "MFP1"),
263 PINCTRL_PIN(2, "MFP2"),
264 PINCTRL_PIN(3, "MFP3"),
265 PINCTRL_PIN(4, "MFP4"),
266 PINCTRL_PIN(5, "MFP5"),
267 PINCTRL_PIN(6, "MFP6"),
268 PINCTRL_PIN(7, "MFP7"),
269 PINCTRL_PIN(8, "MFP8"),
270 PINCTRL_PIN(9, "MFP9"),
271 PINCTRL_PIN(10, "MFP10"),
272 PINCTRL_PIN(11, "MFP11"),
273 PINCTRL_PIN(12, "MFP12"),
274 PINCTRL_PIN(13, "MFP13"),
275 PINCTRL_PIN(14, "MFP14"),
276 PINCTRL_PIN(15, "MFP15"),
277 PINCTRL_PIN(16, "MFP16"),
278 PINCTRL_PIN(17, "MFP17"),
279 PINCTRL_PIN(18, "MFP18"),
280 PINCTRL_PIN(19, "MFP19"),
281 PINCTRL_PIN(20, "MFP20"),
282 };
283
284 static int MFP0_pins[] = {0};
285 static int MFP1_pins[] = {1};
286 static int MFP2_pins[] = {2};
287 static int MFP3_pins[] = {3};
288 static int MFP4_pins[] = {4};
289 static int MFP5_pins[] = {5};
290 static int MFP6_pins[] = {6};
291 static int MFP7_pins[] = {7};
292 static int MFP8_pins[] = {8};
293 static int MFP9_pins[] = {9};
294 static int MFP10_pins[] = {10};
295 static int MFP11_pins[] = {11};
296 static int MFP12_pins[] = {12};
297 static int MFP13_pins[] = {13};
298 static int MFP14_pins[] = {14};
299 static int MFP15_pins[] = {15};
300 static int MFP16_pins[] = {16};
301 static int MFP17_pins[] = {17};
302 static int MFP18_pins[] = {18};
303 static int MFP19_pins[] = {19};
304 static int MFP20_pins[] = {20};
305 static int I2C_pins[] = {19, 20};
306 static int UART_pins[] = {19, 20};
307
308 #define GROUP_DESC(nm) \
309 { \
310 .name = #nm, \
311 .pins = nm ## _pins, \
312 .num_pins = ARRAY_SIZE(nm ## _pins), \
313 }
314
315 #define GROUP_DESC_CONFIG(nm) \
316 { \
317 .name = #nm, \
318 .pins = nm ## _pins, \
319 .num_pins = ARRAY_SIZE(nm ## _pins), \
320 .data = (void *)(const struct max96755f_group_data []) { \
321 { \
322 .configs = nm ## _configs, \
323 .num_configs = ARRAY_SIZE(nm ## _configs), \
324 } \
325 }, \
326 }
327
328 static const struct config_desc MFP0_configs[] = {
329 { 0x0005, LOCK_EN, 0 },
330 { 0x0048, LOC_MS_EN, 0},
331 };
332
333 static const struct config_desc MFP1_configs[] = {
334 { 0x0005, ERRB_EN, 0 },
335 };
336
337 static const struct config_desc MFP4_configs[] = {
338 { 0x070, SPI_EN, 0 },
339 };
340
341 static const struct config_desc MFP5_configs[] = {
342 { 0x006, RCLKEN, 0 },
343 };
344
345 static const struct config_desc MFP7_configs[] = {
346 { 0x0002, AUD_TX_EN_X, 0 },
347 { 0x0002, AUD_TX_EN_Y, 0 }
348 };
349
350 static const struct config_desc MFP8_configs[] = {
351 { 0x0002, AUD_TX_EN_X, 0 },
352 { 0x0002, AUD_TX_EN_Y, 0 }
353 };
354
355 static const struct config_desc MFP9_configs[] = {
356 { 0x0002, AUD_TX_EN_X, 0 },
357 { 0x0002, AUD_TX_EN_Y, 0 }
358 };
359
360 static const struct config_desc MFP10_configs[] = {
361 { 0x0001, IIC_2_EN, 0 },
362 { 0x0003, UART_2_EN, 0 },
363 { 0x0140, AUD_RX_EN, 0},
364 };
365
366 static const struct config_desc MFP11_configs[] = {
367 { 0x0001, IIC_2_EN, 0 },
368 { 0x0003, UART_2_EN, 0 },
369 { 0x0140, AUD_RX_EN, 0},
370 };
371
372 static const struct config_desc MFP12_configs[] = {
373 { 0x0140, AUD_RX_EN, 0 },
374 };
375
376 static const struct config_desc MFP13_configs[] = {
377 { 0x0005, PU_LF0, 0 },
378 };
379
380 static const struct config_desc MFP14_configs[] = {
381 { 0x0005, PU_LF1, 0 },
382 };
383
384 static const struct config_desc MFP15_configs[] = {
385 { 0x0005, PU_LF2, 0 },
386 };
387
388 static const struct config_desc MFP16_configs[] = {
389 { 0x0005, PU_LF3, 0 },
390 };
391
392 static const struct config_desc MFP17_configs[] = {
393 { 0x0001, IIC_1_EN, 0 },
394 { 0x0003, UART_1_EN, 0 },
395 };
396
397 static const struct config_desc MFP18_configs[] = {
398 { 0x0001, IIC_1_EN, 0 },
399 { 0x0003, UART_1_EN, 0 },
400 };
401
402 static const struct group_desc max96755f_groups[] = {
403 GROUP_DESC_CONFIG(MFP0),
404 GROUP_DESC_CONFIG(MFP1),
405 GROUP_DESC(MFP2),
406 GROUP_DESC(MFP3),
407 GROUP_DESC_CONFIG(MFP4),
408 GROUP_DESC_CONFIG(MFP5),
409 GROUP_DESC(MFP6),
410 GROUP_DESC_CONFIG(MFP7),
411 GROUP_DESC_CONFIG(MFP8),
412 GROUP_DESC_CONFIG(MFP9),
413 GROUP_DESC_CONFIG(MFP10),
414 GROUP_DESC_CONFIG(MFP11),
415 GROUP_DESC_CONFIG(MFP12),
416 GROUP_DESC_CONFIG(MFP13),
417 GROUP_DESC_CONFIG(MFP14),
418 GROUP_DESC_CONFIG(MFP15),
419 GROUP_DESC_CONFIG(MFP16),
420 GROUP_DESC_CONFIG(MFP17),
421 GROUP_DESC_CONFIG(MFP18),
422 GROUP_DESC(MFP19),
423 GROUP_DESC(MFP20),
424 GROUP_DESC(I2C),
425 GROUP_DESC(UART),
426 };
427
428 static const char *MFP_groups[] = {
429 "MFP0", "MFP1", "MFP2", "MFP3", "MFP4", "MFP5",
430 "MFP6", "MFP7", "MFP8", "MFP9", "MFP10",
431 "MFP11", "MFP12", "MFP13", "MFP14", "MFP15",
432 "MFP16", "MFP17", "MFP18", "MFP19", "MFP20",
433 };
434 static const char *I2C_groups[] = { "I2C" };
435 static const char *UART_groups[] = { "UART" };
436
437 #define FUNCTION_DESC(nm) \
438 { \
439 .name = #nm, \
440 .group_names = nm##_groups, \
441 .num_group_names = ARRAY_SIZE(nm##_groups), \
442 } \
443
444 #define FUNCTION_DESC_GPIO() \
445 { \
446 .name = "GPIO", \
447 .group_names = MFP_groups, \
448 .num_group_names = ARRAY_SIZE(MFP_groups), \
449 .data = (void *)(const struct max96755f_function_data []) { \
450 { } \
451 }, \
452 } \
453
454 #define FUNCTION_DESC_GPIO_RX(id) \
455 { \
456 .name = "GPIO_RX_"#id, \
457 .group_names = MFP_groups, \
458 .num_group_names = ARRAY_SIZE(MFP_groups), \
459 .data = (void *)(const struct max96755f_function_data []) { \
460 { .gpio_rx_en = 1, .gpio_rx_id = id } \
461 }, \
462 } \
463
464 #define FUNCTION_DESC_GPIO_TX(id) \
465 { \
466 .name = "GPIO_TX_"#id, \
467 .group_names = MFP_groups, \
468 .num_group_names = ARRAY_SIZE(MFP_groups), \
469 .data = (void *)(const struct max96755f_function_data []) { \
470 { .gpio_out_dis = 1, .gpio_tx_en = 1, .gpio_tx_id = id } \
471 }, \
472 } \
473
474 static const struct function_desc max96755f_functions[] = {
475 FUNCTION_DESC_GPIO_TX(0),
476 FUNCTION_DESC_GPIO_TX(1),
477 FUNCTION_DESC_GPIO_TX(2),
478 FUNCTION_DESC_GPIO_TX(3),
479 FUNCTION_DESC_GPIO_TX(4),
480 FUNCTION_DESC_GPIO_TX(5),
481 FUNCTION_DESC_GPIO_TX(6),
482 FUNCTION_DESC_GPIO_TX(7),
483 FUNCTION_DESC_GPIO_TX(8),
484 FUNCTION_DESC_GPIO_TX(9),
485 FUNCTION_DESC_GPIO_TX(10),
486 FUNCTION_DESC_GPIO_TX(11),
487 FUNCTION_DESC_GPIO_TX(12),
488 FUNCTION_DESC_GPIO_TX(13),
489 FUNCTION_DESC_GPIO_TX(14),
490 FUNCTION_DESC_GPIO_TX(15),
491 FUNCTION_DESC_GPIO_TX(16),
492 FUNCTION_DESC_GPIO_TX(17),
493 FUNCTION_DESC_GPIO_TX(18),
494 FUNCTION_DESC_GPIO_TX(19),
495 FUNCTION_DESC_GPIO_TX(20),
496 FUNCTION_DESC_GPIO_RX(0),
497 FUNCTION_DESC_GPIO_RX(1),
498 FUNCTION_DESC_GPIO_RX(2),
499 FUNCTION_DESC_GPIO_RX(3),
500 FUNCTION_DESC_GPIO_RX(4),
501 FUNCTION_DESC_GPIO_RX(5),
502 FUNCTION_DESC_GPIO_RX(6),
503 FUNCTION_DESC_GPIO_RX(7),
504 FUNCTION_DESC_GPIO_RX(8),
505 FUNCTION_DESC_GPIO_RX(9),
506 FUNCTION_DESC_GPIO_RX(10),
507 FUNCTION_DESC_GPIO_RX(11),
508 FUNCTION_DESC_GPIO_RX(12),
509 FUNCTION_DESC_GPIO_RX(13),
510 FUNCTION_DESC_GPIO_RX(14),
511 FUNCTION_DESC_GPIO_RX(15),
512 FUNCTION_DESC_GPIO_RX(16),
513 FUNCTION_DESC_GPIO_RX(17),
514 FUNCTION_DESC_GPIO_RX(18),
515 FUNCTION_DESC_GPIO_RX(19),
516 FUNCTION_DESC_GPIO_RX(20),
517 FUNCTION_DESC_GPIO(),
518 FUNCTION_DESC(I2C),
519 FUNCTION_DESC(UART),
520 };
521
max96755f_pinctrl_probe(struct platform_device * pdev)522 static int max96755f_pinctrl_probe(struct platform_device *pdev)
523 {
524 struct device *dev = &pdev->dev;
525 struct max96755f_pinctrl *mpctl;
526 struct pinctrl_desc *pctl_desc;
527 int i, ret;
528
529 mpctl = devm_kzalloc(dev, sizeof(*mpctl), GFP_KERNEL);
530 if (!mpctl)
531 return -ENOMEM;
532
533 mpctl->dev = dev;
534 platform_set_drvdata(pdev, mpctl);
535
536 mpctl->regmap = dev_get_regmap(dev->parent, NULL);
537 if (!mpctl->regmap)
538 return dev_err_probe(dev, -ENODEV, "failed to get regmap\n");
539
540 pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL);
541 if (!pctl_desc)
542 return -ENOMEM;
543
544 pctl_desc->name = dev_name(dev);
545 pctl_desc->owner = THIS_MODULE;
546 pctl_desc->pctlops = &max96755f_pinctrl_ops;
547 pctl_desc->pmxops = &max96755f_pinmux_ops;
548 pctl_desc->confops = &max96755f_pinconf_ops;
549 pctl_desc->pins = max96755f_pins_desc;
550 pctl_desc->npins = ARRAY_SIZE(max96755f_pins_desc);
551
552 ret = devm_pinctrl_register_and_init(dev, pctl_desc, mpctl,
553 &mpctl->pctl);
554 if (ret)
555 return dev_err_probe(dev, ret, "failed to register pinctrl\n");
556
557 for (i = 0; i < ARRAY_SIZE(max96755f_groups); i++) {
558 const struct group_desc *group = &max96755f_groups[i];
559
560 ret = pinctrl_generic_add_group(mpctl->pctl, group->name,
561 group->pins, group->num_pins,
562 group->data);
563 if (ret < 0)
564 return dev_err_probe(dev, ret,
565 "failed to register group %s\n",
566 group->name);
567 }
568
569 for (i = 0; i < ARRAY_SIZE(max96755f_functions); i++) {
570 const struct function_desc *func = &max96755f_functions[i];
571
572 ret = pinmux_generic_add_function(mpctl->pctl, func->name,
573 func->group_names,
574 func->num_group_names,
575 func->data);
576 if (ret < 0)
577 return dev_err_probe(dev, ret,
578 "failed to register function %s\n",
579 func->name);
580 }
581
582 return pinctrl_enable(mpctl->pctl);
583 }
584
585 static const struct of_device_id max96755f_pinctrl_of_match[] = {
586 { .compatible = "maxim,max96755f-pinctrl" },
587 {}
588 };
589 MODULE_DEVICE_TABLE(of, max96755f_pinctrl_of_match);
590
591 static struct platform_driver max96755f_pinctrl_driver = {
592 .driver = {
593 .name = "max96755f-pinctrl",
594 .of_match_table = max96755f_pinctrl_of_match,
595 },
596 .probe = max96755f_pinctrl_probe,
597 };
598
599 module_platform_driver(max96755f_pinctrl_driver);
600
601 MODULE_AUTHOR("Guochun Huang <hero.huang@rock-chips.com>");
602 MODULE_DESCRIPTION("Maxim max96755f pin control driver");
603 MODULE_LICENSE("GPL");
604