1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Rockchip PCIE3.0 phy driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/phy/pcie.h>
17 #include <linux/phy/phy.h>
18 #include <linux/regmap.h>
19 #include <linux/reset.h>
20 #include <dt-bindings/phy/phy-snps-pcie3.h>
21
22 /* Register for RK3568 */
23 #define GRF_PCIE30PHY_CON1 0x4
24 #define GRF_PCIE30PHY_CON4 0x10
25 #define GRF_PCIE30PHY_CON6 0x18
26 #define GRF_PCIE30PHY_CON9 0x24
27 #define GRF_PCIE30PHY_STATUS0 0x80
28 #define SRAM_INIT_DONE(reg) (reg & BIT(14))
29
30 /* Register for RK3588 */
31 #define PHP_GRF_PCIESEL_CON 0x100
32 #define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0
33 #define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
34 #define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
35 #define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0))
36
37 struct rockchip_p3phy_ops;
38
39 struct rockchip_p3phy_priv {
40 const struct rockchip_p3phy_ops *ops;
41 void __iomem *mmio;
42 /* mode: RC, EP */
43 int mode;
44 /* pcie30_phymode: Aggregation, Bifurcation */
45 int pcie30_phymode;
46 struct regmap *phy_grf;
47 struct regmap *pipe_grf;
48 struct reset_control *p30phy;
49 struct phy *phy;
50 struct clk_bulk_data *clks;
51 int num_clks;
52 bool is_bifurcation;
53 };
54
55 struct rockchip_p3phy_ops {
56 int (*phy_init)(struct rockchip_p3phy_priv *priv);
57 };
58
rockchip_p3phy_set_mode(struct phy * phy,enum phy_mode mode,int submode)59 static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
60 {
61 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
62
63 /* Acutally We don't care EP/RC mode, but just record it */
64 switch (submode) {
65 case PHY_MODE_PCIE_RC:
66 priv->mode = PHY_MODE_PCIE_RC;
67 break;
68 case PHY_MODE_PCIE_EP:
69 priv->mode = PHY_MODE_PCIE_EP;
70 break;
71 case PHY_MODE_PCIE_BIFURCATION:
72 priv->is_bifurcation = true;
73 break;
74 default:
75 pr_info("%s, invalid mode\n", __func__);
76 return -EINVAL;
77 }
78
79 return 0;
80 }
81
82 static const u16 phy_fw[] = {
83 #include "phy-rockchip-snps-pcie3.fw"
84 };
85
rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv * priv)86 static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv)
87 {
88 int i;
89 int ret = 0;
90 u32 reg;
91
92 /* Deassert PCIe PMA output clamp mode */
93 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
94 (0x1 << 15) | (0x1 << 31));
95 /* Set bifurcation if needed, and it doesn't care RC/EP */
96 if (priv->is_bifurcation) {
97 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
98 0x1 | (0xf << 16));
99 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1,
100 (0x1 << 15) | (0x1 << 31));
101 }
102 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
103 (0x0 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
104 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
105 (0x0 << 13) | (0x1 << (13 + 16))); //sdram_bypass
106
107 reset_control_deassert(priv->p30phy);
108 ret = regmap_read_poll_timeout(priv->phy_grf,
109 GRF_PCIE30PHY_STATUS0,
110 reg, SRAM_INIT_DONE(reg),
111 0, 500);
112 if (ret) {
113 pr_err("%s: lock failed 0x%x, check input refclk and power supply\n",
114 __func__, reg);
115 goto out;
116 }
117
118 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
119 (0x3 << 8) | (0x3 << (8 + 16))); //map to access sram
120 for (i = 0; i < ARRAY_SIZE(phy_fw); i++)
121 writel(phy_fw[i], priv->mmio + (i<<2));
122 pr_info("snps pcie3phy FW update! size %ld\n", ARRAY_SIZE(phy_fw));
123
124 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
125 (0x0 << 8) | (0x3 << (8 + 16)));
126 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
127 (0x1 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
128
129 out:
130 return ret;
131 }
132
133 static const struct rockchip_p3phy_ops rk3568_ops = {
134 .phy_init = rockchip_p3phy_rk3568_init,
135 };
136
rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv * priv)137 static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)
138 {
139 int ret = 0;
140 u32 reg;
141
142 /* Deassert PCIe PMA output clamp mode */
143 regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
144 (0x1 << 8) | (0x1 << 24));
145
146 reset_control_deassert(priv->p30phy);
147
148 ret = regmap_read_poll_timeout(priv->phy_grf,
149 RK3588_PCIE3PHY_GRF_PHY0_STATUS1,
150 reg, RK3588_SRAM_INIT_DONE(reg),
151 0, 500);
152 ret |= regmap_read_poll_timeout(priv->phy_grf,
153 RK3588_PCIE3PHY_GRF_PHY1_STATUS1,
154 reg, RK3588_SRAM_INIT_DONE(reg),
155 0, 500);
156 if (ret)
157 pr_err("%s: lock failed 0x%x, check input refclk and power supply\n",
158 __func__, reg);
159 return ret;
160 }
161
162 static const struct rockchip_p3phy_ops rk3588_ops = {
163 .phy_init = rockchip_p3phy_rk3588_init,
164 };
165
rochchip_p3phy_init(struct phy * phy)166 static int rochchip_p3phy_init(struct phy *phy)
167 {
168 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
169 int ret;
170
171 ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
172 if (ret) {
173 pr_err("failed to enable PCIe bulk clks %d\n", ret);
174 return ret;
175 }
176
177 reset_control_assert(priv->p30phy);
178 udelay(1);
179
180 if (priv->ops->phy_init) {
181 ret = priv->ops->phy_init(priv);
182 if (ret)
183 clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
184 };
185
186 return ret;
187 }
188
rochchip_p3phy_exit(struct phy * phy)189 static int rochchip_p3phy_exit(struct phy *phy)
190 {
191 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
192 clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
193 reset_control_assert(priv->p30phy);
194 return 0;
195 }
196
197 static const struct phy_ops rochchip_p3phy_ops = {
198 .init = rochchip_p3phy_init,
199 .exit = rochchip_p3phy_exit,
200 .set_mode = rockchip_p3phy_set_mode,
201 .owner = THIS_MODULE,
202 };
203
rockchip_p3phy_probe(struct platform_device * pdev)204 static int rockchip_p3phy_probe(struct platform_device *pdev)
205 {
206 struct phy_provider *phy_provider;
207 struct device *dev = &pdev->dev;
208 struct rockchip_p3phy_priv *priv;
209 struct device_node *np = dev->of_node;
210 struct resource *res;
211 int ret;
212 u32 val, reg;
213
214 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
215 if (!priv)
216 return -ENOMEM;
217
218 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
219 priv->mmio = devm_ioremap_resource(dev, res);
220 if (IS_ERR(priv->mmio)) {
221 ret = PTR_ERR(priv->mmio);
222 return ret;
223 }
224
225 priv->ops = of_device_get_match_data(&pdev->dev);
226 if (!priv->ops) {
227 dev_err(&pdev->dev, "no of match data provided\n");
228 return -EINVAL;
229 }
230
231 priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf");
232 if (IS_ERR(priv->phy_grf)) {
233 dev_err(dev, "failed to find rockchip,phy_grf regmap\n");
234 return PTR_ERR(priv->phy_grf);
235 }
236
237 priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
238 "rockchip,pipe-grf");
239 if (IS_ERR(priv->pipe_grf))
240 dev_info(dev, "failed to find rockchip,pipe_grf regmap\n");
241
242 ret = device_property_read_u32(dev, "rockchip,pcie30-phymode", &val);
243 if (!ret)
244 priv->pcie30_phymode = val;
245 else
246 priv->pcie30_phymode = PHY_MODE_PCIE_AGGREGATION;
247
248 /* Select correct pcie30_phymode */
249 if (priv->pcie30_phymode > 4)
250 priv->pcie30_phymode = PHY_MODE_PCIE_AGGREGATION;
251
252 regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
253 (0x7<<16) | priv->pcie30_phymode);
254
255 /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
256 if (!IS_ERR(priv->pipe_grf)) {
257 reg = priv->pcie30_phymode & 3;
258 if (reg)
259 regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
260 (reg << 16) | reg);
261 };
262
263 priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops);
264 if (IS_ERR(priv->phy)) {
265 dev_err(dev, "failed to create combphy\n");
266 return PTR_ERR(priv->phy);
267 }
268
269 priv->p30phy = devm_reset_control_get(dev, "phy");
270 if (IS_ERR(priv->p30phy)) {
271 dev_warn(dev, "no phy reset control specified\n");
272 priv->p30phy = NULL;
273 }
274
275 priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
276 if (priv->num_clks < 1)
277 return -ENODEV;
278
279 dev_set_drvdata(dev, priv);
280 phy_set_drvdata(priv->phy, priv);
281 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
282 return PTR_ERR_OR_ZERO(phy_provider);
283 }
284
285 static const struct of_device_id rockchip_p3phy_of_match[] = {
286 { .compatible = "rockchip,rk3568-pcie3-phy", .data = &rk3568_ops },
287 { .compatible = "rockchip,rk3588-pcie3-phy", .data = &rk3588_ops },
288 { },
289 };
290 MODULE_DEVICE_TABLE(of, rockchip_p3phy_of_match);
291
292 static struct platform_driver rockchip_p3phy_driver = {
293 .probe = rockchip_p3phy_probe,
294 .driver = {
295 .name = "rockchip-snps-pcie3-phy",
296 .of_match_table = rockchip_p3phy_of_match,
297 },
298 };
299 module_platform_driver(rockchip_p3phy_driver);
300 MODULE_DESCRIPTION("Rockchip Synopsys PCIe 3.0 PHY driver");
301 MODULE_LICENSE("GPL v2");
302