1 /*
2 * Rockchip USB 3.0 PHY with Innosilicon IP block driver
3 *
4 * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/debugfs.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23 #include <linux/kernel.h>
24 #include <linux/mfd/syscon.h>
25 #include <linux/module.h>
26 #include <linux/of.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_platform.h>
30 #include <linux/phy/phy.h>
31 #include <linux/platform_device.h>
32 #include <linux/regmap.h>
33 #include <linux/reset.h>
34 #include <linux/usb/phy.h>
35 #include <linux/uaccess.h>
36
37 #define U3PHY_PORT_NUM 2
38 #define U3PHY_MAX_CLKS 4
39 #define BIT_WRITEABLE_SHIFT 16
40 #define SCHEDULE_DELAY (60 * HZ)
41
42 #define U3PHY_APB_RST BIT(0)
43 #define U3PHY_POR_RST BIT(1)
44 #define U3PHY_MAC_RST BIT(2)
45
46 struct rockchip_u3phy;
47 struct rockchip_u3phy_port;
48
49 enum rockchip_u3phy_type {
50 U3PHY_TYPE_PIPE,
51 U3PHY_TYPE_UTMI,
52 };
53
54 enum rockchip_u3phy_pipe_pwr {
55 PIPE_PWR_P0 = 0,
56 PIPE_PWR_P1 = 1,
57 PIPE_PWR_P2 = 2,
58 PIPE_PWR_P3 = 3,
59 PIPE_PWR_MAX = 4,
60 };
61
62 enum rockchip_u3phy_rest_req {
63 U3_POR_RSTN = 0,
64 U2_POR_RSTN = 1,
65 PIPE_MAC_RSTN = 2,
66 UTMI_MAC_RSTN = 3,
67 PIPE_APB_RSTN = 4,
68 UTMI_APB_RSTN = 5,
69 U3PHY_RESET_MAX = 6,
70 };
71
72 enum rockchip_u3phy_utmi_state {
73 PHY_UTMI_HS_ONLINE = 0,
74 PHY_UTMI_DISCONNECT = 1,
75 PHY_UTMI_CONNECT = 2,
76 PHY_UTMI_FS_LS_ONLINE = 4,
77 };
78
79 /*
80 * @rvalue: reset value
81 * @dvalue: desired value
82 */
83 struct u3phy_reg {
84 unsigned int offset;
85 unsigned int bitend;
86 unsigned int bitstart;
87 unsigned int rvalue;
88 unsigned int dvalue;
89 };
90
91 struct rockchip_u3phy_grfcfg {
92 struct u3phy_reg um_suspend;
93 struct u3phy_reg ls_det_en;
94 struct u3phy_reg ls_det_st;
95 struct u3phy_reg um_ls;
96 struct u3phy_reg um_hstdct;
97 struct u3phy_reg u2_only_ctrl;
98 struct u3phy_reg u3_disable;
99 struct u3phy_reg pp_pwr_st;
100 struct u3phy_reg pp_pwr_en[PIPE_PWR_MAX];
101 };
102
103 /**
104 * struct rockchip_u3phy_apbcfg: usb3-phy apb configuration.
105 * @u2_pre_emp: usb2-phy pre-emphasis tuning.
106 * @u2_pre_emp_sth: usb2-phy pre-emphasis strength tuning.
107 * @u2_odt_tuning: usb2-phy odt 45ohm tuning.
108 */
109 struct rockchip_u3phy_apbcfg {
110 unsigned int u2_pre_emp;
111 unsigned int u2_pre_emp_sth;
112 unsigned int u2_odt_tuning;
113 };
114
115 struct rockchip_u3phy_cfg {
116 unsigned int reg;
117 const struct rockchip_u3phy_grfcfg grfcfg;
118
119 int (*phy_pipe_power)(struct rockchip_u3phy *,
120 struct rockchip_u3phy_port *,
121 bool on);
122 int (*phy_tuning)(struct rockchip_u3phy *,
123 struct rockchip_u3phy_port *,
124 struct device_node *);
125 };
126
127 struct rockchip_u3phy_port {
128 struct phy *phy;
129 void __iomem *base;
130 unsigned int index;
131 unsigned char type;
132 bool suspended;
133 bool refclk_25m_quirk;
134 struct mutex mutex; /* mutex for updating register */
135 struct delayed_work um_sm_work;
136 };
137
138 struct rockchip_u3phy {
139 struct device *dev;
140 struct regmap *u3phy_grf;
141 struct regmap *grf;
142 int um_ls_irq;
143 struct clk *clks[U3PHY_MAX_CLKS];
144 struct regulator *vbus;
145 struct reset_control *rsts[U3PHY_RESET_MAX];
146 struct rockchip_u3phy_apbcfg apbcfg;
147 const struct rockchip_u3phy_cfg *cfgs;
148 struct rockchip_u3phy_port ports[U3PHY_PORT_NUM];
149 struct usb_phy usb_phy;
150 bool vbus_enabled;
151 };
152
param_write(void __iomem * base,const struct u3phy_reg * reg,bool desired)153 static inline int param_write(void __iomem *base,
154 const struct u3phy_reg *reg, bool desired)
155 {
156 unsigned int val, mask;
157 unsigned int tmp = desired ? reg->dvalue : reg->rvalue;
158 int ret = 0;
159
160 mask = GENMASK(reg->bitend, reg->bitstart);
161 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
162 ret = regmap_write(base, reg->offset, val);
163
164 return ret;
165 }
166
param_exped(void __iomem * base,const struct u3phy_reg * reg,unsigned int value)167 static inline bool param_exped(void __iomem *base,
168 const struct u3phy_reg *reg,
169 unsigned int value)
170 {
171 int ret;
172 unsigned int tmp, orig;
173 unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
174
175 ret = regmap_read(base, reg->offset, &orig);
176 if (ret)
177 return false;
178
179 tmp = (orig & mask) >> reg->bitstart;
180 return tmp == value;
181 }
182
rockchip_set_vbus_power(struct rockchip_u3phy * u3phy,bool en)183 static int rockchip_set_vbus_power(struct rockchip_u3phy *u3phy, bool en)
184 {
185 int ret = 0;
186
187 if (!u3phy->vbus)
188 return 0;
189
190 if (en && !u3phy->vbus_enabled) {
191 ret = regulator_enable(u3phy->vbus);
192 if (ret)
193 dev_err(u3phy->dev,
194 "Failed to enable VBUS supply\n");
195 } else if (!en && u3phy->vbus_enabled) {
196 ret = regulator_disable(u3phy->vbus);
197 }
198
199 if (ret == 0)
200 u3phy->vbus_enabled = en;
201
202 return ret;
203 }
204
rockchip_u3phy_usb2_only_show(struct seq_file * s,void * unused)205 static int rockchip_u3phy_usb2_only_show(struct seq_file *s, void *unused)
206 {
207 struct rockchip_u3phy *u3phy = s->private;
208
209 if (param_exped(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.u2_only_ctrl, 1))
210 dev_info(u3phy->dev, "u2\n");
211 else
212 dev_info(u3phy->dev, "u3\n");
213
214 return 0;
215 }
216
rockchip_u3phy_usb2_only_open(struct inode * inode,struct file * file)217 static int rockchip_u3phy_usb2_only_open(struct inode *inode,
218 struct file *file)
219 {
220 return single_open(file, rockchip_u3phy_usb2_only_show,
221 inode->i_private);
222 }
223
rockchip_u3phy_usb2_only_write(struct file * file,const char __user * ubuf,size_t count,loff_t * ppos)224 static ssize_t rockchip_u3phy_usb2_only_write(struct file *file,
225 const char __user *ubuf,
226 size_t count, loff_t *ppos)
227 {
228 struct seq_file *s = file->private_data;
229 struct rockchip_u3phy *u3phy = s->private;
230 struct rockchip_u3phy_port *u3phy_port;
231 char buf[32];
232 u8 index;
233
234 if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
235 return -EFAULT;
236
237 if (!strncmp(buf, "u3", 2) &&
238 param_exped(u3phy->u3phy_grf,
239 &u3phy->cfgs->grfcfg.u2_only_ctrl, 1)) {
240 dev_info(u3phy->dev, "Set usb3.0 and usb2.0 mode successfully\n");
241
242 rockchip_set_vbus_power(u3phy, false);
243
244 param_write(u3phy->grf,
245 &u3phy->cfgs->grfcfg.u3_disable, false);
246 param_write(u3phy->u3phy_grf,
247 &u3phy->cfgs->grfcfg.u2_only_ctrl, false);
248
249 for (index = 0; index < U3PHY_PORT_NUM; index++) {
250 u3phy_port = &u3phy->ports[index];
251 /* enable u3 rx termimation */
252 if (u3phy_port->type == U3PHY_TYPE_PIPE)
253 writel(0x30, u3phy_port->base + 0xd8);
254 }
255
256 atomic_notifier_call_chain(&u3phy->usb_phy.notifier, 0, NULL);
257
258 rockchip_set_vbus_power(u3phy, true);
259 } else if (!strncmp(buf, "u2", 2) &&
260 param_exped(u3phy->u3phy_grf,
261 &u3phy->cfgs->grfcfg.u2_only_ctrl, 0)) {
262 dev_info(u3phy->dev, "Set usb2.0 only mode successfully\n");
263
264 rockchip_set_vbus_power(u3phy, false);
265
266 param_write(u3phy->grf,
267 &u3phy->cfgs->grfcfg.u3_disable, true);
268 param_write(u3phy->u3phy_grf,
269 &u3phy->cfgs->grfcfg.u2_only_ctrl, true);
270
271 for (index = 0; index < U3PHY_PORT_NUM; index++) {
272 u3phy_port = &u3phy->ports[index];
273 /* disable u3 rx termimation */
274 if (u3phy_port->type == U3PHY_TYPE_PIPE)
275 writel(0x20, u3phy_port->base + 0xd8);
276 }
277
278 atomic_notifier_call_chain(&u3phy->usb_phy.notifier, 0, NULL);
279
280 rockchip_set_vbus_power(u3phy, true);
281 } else {
282 dev_info(u3phy->dev, "Same or illegal mode\n");
283 }
284
285 return count;
286 }
287
288 static const struct file_operations rockchip_u3phy_usb2_only_fops = {
289 .open = rockchip_u3phy_usb2_only_open,
290 .write = rockchip_u3phy_usb2_only_write,
291 .read = seq_read,
292 .llseek = seq_lseek,
293 .release = single_release,
294 };
295
rockchip_u3phy_debugfs_init(struct rockchip_u3phy * u3phy)296 static void rockchip_u3phy_debugfs_init(struct rockchip_u3phy *u3phy)
297 {
298 struct dentry *root;
299
300 root = debugfs_create_dir(dev_name(u3phy->dev), NULL);
301 debugfs_create_file("u3phy_mode", 0644, root,
302 u3phy, &rockchip_u3phy_usb2_only_fops);
303 }
304
get_rest_name(enum rockchip_u3phy_rest_req rst)305 static const char *get_rest_name(enum rockchip_u3phy_rest_req rst)
306 {
307 switch (rst) {
308 case U2_POR_RSTN:
309 return "u3phy-u2-por";
310 case U3_POR_RSTN:
311 return "u3phy-u3-por";
312 case PIPE_MAC_RSTN:
313 return "u3phy-pipe-mac";
314 case UTMI_MAC_RSTN:
315 return "u3phy-utmi-mac";
316 case UTMI_APB_RSTN:
317 return "u3phy-utmi-apb";
318 case PIPE_APB_RSTN:
319 return "u3phy-pipe-apb";
320 default:
321 return "invalid";
322 }
323 }
324
rockchip_u3phy_rest_deassert(struct rockchip_u3phy * u3phy,unsigned int flag)325 static void rockchip_u3phy_rest_deassert(struct rockchip_u3phy *u3phy,
326 unsigned int flag)
327 {
328 int rst;
329
330 if (flag & U3PHY_APB_RST) {
331 dev_dbg(u3phy->dev, "deassert APB bus interface reset\n");
332 for (rst = PIPE_APB_RSTN; rst <= UTMI_APB_RSTN; rst++) {
333 if (u3phy->rsts[rst])
334 reset_control_deassert(u3phy->rsts[rst]);
335 }
336 }
337
338 if (flag & U3PHY_POR_RST) {
339 usleep_range(12, 15);
340 dev_dbg(u3phy->dev, "deassert u2 and u3 phy power on reset\n");
341 for (rst = U3_POR_RSTN; rst <= U2_POR_RSTN; rst++) {
342 if (u3phy->rsts[rst])
343 reset_control_deassert(u3phy->rsts[rst]);
344 }
345 }
346
347 if (flag & U3PHY_MAC_RST) {
348 usleep_range(1200, 1500);
349 dev_dbg(u3phy->dev, "deassert pipe and utmi MAC reset\n");
350 for (rst = PIPE_MAC_RSTN; rst <= UTMI_MAC_RSTN; rst++)
351 if (u3phy->rsts[rst])
352 reset_control_deassert(u3phy->rsts[rst]);
353 }
354 }
355
rockchip_u3phy_rest_assert(struct rockchip_u3phy * u3phy)356 static void rockchip_u3phy_rest_assert(struct rockchip_u3phy *u3phy)
357 {
358 int rst;
359
360 dev_dbg(u3phy->dev, "assert u3phy reset\n");
361 for (rst = 0; rst < U3PHY_RESET_MAX; rst++)
362 if (u3phy->rsts[rst])
363 reset_control_assert(u3phy->rsts[rst]);
364 }
365
rockchip_u3phy_clk_enable(struct rockchip_u3phy * u3phy)366 static int rockchip_u3phy_clk_enable(struct rockchip_u3phy *u3phy)
367 {
368 int ret, clk;
369
370 for (clk = 0; clk < U3PHY_MAX_CLKS && u3phy->clks[clk]; clk++) {
371 ret = clk_prepare_enable(u3phy->clks[clk]);
372 if (ret)
373 goto err_disable_clks;
374 }
375 return 0;
376
377 err_disable_clks:
378 while (--clk >= 0)
379 clk_disable_unprepare(u3phy->clks[clk]);
380 return ret;
381 }
382
rockchip_u3phy_clk_disable(struct rockchip_u3phy * u3phy)383 static void rockchip_u3phy_clk_disable(struct rockchip_u3phy *u3phy)
384 {
385 int clk;
386
387 for (clk = U3PHY_MAX_CLKS - 1; clk >= 0; clk--)
388 if (u3phy->clks[clk])
389 clk_disable_unprepare(u3phy->clks[clk]);
390 }
391
rockchip_u3phy_init(struct phy * phy)392 static int rockchip_u3phy_init(struct phy *phy)
393 {
394 return 0;
395 }
396
rockchip_u3phy_exit(struct phy * phy)397 static int rockchip_u3phy_exit(struct phy *phy)
398 {
399 return 0;
400 }
401
rockchip_u3phy_power_on(struct phy * phy)402 static int rockchip_u3phy_power_on(struct phy *phy)
403 {
404 struct rockchip_u3phy_port *u3phy_port = phy_get_drvdata(phy);
405 struct rockchip_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
406 int ret;
407
408 dev_info(&u3phy_port->phy->dev, "u3phy %s power on\n",
409 (u3phy_port->type == U3PHY_TYPE_UTMI) ? "u2" : "u3");
410
411 if (!u3phy_port->suspended)
412 return 0;
413
414 ret = rockchip_u3phy_clk_enable(u3phy);
415 if (ret)
416 return ret;
417
418 if (u3phy_port->type == U3PHY_TYPE_UTMI) {
419 param_write(u3phy->u3phy_grf,
420 &u3phy->cfgs->grfcfg.um_suspend, false);
421 } else {
422 /* current in p2 ? */
423 if (param_exped(u3phy->u3phy_grf,
424 &u3phy->cfgs->grfcfg.pp_pwr_st, PIPE_PWR_P2))
425 goto done;
426
427 if (u3phy->cfgs->phy_pipe_power) {
428 dev_dbg(u3phy->dev, "do pipe power up\n");
429 u3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, true);
430 }
431
432 /* exit to p0 */
433 param_write(u3phy->u3phy_grf,
434 &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P0], true);
435 usleep_range(90, 100);
436
437 /* enter to p2 from p0 */
438 param_write(u3phy->u3phy_grf,
439 &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P2],
440 false);
441 udelay(3);
442 }
443
444 done:
445 rockchip_set_vbus_power(u3phy, true);
446 u3phy_port->suspended = false;
447 return 0;
448 }
449
rockchip_u3phy_power_off(struct phy * phy)450 static int rockchip_u3phy_power_off(struct phy *phy)
451 {
452 struct rockchip_u3phy_port *u3phy_port = phy_get_drvdata(phy);
453 struct rockchip_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
454
455 dev_info(&u3phy_port->phy->dev, "u3phy %s power off\n",
456 (u3phy_port->type == U3PHY_TYPE_UTMI) ? "u2" : "u3");
457
458 if (u3phy_port->suspended)
459 return 0;
460
461 if (u3phy_port->type == U3PHY_TYPE_UTMI) {
462 param_write(u3phy->u3phy_grf,
463 &u3phy->cfgs->grfcfg.um_suspend, true);
464 } else {
465 /* current in p3 ? */
466 if (param_exped(u3phy->u3phy_grf,
467 &u3phy->cfgs->grfcfg.pp_pwr_st, PIPE_PWR_P3))
468 goto done;
469
470 /* exit to p0 */
471 param_write(u3phy->u3phy_grf,
472 &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P0], true);
473 udelay(2);
474
475 /* enter to p3 from p0 */
476 param_write(u3phy->u3phy_grf,
477 &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P3], true);
478 udelay(6);
479
480 if (u3phy->cfgs->phy_pipe_power) {
481 dev_dbg(u3phy->dev, "do pipe power down\n");
482 u3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, false);
483 }
484 }
485
486 done:
487 rockchip_u3phy_clk_disable(u3phy);
488 u3phy_port->suspended = true;
489 return 0;
490 }
491
492 static __maybe_unused
rockchip_u3phy_xlate(struct device * dev,struct of_phandle_args * args)493 struct phy *rockchip_u3phy_xlate(struct device *dev,
494 struct of_phandle_args *args)
495 {
496 struct rockchip_u3phy *u3phy = dev_get_drvdata(dev);
497 struct rockchip_u3phy_port *u3phy_port = NULL;
498 struct device_node *phy_np = args->np;
499 int index;
500
501 if (args->args_count != 1) {
502 dev_err(dev, "invalid number of cells in 'phy' property\n");
503 return ERR_PTR(-EINVAL);
504 }
505
506 for (index = 0; index < U3PHY_PORT_NUM; index++) {
507 if (phy_np == u3phy->ports[index].phy->dev.of_node) {
508 u3phy_port = &u3phy->ports[index];
509 break;
510 }
511 }
512
513 if (!u3phy_port) {
514 dev_err(dev, "failed to find appropriate phy\n");
515 return ERR_PTR(-EINVAL);
516 }
517
518 return u3phy_port->phy;
519 }
520
521 static struct phy_ops rockchip_u3phy_ops = {
522 .init = rockchip_u3phy_init,
523 .exit = rockchip_u3phy_exit,
524 .power_on = rockchip_u3phy_power_on,
525 .power_off = rockchip_u3phy_power_off,
526 .owner = THIS_MODULE,
527 };
528
529 /*
530 * The function manage host-phy port state and suspend/resume phy port
531 * to save power automatically.
532 *
533 * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
534 * devices is disconnect or not. Besides, we do not need care it is FS/LS
535 * disconnected or HS disconnected, actually, we just only need get the
536 * device is disconnected at last through rearm the delayed work,
537 * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
538 */
rockchip_u3phy_um_sm_work(struct work_struct * work)539 static void rockchip_u3phy_um_sm_work(struct work_struct *work)
540 {
541 struct rockchip_u3phy_port *u3phy_port =
542 container_of(work, struct rockchip_u3phy_port, um_sm_work.work);
543 struct rockchip_u3phy *u3phy =
544 dev_get_drvdata(u3phy_port->phy->dev.parent);
545 unsigned int sh = u3phy->cfgs->grfcfg.um_hstdct.bitend -
546 u3phy->cfgs->grfcfg.um_hstdct.bitstart + 1;
547 unsigned int ul, uhd, state;
548 unsigned int ul_mask, uhd_mask;
549 int ret;
550
551 mutex_lock(&u3phy_port->mutex);
552
553 ret = regmap_read(u3phy->u3phy_grf,
554 u3phy->cfgs->grfcfg.um_ls.offset, &ul);
555 if (ret < 0)
556 goto next_schedule;
557
558 ret = regmap_read(u3phy->u3phy_grf,
559 u3phy->cfgs->grfcfg.um_hstdct.offset, &uhd);
560 if (ret < 0)
561 goto next_schedule;
562
563 uhd_mask = GENMASK(u3phy->cfgs->grfcfg.um_hstdct.bitend,
564 u3phy->cfgs->grfcfg.um_hstdct.bitstart);
565 ul_mask = GENMASK(u3phy->cfgs->grfcfg.um_ls.bitend,
566 u3phy->cfgs->grfcfg.um_ls.bitstart);
567
568 /* stitch on um_ls and um_hstdct as phy state */
569 state = ((uhd & uhd_mask) >> u3phy->cfgs->grfcfg.um_hstdct.bitstart) |
570 (((ul & ul_mask) >> u3phy->cfgs->grfcfg.um_ls.bitstart) << sh);
571
572 switch (state) {
573 case PHY_UTMI_HS_ONLINE:
574 dev_dbg(&u3phy_port->phy->dev, "HS online\n");
575 break;
576 case PHY_UTMI_FS_LS_ONLINE:
577 /*
578 * For FS/LS device, the online state share with connect state
579 * from um_ls and um_hstdct register, so we distinguish
580 * them via suspended flag.
581 *
582 * Plus, there are two cases, one is D- Line pull-up, and D+
583 * line pull-down, the state is 4; another is D+ line pull-up,
584 * and D- line pull-down, the state is 2.
585 */
586 if (!u3phy_port->suspended) {
587 /* D- line pull-up, D+ line pull-down */
588 dev_dbg(&u3phy_port->phy->dev, "FS/LS online\n");
589 break;
590 }
591 fallthrough;
592 case PHY_UTMI_CONNECT:
593 if (u3phy_port->suspended) {
594 dev_dbg(&u3phy_port->phy->dev, "Connected\n");
595 rockchip_u3phy_power_on(u3phy_port->phy);
596 u3phy_port->suspended = false;
597 } else {
598 /* D+ line pull-up, D- line pull-down */
599 dev_dbg(&u3phy_port->phy->dev, "FS/LS online\n");
600 }
601 break;
602 case PHY_UTMI_DISCONNECT:
603 if (!u3phy_port->suspended) {
604 dev_dbg(&u3phy_port->phy->dev, "Disconnected\n");
605 rockchip_u3phy_power_off(u3phy_port->phy);
606 u3phy_port->suspended = true;
607 }
608
609 /*
610 * activate the linestate detection to get the next device
611 * plug-in irq.
612 */
613 param_write(u3phy->u3phy_grf,
614 &u3phy->cfgs->grfcfg.ls_det_st, true);
615 param_write(u3phy->u3phy_grf,
616 &u3phy->cfgs->grfcfg.ls_det_en, true);
617
618 /*
619 * we don't need to rearm the delayed work when the phy port
620 * is suspended.
621 */
622 mutex_unlock(&u3phy_port->mutex);
623 return;
624 default:
625 dev_dbg(&u3phy_port->phy->dev, "unknown phy state\n");
626 break;
627 }
628
629 next_schedule:
630 mutex_unlock(&u3phy_port->mutex);
631 schedule_delayed_work(&u3phy_port->um_sm_work, SCHEDULE_DELAY);
632 }
633
rockchip_u3phy_um_ls_irq(int irq,void * data)634 static irqreturn_t rockchip_u3phy_um_ls_irq(int irq, void *data)
635 {
636 struct rockchip_u3phy_port *u3phy_port = data;
637 struct rockchip_u3phy *u3phy =
638 dev_get_drvdata(u3phy_port->phy->dev.parent);
639
640 if (!param_exped(u3phy->u3phy_grf,
641 &u3phy->cfgs->grfcfg.ls_det_st,
642 u3phy->cfgs->grfcfg.ls_det_st.dvalue))
643 return IRQ_NONE;
644
645 dev_dbg(u3phy->dev, "utmi linestate interrupt\n");
646 mutex_lock(&u3phy_port->mutex);
647
648 /* disable linestate detect irq and clear its status */
649 param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_en, false);
650 param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_st, true);
651
652 mutex_unlock(&u3phy_port->mutex);
653
654 /*
655 * In this case for host phy, a new device is plugged in, meanwhile,
656 * if the phy port is suspended, we need rearm the work to resume it
657 * and mange its states; otherwise, we just return irq handled.
658 */
659 if (u3phy_port->suspended) {
660 dev_dbg(u3phy->dev, "schedule utmi sm work\n");
661 rockchip_u3phy_um_sm_work(&u3phy_port->um_sm_work.work);
662 }
663
664 return IRQ_HANDLED;
665 }
666
rockchip_u3phy_parse_dt(struct rockchip_u3phy * u3phy,struct platform_device * pdev)667 static int rockchip_u3phy_parse_dt(struct rockchip_u3phy *u3phy,
668 struct platform_device *pdev)
669
670 {
671 struct device *dev = &pdev->dev;
672 struct device_node *np = dev->of_node;
673 int ret, i, clk;
674
675 u3phy->um_ls_irq = platform_get_irq_byname(pdev, "linestate");
676 if (u3phy->um_ls_irq < 0) {
677 dev_err(dev, "get utmi linestate irq failed\n");
678 return -ENXIO;
679 }
680
681 /* Get Vbus regulators */
682 u3phy->vbus = devm_regulator_get_optional(dev, "vbus");
683 if (IS_ERR(u3phy->vbus)) {
684 ret = PTR_ERR(u3phy->vbus);
685 if (ret == -EPROBE_DEFER)
686 return ret;
687
688 dev_warn(dev, "Failed to get VBUS supply regulator\n");
689 u3phy->vbus = NULL;
690 }
691
692 for (clk = 0; clk < U3PHY_MAX_CLKS; clk++) {
693 u3phy->clks[clk] = of_clk_get(np, clk);
694 if (IS_ERR(u3phy->clks[clk])) {
695 ret = PTR_ERR(u3phy->clks[clk]);
696 if (ret == -EPROBE_DEFER)
697 goto err_put_clks;
698 u3phy->clks[clk] = NULL;
699 break;
700 }
701 }
702
703 for (i = 0; i < U3PHY_RESET_MAX; i++) {
704 u3phy->rsts[i] = devm_reset_control_get(dev, get_rest_name(i));
705 if (IS_ERR(u3phy->rsts[i])) {
706 dev_info(dev, "no %s reset control specified\n",
707 get_rest_name(i));
708 u3phy->rsts[i] = NULL;
709 }
710 }
711
712 return 0;
713
714 err_put_clks:
715 while (--clk >= 0)
716 clk_put(u3phy->clks[clk]);
717 return ret;
718 }
719
rockchip_u3phy_port_init(struct rockchip_u3phy * u3phy,struct rockchip_u3phy_port * u3phy_port,struct device_node * child_np)720 static int rockchip_u3phy_port_init(struct rockchip_u3phy *u3phy,
721 struct rockchip_u3phy_port *u3phy_port,
722 struct device_node *child_np)
723 {
724 struct resource res;
725 struct phy *phy;
726 int ret;
727
728 dev_dbg(u3phy->dev, "u3phy port initialize\n");
729
730 mutex_init(&u3phy_port->mutex);
731 u3phy_port->suspended = true; /* initial status */
732
733 phy = devm_phy_create(u3phy->dev, child_np, &rockchip_u3phy_ops);
734 if (IS_ERR(phy)) {
735 dev_err(u3phy->dev, "failed to create phy\n");
736 return PTR_ERR(phy);
737 }
738
739 u3phy_port->phy = phy;
740
741 ret = of_address_to_resource(child_np, 0, &res);
742 if (ret) {
743 dev_err(u3phy->dev, "failed to get address resource(np-%s)\n",
744 child_np->name);
745 return ret;
746 }
747
748 u3phy_port->base = devm_ioremap_resource(&u3phy_port->phy->dev, &res);
749 if (IS_ERR(u3phy_port->base)) {
750 dev_err(u3phy->dev, "failed to remap phy regs\n");
751 return PTR_ERR(u3phy_port->base);
752 }
753
754 if (!of_node_cmp(child_np->name, "pipe")) {
755 u3phy_port->type = U3PHY_TYPE_PIPE;
756 u3phy_port->refclk_25m_quirk =
757 of_property_read_bool(child_np,
758 "rockchip,refclk-25m-quirk");
759 } else {
760 u3phy_port->type = U3PHY_TYPE_UTMI;
761 INIT_DELAYED_WORK(&u3phy_port->um_sm_work,
762 rockchip_u3phy_um_sm_work);
763
764 ret = devm_request_threaded_irq(u3phy->dev, u3phy->um_ls_irq,
765 NULL, rockchip_u3phy_um_ls_irq,
766 IRQF_ONESHOT, "rockchip_u3phy",
767 u3phy_port);
768 if (ret) {
769 dev_err(u3phy->dev, "failed to request utmi linestate irq handle\n");
770 return ret;
771 }
772 }
773
774 if (u3phy->cfgs->phy_tuning) {
775 dev_dbg(u3phy->dev, "do u3phy tuning\n");
776 ret = u3phy->cfgs->phy_tuning(u3phy, u3phy_port, child_np);
777 if (ret)
778 return ret;
779 }
780
781 phy_set_drvdata(u3phy_port->phy, u3phy_port);
782 return 0;
783 }
784
rockchip_u3phy_on_init(struct usb_phy * usb_phy)785 static int rockchip_u3phy_on_init(struct usb_phy *usb_phy)
786 {
787 struct rockchip_u3phy *u3phy =
788 container_of(usb_phy, struct rockchip_u3phy, usb_phy);
789
790 rockchip_u3phy_rest_deassert(u3phy, U3PHY_POR_RST | U3PHY_MAC_RST);
791 return 0;
792 }
793
rockchip_u3phy_on_shutdown(struct usb_phy * usb_phy)794 static void rockchip_u3phy_on_shutdown(struct usb_phy *usb_phy)
795 {
796 struct rockchip_u3phy *u3phy =
797 container_of(usb_phy, struct rockchip_u3phy, usb_phy);
798 int rst;
799
800 for (rst = 0; rst < U3PHY_RESET_MAX; rst++)
801 if (u3phy->rsts[rst] && rst != UTMI_APB_RSTN &&
802 rst != PIPE_APB_RSTN)
803 reset_control_assert(u3phy->rsts[rst]);
804 udelay(1);
805 }
806
rockchip_u3phy_on_disconnect(struct usb_phy * usb_phy,enum usb_device_speed speed)807 static int rockchip_u3phy_on_disconnect(struct usb_phy *usb_phy,
808 enum usb_device_speed speed)
809 {
810 struct rockchip_u3phy *u3phy =
811 container_of(usb_phy, struct rockchip_u3phy, usb_phy);
812
813 dev_info(u3phy->dev, "%s device has disconnected\n",
814 (speed == USB_SPEED_SUPER) ? "U3" : "UW/U2/U1.1/U1");
815
816 if (speed == USB_SPEED_SUPER)
817 atomic_notifier_call_chain(&usb_phy->notifier, 0, NULL);
818
819 return 0;
820 }
821
rockchip_u3phy_probe(struct platform_device * pdev)822 static int rockchip_u3phy_probe(struct platform_device *pdev)
823 {
824 struct device *dev = &pdev->dev;
825 struct device_node *np = dev->of_node;
826 struct device_node *child_np;
827 struct phy_provider *provider;
828 struct rockchip_u3phy *u3phy;
829 const struct rockchip_u3phy_cfg *phy_cfgs;
830 const struct of_device_id *match;
831 unsigned int reg[2];
832 int index, ret;
833
834 match = of_match_device(dev->driver->of_match_table, dev);
835 if (!match || !match->data) {
836 dev_err(dev, "phy-cfgs are not assigned!\n");
837 return -EINVAL;
838 }
839
840 u3phy = devm_kzalloc(dev, sizeof(*u3phy), GFP_KERNEL);
841 if (!u3phy)
842 return -ENOMEM;
843
844 u3phy->u3phy_grf =
845 syscon_regmap_lookup_by_phandle(np, "rockchip,u3phygrf");
846 if (IS_ERR(u3phy->u3phy_grf))
847 return PTR_ERR(u3phy->u3phy_grf);
848
849 u3phy->grf =
850 syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
851 if (IS_ERR(u3phy->grf)) {
852 dev_err(dev, "Missing rockchip,grf property\n");
853 return PTR_ERR(u3phy->grf);
854 }
855
856 if (of_property_read_u32_array(np, "reg", reg, 2)) {
857 dev_err(dev, "the reg property is not assigned in %s node\n",
858 np->name);
859 return -EINVAL;
860 }
861
862 u3phy->dev = dev;
863 u3phy->vbus_enabled = false;
864 phy_cfgs = match->data;
865 platform_set_drvdata(pdev, u3phy);
866
867 /* find out a proper config which can be matched with dt. */
868 index = 0;
869 while (phy_cfgs[index].reg) {
870 if (phy_cfgs[index].reg == reg[1]) {
871 u3phy->cfgs = &phy_cfgs[index];
872 break;
873 }
874
875 ++index;
876 }
877
878 if (!u3phy->cfgs) {
879 dev_err(dev, "no phy-cfgs can be matched with %s node\n",
880 np->name);
881 return -EINVAL;
882 }
883
884 ret = rockchip_u3phy_parse_dt(u3phy, pdev);
885 if (ret) {
886 dev_err(dev, "parse dt failed, ret(%d)\n", ret);
887 return ret;
888 }
889
890 ret = rockchip_u3phy_clk_enable(u3phy);
891 if (ret) {
892 dev_err(dev, "clk enable failed, ret(%d)\n", ret);
893 return ret;
894 }
895
896 rockchip_u3phy_rest_assert(u3phy);
897 rockchip_u3phy_rest_deassert(u3phy, U3PHY_APB_RST | U3PHY_POR_RST);
898
899 index = 0;
900 for_each_available_child_of_node(np, child_np) {
901 struct rockchip_u3phy_port *u3phy_port = &u3phy->ports[index];
902
903 u3phy_port->index = index;
904 ret = rockchip_u3phy_port_init(u3phy, u3phy_port, child_np);
905 if (ret) {
906 dev_err(dev, "u3phy port init failed,ret(%d)\n", ret);
907 goto put_child;
908 }
909
910 /* to prevent out of boundary */
911 if (++index >= U3PHY_PORT_NUM)
912 break;
913 }
914
915 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
916 if (IS_ERR(provider)) {
917 ret = PTR_ERR(provider);
918 goto put_child;
919 }
920
921 rockchip_u3phy_rest_deassert(u3phy, U3PHY_MAC_RST);
922 rockchip_u3phy_clk_disable(u3phy);
923
924 u3phy->usb_phy.dev = dev;
925 u3phy->usb_phy.init = rockchip_u3phy_on_init;
926 u3phy->usb_phy.shutdown = rockchip_u3phy_on_shutdown;
927 u3phy->usb_phy.notify_disconnect = rockchip_u3phy_on_disconnect;
928 usb_add_phy(&u3phy->usb_phy, USB_PHY_TYPE_USB3);
929 ATOMIC_INIT_NOTIFIER_HEAD(&u3phy->usb_phy.notifier);
930
931 rockchip_u3phy_debugfs_init(u3phy);
932
933 dev_info(dev, "Rockchip u3phy initialized successfully\n");
934 return 0;
935
936 put_child:
937 of_node_put(child_np);
938 return ret;
939 }
940
rk3328_u3phy_pipe_power(struct rockchip_u3phy * u3phy,struct rockchip_u3phy_port * u3phy_port,bool on)941 static int rk3328_u3phy_pipe_power(struct rockchip_u3phy *u3phy,
942 struct rockchip_u3phy_port *u3phy_port,
943 bool on)
944 {
945 unsigned int reg;
946
947 if (on) {
948 reg = readl(u3phy_port->base + 0x1a8);
949 reg &= ~BIT(4); /* ldo power up */
950 writel(reg, u3phy_port->base + 0x1a8);
951
952 reg = readl(u3phy_port->base + 0x044);
953 reg &= ~BIT(4); /* bg power on */
954 writel(reg, u3phy_port->base + 0x044);
955
956 reg = readl(u3phy_port->base + 0x150);
957 reg |= BIT(6); /* tx bias enable */
958 writel(reg, u3phy_port->base + 0x150);
959
960 reg = readl(u3phy_port->base + 0x080);
961 reg &= ~BIT(2); /* tx cm power up */
962 writel(reg, u3phy_port->base + 0x080);
963
964 reg = readl(u3phy_port->base + 0x0c0);
965 /* tx obs enable and rx cm enable */
966 reg |= (BIT(3) | BIT(4));
967 writel(reg, u3phy_port->base + 0x0c0);
968
969 udelay(1);
970 } else {
971 reg = readl(u3phy_port->base + 0x1a8);
972 reg |= BIT(4); /* ldo power down */
973 writel(reg, u3phy_port->base + 0x1a8);
974
975 reg = readl(u3phy_port->base + 0x044);
976 reg |= BIT(4); /* bg power down */
977 writel(reg, u3phy_port->base + 0x044);
978
979 reg = readl(u3phy_port->base + 0x150);
980 reg &= ~BIT(6); /* tx bias disable */
981 writel(reg, u3phy_port->base + 0x150);
982
983 reg = readl(u3phy_port->base + 0x080);
984 reg |= BIT(2); /* tx cm power down */
985 writel(reg, u3phy_port->base + 0x080);
986
987 reg = readl(u3phy_port->base + 0x0c0);
988 /* tx obs disable and rx cm disable */
989 reg &= ~(BIT(3) | BIT(4));
990 writel(reg, u3phy_port->base + 0x0c0);
991 }
992
993 return 0;
994 }
995
rk3328_u3phy_tuning(struct rockchip_u3phy * u3phy,struct rockchip_u3phy_port * u3phy_port,struct device_node * child_np)996 static int rk3328_u3phy_tuning(struct rockchip_u3phy *u3phy,
997 struct rockchip_u3phy_port *u3phy_port,
998 struct device_node *child_np)
999 {
1000 if (u3phy_port->type == U3PHY_TYPE_UTMI) {
1001 /*
1002 * For rk3328 SoC, pre-emphasis and pre-emphasis strength must
1003 * be written as one fixed value as below.
1004 *
1005 * Dissimilarly, the odt 45ohm value should be flexibly tuninged
1006 * for the different boards to adjust HS eye height, so its
1007 * value can be assigned in DT in code design.
1008 */
1009
1010 /* {bits[2:0]=111}: always enable pre-emphasis */
1011 u3phy->apbcfg.u2_pre_emp = 0x0f;
1012
1013 /* {bits[5:3]=000}: pre-emphasis strength as the weakest */
1014 u3phy->apbcfg.u2_pre_emp_sth = 0x41;
1015
1016 /* {bits[4:0]=10101}: odt 45ohm tuning */
1017 u3phy->apbcfg.u2_odt_tuning = 0xb5;
1018 /* optional override of the odt 45ohm tuning */
1019 of_property_read_u32(child_np, "rockchip,odt-val-tuning",
1020 &u3phy->apbcfg.u2_odt_tuning);
1021
1022 writel(u3phy->apbcfg.u2_pre_emp, u3phy_port->base + 0x030);
1023 writel(u3phy->apbcfg.u2_pre_emp_sth, u3phy_port->base + 0x040);
1024 writel(u3phy->apbcfg.u2_odt_tuning, u3phy_port->base + 0x11c);
1025 } else if (u3phy_port->type == U3PHY_TYPE_PIPE) {
1026 if (u3phy_port->refclk_25m_quirk) {
1027 dev_dbg(u3phy->dev, "switch to 25m refclk\n");
1028 /* ref clk switch to 25M */
1029 writel(0x64, u3phy_port->base + 0x11c);
1030 writel(0x64, u3phy_port->base + 0x028);
1031 writel(0x01, u3phy_port->base + 0x020);
1032 writel(0x21, u3phy_port->base + 0x030);
1033 writel(0x06, u3phy_port->base + 0x108);
1034 writel(0x00, u3phy_port->base + 0x118);
1035 } else {
1036 /* configure for 24M ref clk */
1037 writel(0x80, u3phy_port->base + 0x10c);
1038 writel(0x01, u3phy_port->base + 0x118);
1039 writel(0x38, u3phy_port->base + 0x11c);
1040 writel(0x83, u3phy_port->base + 0x020);
1041 writel(0x02, u3phy_port->base + 0x108);
1042 }
1043
1044 /* Enable SSC */
1045 udelay(3);
1046 writel(0x08, u3phy_port->base + 0x000);
1047 writel(0x0c, u3phy_port->base + 0x120);
1048
1049 /* Tuning Rx for compliance RJTL test */
1050 writel(0x70, u3phy_port->base + 0x150);
1051 writel(0x12, u3phy_port->base + 0x0c8);
1052 writel(0x05, u3phy_port->base + 0x148);
1053 writel(0x08, u3phy_port->base + 0x068);
1054 writel(0xf0, u3phy_port->base + 0x1c4);
1055 writel(0xff, u3phy_port->base + 0x070);
1056 writel(0x0f, u3phy_port->base + 0x06c);
1057 writel(0xe0, u3phy_port->base + 0x060);
1058
1059 /*
1060 * Tuning Tx to increase the bias current
1061 * used in TX driver and RX EQ, it can
1062 * also increase the voltage of LFPS.
1063 */
1064 writel(0x08, u3phy_port->base + 0x180);
1065 } else {
1066 dev_err(u3phy->dev, "invalid u3phy port type\n");
1067 return -EINVAL;
1068 }
1069
1070 return 0;
1071 }
1072
1073 static const struct rockchip_u3phy_cfg rk3328_u3phy_cfgs[] = {
1074 {
1075 .reg = 0xff470000,
1076 .grfcfg = {
1077 .um_suspend = { 0x0004, 15, 0, 0x1452, 0x15d1 },
1078 .u2_only_ctrl = { 0x0020, 15, 15, 0, 1 },
1079 .um_ls = { 0x0030, 5, 4, 0, 1 },
1080 .um_hstdct = { 0x0030, 7, 7, 0, 1 },
1081 .ls_det_en = { 0x0040, 0, 0, 0, 1 },
1082 .ls_det_st = { 0x0044, 0, 0, 0, 1 },
1083 .pp_pwr_st = { 0x0034, 14, 13, 0, 0},
1084 .pp_pwr_en = { {0x0020, 14, 0, 0x0014, 0x0005},
1085 {0x0020, 14, 0, 0x0014, 0x000d},
1086 {0x0020, 14, 0, 0x0014, 0x0015},
1087 {0x0020, 14, 0, 0x0014, 0x001d} },
1088 .u3_disable = { 0x04c4, 15, 0, 0x1100, 0x101},
1089 },
1090 .phy_pipe_power = rk3328_u3phy_pipe_power,
1091 .phy_tuning = rk3328_u3phy_tuning,
1092 },
1093 { /* sentinel */ }
1094 };
1095
1096 static const struct of_device_id rockchip_u3phy_dt_match[] = {
1097 { .compatible = "rockchip,rk3328-u3phy", .data = &rk3328_u3phy_cfgs },
1098 {}
1099 };
1100 MODULE_DEVICE_TABLE(of, rockchip_u3phy_dt_match);
1101
1102 static struct platform_driver rockchip_u3phy_driver = {
1103 .probe = rockchip_u3phy_probe,
1104 .driver = {
1105 .name = "rockchip-u3phy",
1106 .of_match_table = rockchip_u3phy_dt_match,
1107 },
1108 };
1109 module_platform_driver(rockchip_u3phy_driver);
1110
1111 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1112 MODULE_AUTHOR("William Wu <william.wu@rock-chips.com>");
1113 MODULE_DESCRIPTION("Rockchip USB 3.0 PHY driver");
1114 MODULE_LICENSE("GPL v2");
1115