1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Rockchip MIPI CSI2 DPHY driver
4 *
5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_graph.h>
14 #include <linux/of_platform.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/mfd/syscon.h>
19 #include <media/media-entity.h>
20 #include <media/v4l2-ctrls.h>
21 #include <media/v4l2-fwnode.h>
22 #include <media/v4l2-subdev.h>
23 #include <media/v4l2-device.h>
24 #include <linux/reset.h>
25 #include "phy-rockchip-csi2-dphy-common.h"
26
27 /* RK3562 DPHY GRF REG OFFSET */
28 #define RK3562_GRF_VI_CON0 (0x0520)
29 #define RK3562_GRF_VI_CON1 (0x0524)
30
31 /* GRF REG OFFSET */
32 #define GRF_VI_CON0 (0x0340)
33 #define GRF_VI_CON1 (0x0344)
34
35 /*RK3588 DPHY GRF REG OFFSET */
36 #define GRF_DPHY_CON0 (0x0)
37 #define GRF_SOC_CON2 (0x0308)
38
39 /*RV1106 DPHY GRF REG OFFSET */
40 #define GRF_VI_MISC_CON0 (0x50000)
41 #define GRF_VI_CSIPHY_CON5 (0x50014)
42
43 /*GRF REG BIT DEFINE */
44 #define GRF_CSI2PHY_LANE_SEL_SPLIT (0x1)
45 #define GRF_CSI2PHY_SEL_SPLIT_0_1 (0x0)
46 #define GRF_CSI2PHY_SEL_SPLIT_2_3 BIT(0)
47
48 /* PHY REG OFFSET */
49 #define CSI2_DPHY_CTRL_INVALID_OFFSET (0xffff)
50 #define CSI2_DPHY_CTRL_PWRCTL \
51 CSI2_DPHY_CTRL_INVALID_OFFSET
52 #define CSI2_DPHY_CTRL_LANE_ENABLE (0x00)
53 #define CSI2_DPHY_CLK1_LANE_EN (0x2C)
54 #define CSI2_DPHY_DUAL_CAL_EN (0x80)
55 #define CSI2_DPHY_CLK_INV (0X84)
56
57 #define CSI2_DPHY_CLK_WR_THS_SETTLE (0x160)
58 #define CSI2_DPHY_CLK_CALIB_EN (0x168)
59 #define CSI2_DPHY_LANE0_WR_THS_SETTLE (0x1e0)
60 #define CSI2_DPHY_LANE0_CALIB_EN (0x1e8)
61 #define CSI2_DPHY_LANE1_WR_THS_SETTLE (0x260)
62 #define CSI2_DPHY_LANE1_CALIB_EN (0x268)
63 #define CSI2_DPHY_LANE2_WR_THS_SETTLE (0x2e0)
64 #define CSI2_DPHY_LANE2_CALIB_EN (0x2e8)
65 #define CSI2_DPHY_LANE3_WR_THS_SETTLE (0x360)
66 #define CSI2_DPHY_LANE3_CALIB_EN (0x368)
67 #define CSI2_DPHY_CLK1_WR_THS_SETTLE (0x3e0)
68 #define CSI2_DPHY_CLK1_CALIB_EN (0x3e8)
69
70 #define CSI2_DPHY_PATH0_MODE_SEL (0x44C)
71 #define CSI2_DPHY_PATH0_LVDS_MODE_SEL (0x480)
72 #define CSI2_DPHY_PATH1_MODE_SEL (0x84C)
73 #define CSI2_DPHY_PATH1_LVDS_MODE_SEL (0x880)
74
75 /* PHY REG BIT DEFINE */
76 #define CSI2_DPHY_LANE_MODE_FULL (0x4)
77 #define CSI2_DPHY_LANE_MODE_SPLIT (0x2)
78 #define CSI2_DPHY_LANE_SPLIT_TOP (0x1)
79 #define CSI2_DPHY_LANE_SPLIT_BOT (0x2)
80 #define CSI2_DPHY_LANE_SPLIT_LANE0_1 (0x3 << 2)
81 #define CSI2_DPHY_LANE_SPLIT_LANE2_3 (0x3 << 4)
82 #define CSI2_DPHY_LANE_DUAL_MODE_EN BIT(6)
83 #define CSI2_DPHY_LANE_PARA_ARR_NUM (0x2)
84
85 #define CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT 2
86 #define CSI2_DPHY_CTRL_DATALANE_SPLIT_LANE2_3_OFFSET_BIT 4
87 #define CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT 6
88
89 enum csi2_dphy_index {
90 DPHY0 = 0x0,
91 DPHY1,
92 DPHY2,
93 };
94
95 enum csi2_dphy_lane {
96 CSI2_DPHY_LANE_CLOCK = 0,
97 CSI2_DPHY_LANE_CLOCK1,
98 CSI2_DPHY_LANE_DATA0,
99 CSI2_DPHY_LANE_DATA1,
100 CSI2_DPHY_LANE_DATA2,
101 CSI2_DPHY_LANE_DATA3
102 };
103
104 enum grf_reg_id {
105 GRF_DPHY_RX0_TURNDISABLE = 0,
106 GRF_DPHY_RX0_FORCERXMODE,
107 GRF_DPHY_RX0_FORCETXSTOPMODE,
108 GRF_DPHY_RX0_ENABLE,
109 GRF_DPHY_RX0_TESTCLR,
110 GRF_DPHY_RX0_TESTCLK,
111 GRF_DPHY_RX0_TESTEN,
112 GRF_DPHY_RX0_TESTDIN,
113 GRF_DPHY_RX0_TURNREQUEST,
114 GRF_DPHY_RX0_TESTDOUT,
115 GRF_DPHY_TX0_TURNDISABLE,
116 GRF_DPHY_TX0_FORCERXMODE,
117 GRF_DPHY_TX0_FORCETXSTOPMODE,
118 GRF_DPHY_TX0_TURNREQUEST,
119 GRF_DPHY_TX1RX1_TURNDISABLE,
120 GRF_DPHY_TX1RX1_FORCERXMODE,
121 GRF_DPHY_TX1RX1_FORCETXSTOPMODE,
122 GRF_DPHY_TX1RX1_ENABLE,
123 GRF_DPHY_TX1RX1_MASTERSLAVEZ,
124 GRF_DPHY_TX1RX1_BASEDIR,
125 GRF_DPHY_TX1RX1_ENABLECLK,
126 GRF_DPHY_TX1RX1_TURNREQUEST,
127 GRF_DPHY_RX1_SRC_SEL,
128 /* rk3288 only */
129 GRF_CON_DISABLE_ISP,
130 GRF_CON_ISP_DPHY_SEL,
131 GRF_DSI_CSI_TESTBUS_SEL,
132 GRF_DVP_V18SEL,
133 /* rk1808 & rk3326 & rv1126 */
134 GRF_DPHY_CSI2PHY_FORCERXMODE,
135 GRF_DPHY_CSI2PHY_CLKLANE_EN,
136 GRF_DPHY_CSI2PHY_DATALANE_EN,
137 /* rv1126 only */
138 GRF_DPHY_CLK_INV_SEL,
139 GRF_DPHY_SEL,
140 /* rk3368 only */
141 GRF_ISP_MIPI_CSI_HOST_SEL,
142 /* below is for rk3399 only */
143 GRF_DPHY_RX0_CLK_INV_SEL,
144 GRF_DPHY_RX1_CLK_INV_SEL,
145 GRF_DPHY_TX1RX1_SRC_SEL,
146 /* below is for rk3568 only */
147 GRF_DPHY_CSI2PHY_CLKLANE1_EN,
148 GRF_DPHY_CLK1_INV_SEL,
149 GRF_DPHY_ISP_CSI2PHY_SEL,
150 GRF_DPHY_CIF_CSI2PHY_SEL,
151 GRF_DPHY_CSI2PHY_LANE_SEL,
152 GRF_DPHY_CSI2PHY1_LANE_SEL,
153 GRF_DPHY_CSI2PHY_DATALANE_EN0,
154 GRF_DPHY_CSI2PHY_DATALANE_EN1,
155 GRF_CPHY_MODE,
156 GRF_DPHY_CSIHOST2_SEL,
157 GRF_DPHY_CSIHOST3_SEL,
158 GRF_DPHY_CSIHOST4_SEL,
159 GRF_DPHY_CSIHOST5_SEL,
160 /* below is for rv1106 only */
161 GRF_MIPI_HOST0_SEL,
162 GRF_LVDS_HOST0_SEL,
163 /* below is for rk3562 */
164 GRF_DPHY1_CLK_INV_SEL,
165 GRF_DPHY1_CLK1_INV_SEL,
166 GRF_DPHY1_CSI2PHY_CLKLANE1_EN,
167 GRF_DPHY1_CSI2PHY_FORCERXMODE,
168 GRF_DPHY1_CSI2PHY_CLKLANE_EN,
169 GRF_DPHY1_CSI2PHY_DATALANE_EN,
170 GRF_DPHY1_CSI2PHY_DATALANE_EN0,
171 GRF_DPHY1_CSI2PHY_DATALANE_EN1,
172 };
173
174 enum csi2dphy_reg_id {
175 CSI2PHY_REG_CTRL_LANE_ENABLE = 0,
176 CSI2PHY_CTRL_PWRCTL,
177 CSI2PHY_CTRL_DIG_RST,
178 CSI2PHY_CLK_THS_SETTLE,
179 CSI2PHY_LANE0_THS_SETTLE,
180 CSI2PHY_LANE1_THS_SETTLE,
181 CSI2PHY_LANE2_THS_SETTLE,
182 CSI2PHY_LANE3_THS_SETTLE,
183 CSI2PHY_CLK_CALIB_ENABLE,
184 CSI2PHY_LANE0_CALIB_ENABLE,
185 CSI2PHY_LANE1_CALIB_ENABLE,
186 CSI2PHY_LANE2_CALIB_ENABLE,
187 CSI2PHY_LANE3_CALIB_ENABLE,
188 //rv1126 only
189 CSI2PHY_MIPI_LVDS_MODEL,
190 CSI2PHY_LVDS_MODE,
191 //rk3568 only
192 CSI2PHY_DUAL_CLK_EN,
193 CSI2PHY_CLK1_THS_SETTLE,
194 CSI2PHY_CLK1_CALIB_ENABLE,
195 //rk3588
196 CSI2PHY_CLK_LANE_ENABLE,
197 CSI2PHY_CLK1_LANE_ENABLE,
198 CSI2PHY_DATA_LANE0_ENABLE,
199 CSI2PHY_DATA_LANE1_ENABLE,
200 CSI2PHY_DATA_LANE2_ENABLE,
201 CSI2PHY_DATA_LANE3_ENABLE,
202 CSI2PHY_LANE0_ERR_SOT_SYNC,
203 CSI2PHY_LANE1_ERR_SOT_SYNC,
204 CSI2PHY_LANE2_ERR_SOT_SYNC,
205 CSI2PHY_LANE3_ERR_SOT_SYNC,
206 CSI2PHY_S0C_GNR_CON1,
207 CSI2PHY_COMBO_S0D0_GNR_CON1,
208 CSI2PHY_COMBO_S0D1_GNR_CON1,
209 CSI2PHY_COMBO_S0D2_GNR_CON1,
210 CSI2PHY_S0D3_GNR_CON1,
211 CSI2PHY_PATH0_MODEL,
212 CSI2PHY_PATH0_LVDS_MODEL,
213 CSI2PHY_PATH1_MODEL,
214 CSI2PHY_PATH1_LVDS_MODEL,
215 CSI2PHY_CLK_INV,
216 };
217
218 #define HIWORD_UPDATE(val, mask, shift) \
219 ((val) << (shift) | (mask) << ((shift) + 16))
220
221 #define GRF_REG(_offset, _width, _shift) \
222 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
223
224 #define CSI2PHY_REG(_offset) \
225 { .offset = _offset, }
226
227 struct hsfreq_range {
228 u32 range_h;
229 u16 cfg_bit;
230 };
231
write_sys_grf_reg(struct csi2_dphy_hw * hw,int index,u8 value)232 static inline void write_sys_grf_reg(struct csi2_dphy_hw *hw,
233 int index, u8 value)
234 {
235 const struct grf_reg *reg = &hw->grf_regs[index];
236 unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift);
237
238 if (reg->mask)
239 regmap_write(hw->regmap_sys_grf, reg->offset, val);
240 }
241
write_grf_reg(struct csi2_dphy_hw * hw,int index,u8 value)242 static inline void write_grf_reg(struct csi2_dphy_hw *hw,
243 int index, u8 value)
244 {
245 const struct grf_reg *reg = &hw->grf_regs[index];
246 unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift);
247
248 if (reg->mask)
249 regmap_write(hw->regmap_grf, reg->offset, val);
250 }
251
read_grf_reg(struct csi2_dphy_hw * hw,int index)252 static inline u32 read_grf_reg(struct csi2_dphy_hw *hw, int index)
253 {
254 const struct grf_reg *reg = &hw->grf_regs[index];
255 unsigned int val = 0;
256
257 if (reg->mask) {
258 regmap_read(hw->regmap_grf, reg->offset, &val);
259 val = (val >> reg->shift) & reg->mask;
260 }
261
262 return val;
263 }
264
write_csi2_dphy_reg(struct csi2_dphy_hw * hw,int index,u32 value)265 static inline void write_csi2_dphy_reg(struct csi2_dphy_hw *hw,
266 int index, u32 value)
267 {
268 const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
269
270 if ((index == CSI2PHY_REG_CTRL_LANE_ENABLE) ||
271 (index == CSI2PHY_CLK_LANE_ENABLE) ||
272 (index != CSI2PHY_REG_CTRL_LANE_ENABLE &&
273 reg->offset != 0x0))
274 writel(value, hw->hw_base_addr + reg->offset);
275 }
276
write_csi2_dphy_reg_mask(struct csi2_dphy_hw * hw,int index,u32 value,u32 mask)277 static inline void write_csi2_dphy_reg_mask(struct csi2_dphy_hw *hw,
278 int index, u32 value, u32 mask)
279 {
280 const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
281 u32 read_val = 0;
282
283 read_val = readl(hw->hw_base_addr + reg->offset);
284 read_val &= ~mask;
285 read_val |= value;
286 writel(read_val, hw->hw_base_addr + reg->offset);
287 }
288
read_csi2_dphy_reg(struct csi2_dphy_hw * hw,int index,u32 * value)289 static inline void read_csi2_dphy_reg(struct csi2_dphy_hw *hw,
290 int index, u32 *value)
291 {
292 const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
293
294 if ((index == CSI2PHY_REG_CTRL_LANE_ENABLE) ||
295 (index == CSI2PHY_CLK_LANE_ENABLE) ||
296 (index != CSI2PHY_REG_CTRL_LANE_ENABLE &&
297 reg->offset != 0x0))
298 *value = readl(hw->hw_base_addr + reg->offset);
299 }
300
csi_mipidphy_wr_ths_settle(struct csi2_dphy_hw * hw,int hsfreq,enum csi2_dphy_lane lane)301 static void csi_mipidphy_wr_ths_settle(struct csi2_dphy_hw *hw,
302 int hsfreq,
303 enum csi2_dphy_lane lane)
304 {
305 unsigned int val = 0;
306 unsigned int offset;
307
308 switch (lane) {
309 case CSI2_DPHY_LANE_CLOCK:
310 offset = CSI2PHY_CLK_THS_SETTLE;
311 break;
312 case CSI2_DPHY_LANE_CLOCK1:
313 offset = CSI2PHY_CLK1_THS_SETTLE;
314 break;
315 case CSI2_DPHY_LANE_DATA0:
316 offset = CSI2PHY_LANE0_THS_SETTLE;
317 break;
318 case CSI2_DPHY_LANE_DATA1:
319 offset = CSI2PHY_LANE1_THS_SETTLE;
320 break;
321 case CSI2_DPHY_LANE_DATA2:
322 offset = CSI2PHY_LANE2_THS_SETTLE;
323 break;
324 case CSI2_DPHY_LANE_DATA3:
325 offset = CSI2PHY_LANE3_THS_SETTLE;
326 break;
327 default:
328 return;
329 }
330
331 read_csi2_dphy_reg(hw, offset, &val);
332 val = (val & ~0x7f) | hsfreq;
333 write_csi2_dphy_reg(hw, offset, val);
334 }
335
336 static const struct grf_reg rk3568_grf_dphy_regs[] = {
337 [GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(GRF_VI_CON0, 4, 0),
338 [GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(GRF_VI_CON0, 4, 4),
339 [GRF_DPHY_CSI2PHY_DATALANE_EN0] = GRF_REG(GRF_VI_CON0, 2, 4),
340 [GRF_DPHY_CSI2PHY_DATALANE_EN1] = GRF_REG(GRF_VI_CON0, 2, 6),
341 [GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(GRF_VI_CON0, 1, 8),
342 [GRF_DPHY_CLK_INV_SEL] = GRF_REG(GRF_VI_CON0, 1, 9),
343 [GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(GRF_VI_CON0, 1, 10),
344 [GRF_DPHY_CLK1_INV_SEL] = GRF_REG(GRF_VI_CON0, 1, 11),
345 [GRF_DPHY_ISP_CSI2PHY_SEL] = GRF_REG(GRF_VI_CON1, 1, 12),
346 [GRF_DPHY_CIF_CSI2PHY_SEL] = GRF_REG(GRF_VI_CON1, 1, 11),
347 [GRF_DPHY_CSI2PHY_LANE_SEL] = GRF_REG(GRF_VI_CON1, 1, 7),
348 };
349
350 static const struct csi2dphy_reg rk3568_csi2dphy_regs[] = {
351 [CSI2PHY_REG_CTRL_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CTRL_LANE_ENABLE),
352 [CSI2PHY_DUAL_CLK_EN] = CSI2PHY_REG(CSI2_DPHY_DUAL_CAL_EN),
353 [CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK_WR_THS_SETTLE),
354 [CSI2PHY_CLK_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK_CALIB_EN),
355 [CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_WR_THS_SETTLE),
356 [CSI2PHY_LANE0_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_CALIB_EN),
357 [CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_WR_THS_SETTLE),
358 [CSI2PHY_LANE1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_CALIB_EN),
359 [CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_WR_THS_SETTLE),
360 [CSI2PHY_LANE2_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_CALIB_EN),
361 [CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_WR_THS_SETTLE),
362 [CSI2PHY_LANE3_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_CALIB_EN),
363 [CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE),
364 [CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
365 };
366
367 static const struct grf_reg rk3588_grf_dphy_regs[] = {
368 [GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(GRF_DPHY_CON0, 4, 0),
369 [GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(GRF_DPHY_CON0, 4, 4),
370 [GRF_DPHY_CSI2PHY_DATALANE_EN0] = GRF_REG(GRF_DPHY_CON0, 2, 4),
371 [GRF_DPHY_CSI2PHY_DATALANE_EN1] = GRF_REG(GRF_DPHY_CON0, 2, 6),
372 [GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(GRF_DPHY_CON0, 1, 8),
373 [GRF_DPHY_CLK_INV_SEL] = GRF_REG(GRF_DPHY_CON0, 1, 9),
374 [GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(GRF_DPHY_CON0, 1, 10),
375 [GRF_DPHY_CLK1_INV_SEL] = GRF_REG(GRF_DPHY_CON0, 1, 11),
376 [GRF_DPHY_CSI2PHY_LANE_SEL] = GRF_REG(GRF_SOC_CON2, 1, 6),
377 [GRF_DPHY_CSI2PHY1_LANE_SEL] = GRF_REG(GRF_SOC_CON2, 1, 7),
378 [GRF_DPHY_CSIHOST2_SEL] = GRF_REG(GRF_SOC_CON2, 1, 8),
379 [GRF_DPHY_CSIHOST3_SEL] = GRF_REG(GRF_SOC_CON2, 1, 9),
380 [GRF_DPHY_CSIHOST4_SEL] = GRF_REG(GRF_SOC_CON2, 1, 10),
381 [GRF_DPHY_CSIHOST5_SEL] = GRF_REG(GRF_SOC_CON2, 1, 11),
382 };
383
384 static const struct csi2dphy_reg rk3588_csi2dphy_regs[] = {
385 [CSI2PHY_REG_CTRL_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CTRL_LANE_ENABLE),
386 [CSI2PHY_DUAL_CLK_EN] = CSI2PHY_REG(CSI2_DPHY_DUAL_CAL_EN),
387 [CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK_WR_THS_SETTLE),
388 [CSI2PHY_CLK_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK_CALIB_EN),
389 [CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_WR_THS_SETTLE),
390 [CSI2PHY_LANE0_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_CALIB_EN),
391 [CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_WR_THS_SETTLE),
392 [CSI2PHY_LANE1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_CALIB_EN),
393 [CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_WR_THS_SETTLE),
394 [CSI2PHY_LANE2_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_CALIB_EN),
395 [CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_WR_THS_SETTLE),
396 [CSI2PHY_LANE3_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_CALIB_EN),
397 [CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE),
398 [CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
399 [CSI2PHY_CLK1_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_LANE_EN),
400 };
401
402 static const struct grf_reg rv1106_grf_dphy_regs[] = {
403 [GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(GRF_VI_CSIPHY_CON5, 4, 0),
404 [GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(GRF_VI_CSIPHY_CON5, 1, 8),
405 [GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(GRF_VI_CSIPHY_CON5, 4, 4),
406 [GRF_DPHY_CSI2PHY_DATALANE_EN0] = GRF_REG(GRF_VI_CSIPHY_CON5, 2, 4),
407 [GRF_DPHY_CSI2PHY_DATALANE_EN1] = GRF_REG(GRF_VI_CSIPHY_CON5, 2, 6),
408 [GRF_DPHY_CLK_INV_SEL] = GRF_REG(GRF_VI_CSIPHY_CON5, 1, 9),
409 [GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(GRF_VI_CSIPHY_CON5, 1, 10),
410 [GRF_DPHY_CLK1_INV_SEL] = GRF_REG(GRF_VI_CSIPHY_CON5, 1, 11),
411 [GRF_MIPI_HOST0_SEL] = GRF_REG(GRF_VI_MISC_CON0, 1, 0),
412 [GRF_LVDS_HOST0_SEL] = GRF_REG(GRF_VI_MISC_CON0, 1, 2),
413 };
414
415 static const struct csi2dphy_reg rv1106_csi2dphy_regs[] = {
416 [CSI2PHY_REG_CTRL_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CTRL_LANE_ENABLE),
417 [CSI2PHY_DUAL_CLK_EN] = CSI2PHY_REG(CSI2_DPHY_DUAL_CAL_EN),
418 [CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK_WR_THS_SETTLE),
419 [CSI2PHY_CLK_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK_CALIB_EN),
420 [CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_WR_THS_SETTLE),
421 [CSI2PHY_LANE0_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_CALIB_EN),
422 [CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_WR_THS_SETTLE),
423 [CSI2PHY_LANE1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_CALIB_EN),
424 [CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_WR_THS_SETTLE),
425 [CSI2PHY_LANE2_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_CALIB_EN),
426 [CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_WR_THS_SETTLE),
427 [CSI2PHY_LANE3_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_CALIB_EN),
428 [CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE),
429 [CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
430 [CSI2PHY_CLK1_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_LANE_EN),
431 [CSI2PHY_PATH0_MODEL] = CSI2PHY_REG(CSI2_DPHY_PATH0_MODE_SEL),
432 [CSI2PHY_PATH0_LVDS_MODEL] = CSI2PHY_REG(CSI2_DPHY_PATH0_LVDS_MODE_SEL),
433 [CSI2PHY_PATH1_MODEL] = CSI2PHY_REG(CSI2_DPHY_PATH1_MODE_SEL),
434 [CSI2PHY_PATH1_LVDS_MODEL] = CSI2PHY_REG(CSI2_DPHY_PATH1_LVDS_MODE_SEL),
435 [CSI2PHY_CLK_INV] = CSI2PHY_REG(CSI2_DPHY_CLK_INV),
436 };
437
438 static const struct grf_reg rk3562_grf_dphy_regs[] = {
439 [GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(RK3562_GRF_VI_CON0, 4, 0),
440 [GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(RK3562_GRF_VI_CON0, 4, 4),
441 [GRF_DPHY_CSI2PHY_DATALANE_EN0] = GRF_REG(RK3562_GRF_VI_CON0, 2, 4),
442 [GRF_DPHY_CSI2PHY_DATALANE_EN1] = GRF_REG(RK3562_GRF_VI_CON0, 2, 6),
443 [GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(RK3562_GRF_VI_CON0, 1, 8),
444 [GRF_DPHY_CLK_INV_SEL] = GRF_REG(RK3562_GRF_VI_CON0, 1, 9),
445 [GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(RK3562_GRF_VI_CON0, 1, 10),
446 [GRF_DPHY_CLK1_INV_SEL] = GRF_REG(RK3562_GRF_VI_CON0, 1, 11),
447 [GRF_DPHY_CSI2PHY_LANE_SEL] = GRF_REG(RK3562_GRF_VI_CON0, 1, 12),
448 [GRF_DPHY_CSI2PHY1_LANE_SEL] = GRF_REG(RK3562_GRF_VI_CON0, 1, 13),
449 [GRF_DPHY1_CSI2PHY_FORCERXMODE] = GRF_REG(RK3562_GRF_VI_CON1, 4, 0),
450 [GRF_DPHY1_CSI2PHY_DATALANE_EN] = GRF_REG(RK3562_GRF_VI_CON1, 4, 4),
451 [GRF_DPHY1_CSI2PHY_DATALANE_EN0] = GRF_REG(RK3562_GRF_VI_CON1, 2, 4),
452 [GRF_DPHY1_CSI2PHY_DATALANE_EN1] = GRF_REG(RK3562_GRF_VI_CON1, 2, 6),
453 [GRF_DPHY1_CSI2PHY_CLKLANE_EN] = GRF_REG(RK3562_GRF_VI_CON1, 1, 8),
454 [GRF_DPHY1_CLK_INV_SEL] = GRF_REG(RK3562_GRF_VI_CON1, 1, 9),
455 [GRF_DPHY1_CSI2PHY_CLKLANE1_EN] = GRF_REG(RK3562_GRF_VI_CON1, 1, 10),
456 [GRF_DPHY1_CLK1_INV_SEL] = GRF_REG(RK3562_GRF_VI_CON1, 1, 11),
457 };
458
459 static const struct csi2dphy_reg rk3562_csi2dphy_regs[] = {
460 [CSI2PHY_REG_CTRL_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CTRL_LANE_ENABLE),
461 [CSI2PHY_DUAL_CLK_EN] = CSI2PHY_REG(CSI2_DPHY_DUAL_CAL_EN),
462 [CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK_WR_THS_SETTLE),
463 [CSI2PHY_CLK_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK_CALIB_EN),
464 [CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_WR_THS_SETTLE),
465 [CSI2PHY_LANE0_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_CALIB_EN),
466 [CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_WR_THS_SETTLE),
467 [CSI2PHY_LANE1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_CALIB_EN),
468 [CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_WR_THS_SETTLE),
469 [CSI2PHY_LANE2_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_CALIB_EN),
470 [CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_WR_THS_SETTLE),
471 [CSI2PHY_LANE3_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_CALIB_EN),
472 [CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE),
473 [CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
474 [CSI2PHY_CLK1_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_LANE_EN),
475 };
476
477 /* These tables must be sorted by .range_h ascending. */
478 static const struct hsfreq_range rk3568_csi2_dphy_hw_hsfreq_ranges[] = {
479 { 109, 0x02}, { 149, 0x03}, { 199, 0x06}, { 249, 0x06},
480 { 299, 0x06}, { 399, 0x08}, { 499, 0x0b}, { 599, 0x0e},
481 { 699, 0x10}, { 799, 0x12}, { 999, 0x16}, {1199, 0x1e},
482 {1399, 0x23}, {1599, 0x2d}, {1799, 0x32}, {1999, 0x37},
483 {2199, 0x3c}, {2399, 0x41}, {2499, 0x46}
484 };
485
get_remote_sensor(struct v4l2_subdev * sd)486 static struct v4l2_subdev *get_remote_sensor(struct v4l2_subdev *sd)
487 {
488 struct media_pad *local, *remote;
489 struct media_entity *sensor_me;
490
491 local = &sd->entity.pads[CSI2_DPHY_RX_PAD_SINK];
492 remote = media_entity_remote_pad(local);
493 if (!remote) {
494 v4l2_warn(sd, "No link between dphy and sensor\n");
495 return NULL;
496 }
497
498 sensor_me = media_entity_remote_pad(local)->entity;
499 return media_entity_to_v4l2_subdev(sensor_me);
500 }
501
sd_to_sensor(struct csi2_dphy * dphy,struct v4l2_subdev * sd)502 static struct csi2_sensor *sd_to_sensor(struct csi2_dphy *dphy,
503 struct v4l2_subdev *sd)
504 {
505 int i;
506
507 for (i = 0; i < dphy->num_sensors; ++i)
508 if (dphy->sensors[i].sd == sd)
509 return &dphy->sensors[i];
510
511 return NULL;
512 }
513
get_lvds_data_width(u32 pixelformat)514 static unsigned char get_lvds_data_width(u32 pixelformat)
515 {
516 switch (pixelformat) {
517 /* csi raw8 */
518 case MEDIA_BUS_FMT_SBGGR8_1X8:
519 case MEDIA_BUS_FMT_SGBRG8_1X8:
520 case MEDIA_BUS_FMT_SGRBG8_1X8:
521 case MEDIA_BUS_FMT_SRGGB8_1X8:
522 return 0x2;
523 /* csi raw10 */
524 case MEDIA_BUS_FMT_SBGGR10_1X10:
525 case MEDIA_BUS_FMT_SGBRG10_1X10:
526 case MEDIA_BUS_FMT_SGRBG10_1X10:
527 case MEDIA_BUS_FMT_SRGGB10_1X10:
528 return 0x0;
529 /* csi raw12 */
530 case MEDIA_BUS_FMT_SBGGR12_1X12:
531 case MEDIA_BUS_FMT_SGBRG12_1X12:
532 case MEDIA_BUS_FMT_SGRBG12_1X12:
533 case MEDIA_BUS_FMT_SRGGB12_1X12:
534 return 0x1;
535 /* csi uyvy 422 */
536 case MEDIA_BUS_FMT_UYVY8_2X8:
537 case MEDIA_BUS_FMT_VYUY8_2X8:
538 case MEDIA_BUS_FMT_YUYV8_2X8:
539 case MEDIA_BUS_FMT_YVYU8_2X8:
540 case MEDIA_BUS_FMT_RGB888_1X24:
541 return 0x2;
542
543 default:
544 return 0x2;
545 }
546 }
547
csi2_dphy_hw_do_reset(struct csi2_dphy_hw * hw)548 static void csi2_dphy_hw_do_reset(struct csi2_dphy_hw *hw)
549 {
550 if (hw->rsts_bulk)
551 reset_control_assert(hw->rsts_bulk);
552
553 udelay(5);
554
555 if (hw->rsts_bulk)
556 reset_control_deassert(hw->rsts_bulk);
557 }
558
csi2_dphy_config_dual_mode(struct csi2_dphy * dphy,struct csi2_sensor * sensor)559 static void csi2_dphy_config_dual_mode(struct csi2_dphy *dphy,
560 struct csi2_sensor *sensor)
561 {
562 struct csi2_dphy_hw *hw = dphy->dphy_hw;
563 struct v4l2_subdev *sd = &dphy->sd;
564 bool is_cif = false;
565 char *model;
566 u32 val;
567
568 model = sd->v4l2_dev->mdev->model;
569 if (!strncmp(model, "rkcif_mipi_lvds", sizeof("rkcif_mipi_lvds") - 1))
570 is_cif = true;
571 else
572 is_cif = false;
573
574 if (hw->lane_mode == LANE_MODE_FULL) {
575 val = !GRF_CSI2PHY_LANE_SEL_SPLIT;
576 if (dphy->phy_index < 3) {
577 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN,
578 GENMASK(sensor->lanes - 1, 0));
579 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
580 if (hw->drv_data->chip_id != CHIP_ID_RK3588)
581 write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
582 else
583 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
584 } else {
585 if (hw->drv_data->chip_id <= CHIP_ID_RK3588) {
586 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN,
587 GENMASK(sensor->lanes - 1, 0));
588 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
589 } else {
590 write_grf_reg(hw, GRF_DPHY1_CSI2PHY_DATALANE_EN,
591 GENMASK(sensor->lanes - 1, 0));
592 write_grf_reg(hw, GRF_DPHY1_CSI2PHY_CLKLANE_EN, 0x1);
593 }
594 if (hw->drv_data->chip_id != CHIP_ID_RK3588)
595 write_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
596 else
597 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
598 }
599 } else {
600 val = GRF_CSI2PHY_LANE_SEL_SPLIT;
601
602 switch (dphy->phy_index) {
603 case 1:
604 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN0,
605 GENMASK(sensor->lanes - 1, 0));
606 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
607 if (hw->drv_data->chip_id < CHIP_ID_RK3588) {
608 write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
609 if (is_cif)
610 write_grf_reg(hw, GRF_DPHY_CIF_CSI2PHY_SEL,
611 GRF_CSI2PHY_SEL_SPLIT_0_1);
612 else
613 write_grf_reg(hw, GRF_DPHY_ISP_CSI2PHY_SEL,
614 GRF_CSI2PHY_SEL_SPLIT_0_1);
615 } else if (hw->drv_data->chip_id == CHIP_ID_RK3588) {
616 write_sys_grf_reg(hw, GRF_DPHY_CSIHOST2_SEL, 0x0);
617 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
618 } else if (hw->drv_data->chip_id == CHIP_ID_RV1106) {
619 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY)
620 write_grf_reg(hw, GRF_MIPI_HOST0_SEL, 0x1);
621 else
622 write_grf_reg(hw, GRF_LVDS_HOST0_SEL, 0x1);
623 } else if (hw->drv_data->chip_id == CHIP_ID_RK3562) {
624 write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
625 }
626 break;
627 case 2:
628 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN1,
629 GENMASK(sensor->lanes - 1, 0));
630 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE1_EN, 0x1);
631 if (hw->drv_data->chip_id < CHIP_ID_RK3588) {
632 write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
633 if (is_cif)
634 write_grf_reg(hw, GRF_DPHY_CIF_CSI2PHY_SEL,
635 GRF_CSI2PHY_SEL_SPLIT_2_3);
636 else
637 write_grf_reg(hw, GRF_DPHY_ISP_CSI2PHY_SEL,
638 GRF_CSI2PHY_SEL_SPLIT_2_3);
639 } else if (hw->drv_data->chip_id == CHIP_ID_RK3588) {
640 write_sys_grf_reg(hw, GRF_DPHY_CSIHOST3_SEL, 0x1);
641 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
642 } else if (hw->drv_data->chip_id == CHIP_ID_RK3562) {
643 write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
644 }
645 break;
646 case 4:
647 if (hw->drv_data->chip_id == CHIP_ID_RK3588) {
648 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
649 write_sys_grf_reg(hw, GRF_DPHY_CSIHOST4_SEL, 0x0);
650 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN0,
651 GENMASK(sensor->lanes - 1, 0));
652 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
653 } else if (hw->drv_data->chip_id == CHIP_ID_RK3562) {
654 write_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
655 write_grf_reg(hw, GRF_DPHY1_CSI2PHY_DATALANE_EN0,
656 GENMASK(sensor->lanes - 1, 0));
657 write_grf_reg(hw, GRF_DPHY1_CSI2PHY_CLKLANE_EN, 0x1);
658 }
659 break;
660 case 5:
661 if (hw->drv_data->chip_id == CHIP_ID_RK3588) {
662 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
663 write_sys_grf_reg(hw, GRF_DPHY_CSIHOST5_SEL, 0x1);
664 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN1,
665 GENMASK(sensor->lanes - 1, 0));
666 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE1_EN, 0x1);
667 } else if (hw->drv_data->chip_id == CHIP_ID_RK3562) {
668 write_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
669 write_grf_reg(hw, GRF_DPHY1_CSI2PHY_DATALANE_EN1,
670 GENMASK(sensor->lanes - 1, 0));
671 write_grf_reg(hw, GRF_DPHY1_CSI2PHY_CLKLANE1_EN, 0x1);
672 }
673 break;
674 default:
675 break;
676 };
677 }
678 }
679
csi2_dphy_hw_stream_on(struct csi2_dphy * dphy,struct v4l2_subdev * sd)680 static int csi2_dphy_hw_stream_on(struct csi2_dphy *dphy,
681 struct v4l2_subdev *sd)
682 {
683 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
684 struct csi2_sensor *sensor;
685 struct csi2_dphy_hw *hw = dphy->dphy_hw;
686 const struct dphy_hw_drv_data *drv_data = hw->drv_data;
687 const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
688 int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
689 int i, hsfreq = 0;
690 u32 val = 0, pre_val;
691 u8 lvds_width = 0;
692
693 if (!sensor_sd)
694 return -ENODEV;
695 sensor = sd_to_sensor(dphy, sensor_sd);
696 if (!sensor)
697 return -ENODEV;
698
699 mutex_lock(&hw->mutex);
700
701 /* set data lane num and enable clock lane */
702 /*
703 * for rk356x: dphy0 is used just for full mode,
704 * dphy1 is used just for split mode,uses lane0_1,
705 * dphy2 is used just for split mode,uses lane2_3
706 */
707 read_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, &pre_val);
708 if (hw->lane_mode == LANE_MODE_FULL) {
709 val |= (GENMASK(sensor->lanes - 1, 0) <<
710 CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT) |
711 (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
712 } else {
713 if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT)))
714 val |= (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
715
716 if (dphy->phy_index % 3 == DPHY1)
717 val |= (GENMASK(sensor->lanes - 1, 0) <<
718 CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT);
719
720 if (dphy->phy_index % 3 == DPHY2) {
721 val |= (GENMASK(sensor->lanes - 1, 0) <<
722 CSI2_DPHY_CTRL_DATALANE_SPLIT_LANE2_3_OFFSET_BIT);
723 if (hw->drv_data->chip_id >= CHIP_ID_RK3588)
724 write_csi2_dphy_reg(hw, CSI2PHY_CLK1_LANE_ENABLE, BIT(6));
725 }
726 }
727 val |= pre_val;
728 write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, val);
729
730 /* Reset dphy digital part */
731 if (hw->lane_mode == LANE_MODE_FULL) {
732 write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x1e);
733 write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x1f);
734 } else {
735 read_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, &val);
736 if (!(val & CSI2_DPHY_LANE_DUAL_MODE_EN)) {
737 write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5e);
738 write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5f);
739 }
740 }
741 csi2_dphy_config_dual_mode(dphy, sensor);
742
743 /* not into receive mode/wait stopstate */
744 write_grf_reg(hw, GRF_DPHY_CSI2PHY_FORCERXMODE, 0x0);
745
746 /* enable calibration */
747 if (dphy->data_rate_mbps > 1500) {
748 if (hw->lane_mode == LANE_MODE_FULL) {
749 write_csi2_dphy_reg(hw, CSI2PHY_CLK_CALIB_ENABLE, 0x80);
750 if (sensor->lanes > 0x00)
751 write_csi2_dphy_reg(hw, CSI2PHY_LANE0_CALIB_ENABLE, 0x80);
752 if (sensor->lanes > 0x01)
753 write_csi2_dphy_reg(hw, CSI2PHY_LANE1_CALIB_ENABLE, 0x80);
754 if (sensor->lanes > 0x02)
755 write_csi2_dphy_reg(hw, CSI2PHY_LANE2_CALIB_ENABLE, 0x80);
756 if (sensor->lanes > 0x03)
757 write_csi2_dphy_reg(hw, CSI2PHY_LANE3_CALIB_ENABLE, 0x80);
758 } else {
759 if (dphy->phy_index % 3 == DPHY1) {
760 write_csi2_dphy_reg(hw, CSI2PHY_CLK_CALIB_ENABLE, 0x80);
761 if (sensor->lanes > 0x00)
762 write_csi2_dphy_reg(hw, CSI2PHY_LANE0_CALIB_ENABLE, 0x80);
763 if (sensor->lanes > 0x01)
764 write_csi2_dphy_reg(hw, CSI2PHY_LANE1_CALIB_ENABLE, 0x80);
765 }
766
767 if (dphy->phy_index % 3 == DPHY2) {
768 write_csi2_dphy_reg(hw, CSI2PHY_CLK1_CALIB_ENABLE, 0x80);
769 if (sensor->lanes > 0x00)
770 write_csi2_dphy_reg(hw, CSI2PHY_LANE2_CALIB_ENABLE, 0x80);
771 if (sensor->lanes > 0x01)
772 write_csi2_dphy_reg(hw, CSI2PHY_LANE3_CALIB_ENABLE, 0x80);
773 }
774 }
775 }
776
777 /* set clock lane and data lane */
778 for (i = 0; i < num_hsfreq_ranges; i++) {
779 if (hsfreq_ranges[i].range_h >= dphy->data_rate_mbps) {
780 hsfreq = hsfreq_ranges[i].cfg_bit;
781 break;
782 }
783 }
784
785 if (i == num_hsfreq_ranges) {
786 i = num_hsfreq_ranges - 1;
787 dev_warn(dphy->dev, "data rate: %lld mbps, max support %d mbps",
788 dphy->data_rate_mbps, hsfreq_ranges[i].range_h + 1);
789 hsfreq = hsfreq_ranges[i].cfg_bit;
790 }
791
792 if (hw->lane_mode == LANE_MODE_FULL) {
793 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_CLOCK);
794 if (sensor->lanes > 0x00)
795 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA0);
796 if (sensor->lanes > 0x01)
797 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA1);
798 if (sensor->lanes > 0x02)
799 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA2);
800 if (sensor->lanes > 0x03)
801 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA3);
802 } else {
803 if (dphy->phy_index % 3 == DPHY1) {
804 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_CLOCK);
805 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA0);
806 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA1);
807 }
808
809 if (dphy->phy_index % 3 == DPHY2) {
810 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_CLOCK1);
811 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA2);
812 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA3);
813 }
814 }
815
816 if (hw->drv_data->chip_id == CHIP_ID_RV1106) {
817 if (dphy->phy_index % 3 == DPHY0 ||
818 dphy->phy_index % 3 == DPHY1) {
819 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
820 write_csi2_dphy_reg(hw, CSI2PHY_PATH0_MODEL, 0x2);
821 } else {
822 write_csi2_dphy_reg(hw, CSI2PHY_PATH0_MODEL, 0x4);
823 lvds_width = get_lvds_data_width(sensor->format.code);
824 write_csi2_dphy_reg(hw, CSI2PHY_PATH0_LVDS_MODEL, (lvds_width << 4) | 0X0f);
825 }
826 } else {
827 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
828 write_csi2_dphy_reg(hw, CSI2PHY_PATH1_MODEL, 0x2);
829 } else {
830 write_csi2_dphy_reg(hw, CSI2PHY_PATH1_MODEL, 0x4);
831 lvds_width = get_lvds_data_width(sensor->format.code);
832 write_csi2_dphy_reg(hw, CSI2PHY_PATH1_LVDS_MODEL, (lvds_width << 4) | 0X0f);
833 }
834 }
835 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
836 if (hw->lane_mode == LANE_MODE_FULL)
837 write_csi2_dphy_reg(hw, CSI2PHY_CLK_INV, 0x04);
838 else
839 write_csi2_dphy_reg(hw, CSI2PHY_CLK_INV, 0x14);
840 }
841 }
842
843 atomic_inc(&hw->stream_cnt);
844
845 mutex_unlock(&hw->mutex);
846
847 return 0;
848 }
849
csi2_dphy_hw_stream_off(struct csi2_dphy * dphy,struct v4l2_subdev * sd)850 static int csi2_dphy_hw_stream_off(struct csi2_dphy *dphy,
851 struct v4l2_subdev *sd)
852 {
853 struct csi2_dphy_hw *hw = dphy->dphy_hw;
854
855 if (atomic_dec_return(&hw->stream_cnt))
856 return 0;
857
858 mutex_lock(&hw->mutex);
859
860 write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, 0x01);
861 csi2_dphy_hw_do_reset(hw);
862 usleep_range(500, 1000);
863
864 mutex_unlock(&hw->mutex);
865
866 return 0;
867 }
868
csi2_dphy_hw_ttl_mode_enable(struct csi2_dphy_hw * hw)869 static int csi2_dphy_hw_ttl_mode_enable(struct csi2_dphy_hw *hw)
870 {
871 int ret = 0;
872
873 ret = clk_bulk_prepare_enable(hw->num_clks, hw->clks_bulk);
874 if (ret) {
875 dev_err(hw->dev, "failed to enable clks\n");
876 return ret;
877 }
878
879 write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, 0x7d);
880 write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5f);
881 write_csi2_dphy_reg(hw, CSI2PHY_PATH0_MODEL, 0x1);
882 write_csi2_dphy_reg(hw, CSI2PHY_PATH1_MODEL, 0x1);
883 return ret;
884 }
885
csi2_dphy_hw_ttl_mode_disable(struct csi2_dphy_hw * hw)886 static void csi2_dphy_hw_ttl_mode_disable(struct csi2_dphy_hw *hw)
887 {
888 write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, 0x01);
889 clk_bulk_disable_unprepare(hw->num_clks, hw->clks_bulk);
890 }
891
rk3568_csi2_dphy_hw_individual_init(struct csi2_dphy_hw * hw)892 static void rk3568_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)
893 {
894 hw->grf_regs = rk3568_grf_dphy_regs;
895 }
896
rk3588_csi2_dphy_hw_individual_init(struct csi2_dphy_hw * hw)897 static void rk3588_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)
898 {
899 hw->grf_regs = rk3588_grf_dphy_regs;
900 }
901
rv1106_csi2_dphy_hw_individual_init(struct csi2_dphy_hw * hw)902 static void rv1106_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)
903 {
904 hw->grf_regs = rv1106_grf_dphy_regs;
905 }
906
rk3562_csi2_dphy_hw_individual_init(struct csi2_dphy_hw * hw)907 static void rk3562_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)
908 {
909 hw->grf_regs = rk3562_grf_dphy_regs;
910 }
911
912 static const struct dphy_hw_drv_data rk3568_csi2_dphy_hw_drv_data = {
913 .hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges,
914 .num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges),
915 .csi2dphy_regs = rk3568_csi2dphy_regs,
916 .grf_regs = rk3568_grf_dphy_regs,
917 .individual_init = rk3568_csi2_dphy_hw_individual_init,
918 .chip_id = CHIP_ID_RK3568,
919 .stream_on = csi2_dphy_hw_stream_on,
920 .stream_off = csi2_dphy_hw_stream_off,
921 };
922
923 static const struct dphy_hw_drv_data rk3588_csi2_dphy_hw_drv_data = {
924 .hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges,
925 .num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges),
926 .csi2dphy_regs = rk3588_csi2dphy_regs,
927 .grf_regs = rk3588_grf_dphy_regs,
928 .individual_init = rk3588_csi2_dphy_hw_individual_init,
929 .chip_id = CHIP_ID_RK3588,
930 .stream_on = csi2_dphy_hw_stream_on,
931 .stream_off = csi2_dphy_hw_stream_off,
932 };
933
934 static const struct dphy_hw_drv_data rv1106_csi2_dphy_hw_drv_data = {
935 .hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges,
936 .num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges),
937 .csi2dphy_regs = rv1106_csi2dphy_regs,
938 .grf_regs = rv1106_grf_dphy_regs,
939 .individual_init = rv1106_csi2_dphy_hw_individual_init,
940 .chip_id = CHIP_ID_RV1106,
941 .stream_on = csi2_dphy_hw_stream_on,
942 .stream_off = csi2_dphy_hw_stream_off,
943 };
944
945 static const struct dphy_hw_drv_data rk3562_csi2_dphy_hw_drv_data = {
946 .hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges,
947 .num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges),
948 .csi2dphy_regs = rk3562_csi2dphy_regs,
949 .grf_regs = rk3562_grf_dphy_regs,
950 .individual_init = rk3562_csi2_dphy_hw_individual_init,
951 .chip_id = CHIP_ID_RK3562,
952 .stream_on = csi2_dphy_hw_stream_on,
953 .stream_off = csi2_dphy_hw_stream_off,
954 };
955
956 static const struct of_device_id rockchip_csi2_dphy_hw_match_id[] = {
957 {
958 .compatible = "rockchip,rk3568-csi2-dphy-hw",
959 .data = &rk3568_csi2_dphy_hw_drv_data,
960 },
961 {
962 .compatible = "rockchip,rk3588-csi2-dphy-hw",
963 .data = &rk3588_csi2_dphy_hw_drv_data,
964 },
965 {
966 .compatible = "rockchip,rv1106-csi2-dphy-hw",
967 .data = &rv1106_csi2_dphy_hw_drv_data,
968 },
969 {
970 .compatible = "rockchip,rk3562-csi2-dphy-hw",
971 .data = &rk3562_csi2_dphy_hw_drv_data,
972 },
973 {}
974 };
975 MODULE_DEVICE_TABLE(of, rockchip_csi2_dphy_hw_match_id);
976
rockchip_csi2_dphy_hw_probe(struct platform_device * pdev)977 static int rockchip_csi2_dphy_hw_probe(struct platform_device *pdev)
978 {
979 struct device *dev = &pdev->dev;
980 struct csi2_dphy_hw *dphy_hw;
981 struct regmap *grf;
982 struct resource *res;
983 const struct of_device_id *of_id;
984 const struct dphy_hw_drv_data *drv_data;
985
986 dphy_hw = devm_kzalloc(dev, sizeof(*dphy_hw), GFP_KERNEL);
987 if (!dphy_hw)
988 return -ENOMEM;
989 dphy_hw->dev = dev;
990
991 of_id = of_match_device(rockchip_csi2_dphy_hw_match_id, dev);
992 if (!of_id)
993 return -EINVAL;
994
995 drv_data = of_id->data;
996
997 grf = syscon_regmap_lookup_by_phandle(dev->of_node,
998 "rockchip,grf");
999 if (IS_ERR(grf)) {
1000 dev_err(dev, "Can't find GRF syscon\n");
1001 return -ENODEV;
1002 }
1003 dphy_hw->regmap_grf = grf;
1004
1005 if (drv_data->chip_id == CHIP_ID_RK3588) {
1006 grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1007 "rockchip,sys_grf");
1008 if (IS_ERR(grf)) {
1009 dev_err(dev, "Can't find SYS GRF syscon\n");
1010 return -ENODEV;
1011 }
1012 dphy_hw->regmap_sys_grf = grf;
1013 }
1014
1015 dphy_hw->num_clks = devm_clk_bulk_get_all(dev, &dphy_hw->clks_bulk);
1016 if (dphy_hw->num_clks < 0)
1017 dev_err(dev, "failed to get csi2 clks\n");
1018
1019 dphy_hw->rsts_bulk = devm_reset_control_array_get_optional_exclusive(dev);
1020 if (IS_ERR(dphy_hw->rsts_bulk))
1021 dev_err_probe(dev, PTR_ERR(dphy_hw->rsts_bulk), "failed to get dphy reset\n");
1022
1023 dphy_hw->dphy_dev_num = 0;
1024 dphy_hw->drv_data = drv_data;
1025 dphy_hw->lane_mode = LANE_MODE_UNDEF;
1026 dphy_hw->grf_regs = drv_data->grf_regs;
1027 dphy_hw->txrx_regs = drv_data->txrx_regs;
1028 dphy_hw->csi2dphy_regs = drv_data->csi2dphy_regs;
1029
1030 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1031 dphy_hw->hw_base_addr = devm_ioremap_resource(dev, res);
1032 if (IS_ERR(dphy_hw->hw_base_addr)) {
1033 resource_size_t offset = res->start;
1034 resource_size_t size = resource_size(res);
1035
1036 dphy_hw->hw_base_addr = devm_ioremap(dev, offset, size);
1037 if (IS_ERR(dphy_hw->hw_base_addr)) {
1038 dev_err(dev, "Can't find csi2 dphy hw addr!\n");
1039 return -ENODEV;
1040 }
1041 }
1042 dphy_hw->stream_on = drv_data->stream_on;
1043 dphy_hw->stream_off = drv_data->stream_off;
1044
1045 if (drv_data->chip_id == CHIP_ID_RV1106) {
1046 dphy_hw->ttl_mode_enable = csi2_dphy_hw_ttl_mode_enable;
1047 dphy_hw->ttl_mode_disable = csi2_dphy_hw_ttl_mode_disable;
1048 } else {
1049 dphy_hw->ttl_mode_enable = NULL;
1050 dphy_hw->ttl_mode_disable = NULL;
1051 }
1052
1053 atomic_set(&dphy_hw->stream_cnt, 0);
1054
1055 mutex_init(&dphy_hw->mutex);
1056
1057 platform_set_drvdata(pdev, dphy_hw);
1058
1059 pm_runtime_enable(&pdev->dev);
1060
1061 dev_info(dev, "csi2 dphy hw probe successfully!\n");
1062
1063 return 0;
1064 }
1065
rockchip_csi2_dphy_hw_remove(struct platform_device * pdev)1066 static int rockchip_csi2_dphy_hw_remove(struct platform_device *pdev)
1067 {
1068 struct csi2_dphy_hw *hw = platform_get_drvdata(pdev);
1069
1070 pm_runtime_disable(&pdev->dev);
1071 mutex_destroy(&hw->mutex);
1072
1073 return 0;
1074 }
1075
1076 static struct platform_driver rockchip_csi2_dphy_hw_driver = {
1077 .probe = rockchip_csi2_dphy_hw_probe,
1078 .remove = rockchip_csi2_dphy_hw_remove,
1079 .driver = {
1080 .name = "rockchip-csi2-dphy-hw",
1081 .of_match_table = rockchip_csi2_dphy_hw_match_id,
1082 },
1083 };
1084
rockchip_csi2_dphy_hw_init(void)1085 int rockchip_csi2_dphy_hw_init(void)
1086 {
1087 return platform_driver_register(&rockchip_csi2_dphy_hw_driver);
1088 }
1089
1090 #if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
1091 subsys_initcall(rockchip_csi2_dphy_hw_init);
1092 #else
1093 #if !defined(CONFIG_VIDEO_REVERSE_IMAGE)
1094 module_platform_driver(rockchip_csi2_dphy_hw_driver);
1095 #endif
1096 #endif
1097
1098 MODULE_AUTHOR("Rockchip Camera/ISP team");
1099 MODULE_DESCRIPTION("Rockchip MIPI CSI2 DPHY HW driver");
1100 MODULE_LICENSE("GPL v2");
1101