1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Rockchip eFuse Driver
4 *
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Caesar Wang <wxt@rock-chips.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/io.h>
14 #include <linux/module.h>
15 #include <linux/nvmem-provider.h>
16 #include <linux/slab.h>
17 #include <linux/of.h>
18 #include <linux/of_platform.h>
19 #include <linux/platform_device.h>
20 #include <linux/rockchip/rockchip_sip.h>
21
22 #define T_CSB_P_S 0
23 #define T_PGENB_P_S 0
24 #define T_LOAD_P_S 0
25 #define T_ADDR_P_S 0
26 #define T_STROBE_P_S (0 + 110) /* 1.1us */
27 #define T_CSB_P_L (0 + 110 + 1000 + 20) /* 200ns */
28 #define T_PGENB_P_L (0 + 110 + 1000 + 20)
29 #define T_LOAD_P_L (0 + 110 + 1000 + 20)
30 #define T_ADDR_P_L (0 + 110 + 1000 + 20)
31 #define T_STROBE_P_L (0 + 110 + 1000) /* 10us */
32 #define T_CSB_R_S 0
33 #define T_PGENB_R_S 0
34 #define T_LOAD_R_S 0
35 #define T_ADDR_R_S 2
36 #define T_STROBE_R_S (2 + 3)
37 #define T_CSB_R_L (2 + 3 + 3 + 3)
38 #define T_PGENB_R_L (2 + 3 + 3 + 3)
39 #define T_LOAD_R_L (2 + 3 + 3 + 3)
40 #define T_ADDR_R_L (2 + 3 + 3 + 2)
41 #define T_STROBE_R_L (2 + 3 + 3)
42
43 #define T_CSB_P 0x28
44 #define T_PGENB_P 0x2c
45 #define T_LOAD_P 0x30
46 #define T_ADDR_P 0x34
47 #define T_STROBE_P 0x38
48 #define T_CSB_R 0x3c
49 #define T_PGENB_R 0x40
50 #define T_LOAD_R 0x44
51 #define T_ADDR_R 0x48
52 #define T_STROBE_R 0x4c
53
54 #define RK1808_MOD 0x00
55 #define RK1808_INT_STATUS RK3328_INT_STATUS
56 #define RK1808_DOUT RK3328_DOUT
57 #define RK1808_AUTO_CTRL RK3328_AUTO_CTRL
58 #define RK1808_USER_MODE BIT(0)
59 #define RK1808_INT_FINISH RK3328_INT_FINISH
60 #define RK1808_AUTO_ENB RK3328_AUTO_ENB
61 #define RK1808_AUTO_RD RK3328_AUTO_RD
62 #define RK1808_A_SHIFT RK3399_A_SHIFT
63 #define RK1808_A_MASK RK3399_A_MASK
64 #define RK1808_NBYTES RK3399_NBYTES
65
66 #define RK3128_A_SHIFT 7
67 #define RK3288_A_SHIFT 6
68 #define RK3288_A_MASK 0x3ff
69 #define RK3288_PGENB BIT(3)
70 #define RK3288_LOAD BIT(2)
71 #define RK3288_STROBE BIT(1)
72 #define RK3288_CSB BIT(0)
73
74 #define RK3328_SECURE_SIZES 96
75 #define RK3328_INT_STATUS 0x0018
76 #define RK3328_DOUT 0x0020
77 #define RK3328_AUTO_CTRL 0x0024
78 #define RK3328_INT_FINISH BIT(0)
79 #define RK3328_AUTO_ENB BIT(0)
80 #define RK3328_AUTO_RD BIT(1)
81
82 #define RK3399_A_SHIFT 16
83 #define RK3399_A_MASK 0x3ff
84 #define RK3399_NBYTES 4
85 #define RK3399_STROBSFTSEL BIT(9)
86 #define RK3399_RSB BIT(7)
87 #define RK3399_PD BIT(5)
88 #define RK3399_PGENB BIT(3)
89 #define RK3399_LOAD BIT(2)
90 #define RK3399_STROBE BIT(1)
91 #define RK3399_CSB BIT(0)
92
93 #define REG_EFUSE_CTRL 0x0000
94 #define REG_EFUSE_DOUT 0x0004
95
96 struct rockchip_efuse_chip {
97 struct device *dev;
98 void __iomem *base;
99 struct clk_bulk_data *clks;
100 int num_clks;
101 phys_addr_t phys;
102 struct mutex mutex;
103 };
104
rk1808_efuse_timing_init(void __iomem * base)105 static void rk1808_efuse_timing_init(void __iomem *base)
106 {
107 /* enable auto mode */
108 writel(readl(base + RK1808_MOD) & (~RK1808_USER_MODE),
109 base + RK1808_MOD);
110
111 /* setup efuse timing */
112 writel((T_CSB_P_S << 16) | T_CSB_P_L, base + T_CSB_P);
113 writel((T_PGENB_P_S << 16) | T_PGENB_P_L, base + T_PGENB_P);
114 writel((T_LOAD_P_S << 16) | T_LOAD_P_L, base + T_LOAD_P);
115 writel((T_ADDR_P_S << 16) | T_ADDR_P_L, base + T_ADDR_P);
116 writel((T_STROBE_P_S << 16) | T_STROBE_P_L, base + T_STROBE_P);
117 writel((T_CSB_R_S << 16) | T_CSB_R_L, base + T_CSB_R);
118 writel((T_PGENB_R_S << 16) | T_PGENB_R_L, base + T_PGENB_R);
119 writel((T_LOAD_R_S << 16) | T_LOAD_R_L, base + T_LOAD_R);
120 writel((T_ADDR_R_S << 16) | T_ADDR_R_L, base + T_ADDR_R);
121 writel((T_STROBE_R_S << 16) | T_STROBE_R_L, base + T_STROBE_R);
122 }
123
rk1808_efuse_timing_deinit(void __iomem * base)124 static void rk1808_efuse_timing_deinit(void __iomem *base)
125 {
126 /* disable auto mode */
127 writel(readl(base + RK1808_MOD) | RK1808_USER_MODE,
128 base + RK1808_MOD);
129
130 /* clear efuse timing */
131 writel(0, base + T_CSB_P);
132 writel(0, base + T_PGENB_P);
133 writel(0, base + T_LOAD_P);
134 writel(0, base + T_ADDR_P);
135 writel(0, base + T_STROBE_P);
136 writel(0, base + T_CSB_R);
137 writel(0, base + T_PGENB_R);
138 writel(0, base + T_LOAD_R);
139 writel(0, base + T_ADDR_R);
140 writel(0, base + T_STROBE_R);
141 }
142
rockchip_rk1808_efuse_read(void * context,unsigned int offset,void * val,size_t bytes)143 static int rockchip_rk1808_efuse_read(void *context, unsigned int offset,
144 void *val, size_t bytes)
145 {
146 struct rockchip_efuse_chip *efuse = context;
147 unsigned int addr_start, addr_end, addr_offset, addr_len;
148 u32 out_value, status;
149 u8 *buf;
150 int ret, i = 0;
151
152 mutex_lock(&efuse->mutex);
153
154 ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks);
155 if (ret < 0) {
156 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
157 goto out;
158 }
159
160 addr_start = rounddown(offset, RK1808_NBYTES) / RK1808_NBYTES;
161 addr_end = roundup(offset + bytes, RK1808_NBYTES) / RK1808_NBYTES;
162 addr_offset = offset % RK1808_NBYTES;
163 addr_len = addr_end - addr_start;
164
165 buf = kzalloc(sizeof(*buf) * addr_len * RK1808_NBYTES, GFP_KERNEL);
166 if (!buf) {
167 ret = -ENOMEM;
168 goto nomem;
169 }
170
171 rk1808_efuse_timing_init(efuse->base);
172
173 while (addr_len--) {
174 writel(RK1808_AUTO_RD | RK1808_AUTO_ENB |
175 ((addr_start++ & RK1808_A_MASK) << RK1808_A_SHIFT),
176 efuse->base + RK1808_AUTO_CTRL);
177 udelay(2);
178 status = readl(efuse->base + RK1808_INT_STATUS);
179 if (!(status & RK1808_INT_FINISH)) {
180 ret = -EIO;
181 goto err;
182 }
183 out_value = readl(efuse->base + RK1808_DOUT);
184 writel(RK1808_INT_FINISH, efuse->base + RK1808_INT_STATUS);
185
186 memcpy(&buf[i], &out_value, RK1808_NBYTES);
187 i += RK1808_NBYTES;
188 }
189 memcpy(val, buf + addr_offset, bytes);
190 err:
191 rk1808_efuse_timing_deinit(efuse->base);
192 kfree(buf);
193 nomem:
194 rk1808_efuse_timing_deinit(efuse->base);
195 clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks);
196 out:
197 mutex_unlock(&efuse->mutex);
198
199 return ret;
200 }
201
rockchip_rk3128_efuse_read(void * context,unsigned int offset,void * val,size_t bytes)202 static int rockchip_rk3128_efuse_read(void *context, unsigned int offset,
203 void *val, size_t bytes)
204 {
205 struct rockchip_efuse_chip *efuse = context;
206 u8 *buf = val;
207 int ret;
208
209 ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks);
210 if (ret < 0) {
211 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
212 return ret;
213 }
214
215 writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL);
216 udelay(1);
217 while (bytes--) {
218 writel(readl(efuse->base + REG_EFUSE_CTRL) &
219 (~(RK3288_A_MASK << RK3128_A_SHIFT)),
220 efuse->base + REG_EFUSE_CTRL);
221 writel(readl(efuse->base + REG_EFUSE_CTRL) |
222 ((offset++ & RK3288_A_MASK) << RK3128_A_SHIFT),
223 efuse->base + REG_EFUSE_CTRL);
224 udelay(1);
225 writel(readl(efuse->base + REG_EFUSE_CTRL) |
226 RK3288_STROBE, efuse->base + REG_EFUSE_CTRL);
227 udelay(1);
228 *buf++ = readb(efuse->base + REG_EFUSE_DOUT);
229 writel(readl(efuse->base + REG_EFUSE_CTRL) &
230 (~RK3288_STROBE), efuse->base + REG_EFUSE_CTRL);
231 udelay(1);
232 }
233
234 /* Switch to standby mode */
235 writel(RK3288_PGENB | RK3288_CSB, efuse->base + REG_EFUSE_CTRL);
236
237 clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks);
238
239 return 0;
240 }
241
rockchip_rk3288_efuse_read(void * context,unsigned int offset,void * val,size_t bytes)242 static int rockchip_rk3288_efuse_read(void *context, unsigned int offset,
243 void *val, size_t bytes)
244 {
245 struct rockchip_efuse_chip *efuse = context;
246 u8 *buf = val;
247 int ret;
248
249 ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks);
250 if (ret < 0) {
251 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
252 return ret;
253 }
254
255 writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL);
256 udelay(1);
257 while (bytes--) {
258 writel(readl(efuse->base + REG_EFUSE_CTRL) &
259 (~(RK3288_A_MASK << RK3288_A_SHIFT)),
260 efuse->base + REG_EFUSE_CTRL);
261 writel(readl(efuse->base + REG_EFUSE_CTRL) |
262 ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT),
263 efuse->base + REG_EFUSE_CTRL);
264 udelay(1);
265 writel(readl(efuse->base + REG_EFUSE_CTRL) |
266 RK3288_STROBE, efuse->base + REG_EFUSE_CTRL);
267 udelay(1);
268 *buf++ = readb(efuse->base + REG_EFUSE_DOUT);
269 writel(readl(efuse->base + REG_EFUSE_CTRL) &
270 (~RK3288_STROBE), efuse->base + REG_EFUSE_CTRL);
271 udelay(1);
272 }
273
274 /* Switch to standby mode */
275 writel(RK3288_PGENB | RK3288_CSB, efuse->base + REG_EFUSE_CTRL);
276
277 clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks);
278
279 return 0;
280 }
281
rockchip_rk3288_efuse_secure_read(void * context,unsigned int offset,void * val,size_t bytes)282 static int rockchip_rk3288_efuse_secure_read(void *context,
283 unsigned int offset,
284 void *val, size_t bytes)
285 {
286 struct rockchip_efuse_chip *efuse = context;
287 u8 *buf = val;
288 u32 wr_val;
289 int ret;
290
291 ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks);
292 if (ret < 0) {
293 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
294 return ret;
295 }
296
297 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL,
298 RK3288_LOAD | RK3288_PGENB);
299 udelay(1);
300 while (bytes--) {
301 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) &
302 (~(RK3288_A_MASK << RK3288_A_SHIFT));
303 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
304 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) |
305 ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT);
306 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
307 udelay(1);
308 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) |
309 RK3288_STROBE;
310 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
311 udelay(1);
312 *buf++ = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_DOUT);
313 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) &
314 (~RK3288_STROBE);
315 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
316 udelay(1);
317 }
318
319 /* Switch to standby mode */
320 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL,
321 RK3288_PGENB | RK3288_CSB);
322
323 clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks);
324
325 return 0;
326 }
327
rockchip_rk3328_efuse_read(void * context,unsigned int offset,void * val,size_t bytes)328 static int rockchip_rk3328_efuse_read(void *context, unsigned int offset,
329 void *val, size_t bytes)
330 {
331 struct rockchip_efuse_chip *efuse = context;
332 unsigned int addr_start, addr_end, addr_offset, addr_len;
333 u32 out_value, status;
334 u8 *buf;
335 int ret, i = 0;
336
337 ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks);
338 if (ret < 0) {
339 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
340 return ret;
341 }
342
343 /* 128 Byte efuse, 96 Byte for secure, 32 Byte for non-secure */
344 offset += RK3328_SECURE_SIZES;
345 addr_start = rounddown(offset, RK3399_NBYTES) / RK3399_NBYTES;
346 addr_end = roundup(offset + bytes, RK3399_NBYTES) / RK3399_NBYTES;
347 addr_offset = offset % RK3399_NBYTES;
348 addr_len = addr_end - addr_start;
349
350 buf = kzalloc(array3_size(addr_len, RK3399_NBYTES, sizeof(*buf)),
351 GFP_KERNEL);
352 if (!buf) {
353 ret = -ENOMEM;
354 goto nomem;
355 }
356
357 while (addr_len--) {
358 writel(RK3328_AUTO_RD | RK3328_AUTO_ENB |
359 ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
360 efuse->base + RK3328_AUTO_CTRL);
361 udelay(4);
362 status = readl(efuse->base + RK3328_INT_STATUS);
363 if (!(status & RK3328_INT_FINISH)) {
364 ret = -EIO;
365 goto err;
366 }
367 out_value = readl(efuse->base + RK3328_DOUT);
368 writel(RK3328_INT_FINISH, efuse->base + RK3328_INT_STATUS);
369
370 memcpy(&buf[i], &out_value, RK3399_NBYTES);
371 i += RK3399_NBYTES;
372 }
373
374 memcpy(val, buf + addr_offset, bytes);
375 err:
376 kfree(buf);
377 nomem:
378 clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks);
379
380 return ret;
381 }
382
rockchip_rk3368_efuse_read(void * context,unsigned int offset,void * val,size_t bytes)383 static int rockchip_rk3368_efuse_read(void *context, unsigned int offset,
384 void *val, size_t bytes)
385 {
386 struct rockchip_efuse_chip *efuse = context;
387 u8 *buf = val;
388 u32 wr_val;
389 int ret;
390
391 ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks);
392 if (ret < 0) {
393 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
394 return ret;
395 }
396
397 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL,
398 RK3288_LOAD | RK3288_PGENB);
399 udelay(1);
400 while (bytes--) {
401 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) &
402 (~(RK3288_A_MASK << RK3288_A_SHIFT));
403 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
404 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) |
405 ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT);
406 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
407 udelay(1);
408 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) |
409 RK3288_STROBE;
410 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
411 udelay(1);
412 *buf++ = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_DOUT);
413 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) &
414 (~RK3288_STROBE);
415 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
416 udelay(1);
417 }
418
419 /* Switch to standby mode */
420 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL,
421 RK3288_PGENB | RK3288_CSB);
422
423 clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks);
424
425 return 0;
426 }
427
rockchip_rk3399_efuse_read(void * context,unsigned int offset,void * val,size_t bytes)428 static int rockchip_rk3399_efuse_read(void *context, unsigned int offset,
429 void *val, size_t bytes)
430 {
431 struct rockchip_efuse_chip *efuse = context;
432 unsigned int addr_start, addr_end, addr_offset, addr_len;
433 u32 out_value;
434 u8 *buf;
435 int ret, i = 0;
436
437 ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks);
438 if (ret < 0) {
439 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
440 return ret;
441 }
442
443 addr_start = rounddown(offset, RK3399_NBYTES) / RK3399_NBYTES;
444 addr_end = roundup(offset + bytes, RK3399_NBYTES) / RK3399_NBYTES;
445 addr_offset = offset % RK3399_NBYTES;
446 addr_len = addr_end - addr_start;
447
448 buf = kzalloc(array3_size(addr_len, RK3399_NBYTES, sizeof(*buf)),
449 GFP_KERNEL);
450 if (!buf) {
451 ret = -ENOMEM;
452 goto disable_clks;
453 }
454
455 writel(RK3399_LOAD | RK3399_PGENB | RK3399_STROBSFTSEL | RK3399_RSB,
456 efuse->base + REG_EFUSE_CTRL);
457 udelay(1);
458 while (addr_len--) {
459 writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3399_STROBE |
460 ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
461 efuse->base + REG_EFUSE_CTRL);
462 udelay(1);
463 out_value = readl(efuse->base + REG_EFUSE_DOUT);
464 writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3399_STROBE),
465 efuse->base + REG_EFUSE_CTRL);
466 udelay(1);
467
468 memcpy(&buf[i], &out_value, RK3399_NBYTES);
469 i += RK3399_NBYTES;
470 }
471
472 /* Switch to standby mode */
473 writel(RK3399_PD | RK3399_CSB, efuse->base + REG_EFUSE_CTRL);
474
475 memcpy(val, buf + addr_offset, bytes);
476
477 kfree(buf);
478
479 disable_clks:
480 clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks);
481
482 return ret;
483 }
484
485 static struct nvmem_config econfig = {
486 .name = "rockchip-efuse",
487 .stride = 1,
488 .word_size = 1,
489 .read_only = true,
490 };
491
492 static const struct of_device_id rockchip_efuse_match[] = {
493 /* deprecated but kept around for dts binding compatibility */
494 {
495 .compatible = "rockchip,rk1808-efuse",
496 .data = (void *)&rockchip_rk1808_efuse_read,
497 },
498 {
499 .compatible = "rockchip,rockchip-efuse",
500 .data = (void *)&rockchip_rk3288_efuse_read,
501 },
502 {
503 .compatible = "rockchip,rk3066a-efuse",
504 .data = (void *)&rockchip_rk3288_efuse_read,
505 },
506 {
507 .compatible = "rockchip,rk3128-efuse",
508 .data = (void *)&rockchip_rk3128_efuse_read,
509 },
510 {
511 .compatible = "rockchip,rk3188-efuse",
512 .data = (void *)&rockchip_rk3288_efuse_read,
513 },
514 {
515 .compatible = "rockchip,rk3228-efuse",
516 .data = (void *)&rockchip_rk3288_efuse_read,
517 },
518 {
519 .compatible = "rockchip,rk3288-efuse",
520 .data = (void *)&rockchip_rk3288_efuse_read,
521 },
522 {
523 .compatible = "rockchip,rk3288-secure-efuse",
524 .data = (void *)&rockchip_rk3288_efuse_secure_read,
525 },
526 {
527 .compatible = "rockchip,rk3328-efuse",
528 .data = (void *)&rockchip_rk3328_efuse_read,
529 },
530 {
531 .compatible = "rockchip,rk3368-efuse",
532 .data = (void *)&rockchip_rk3368_efuse_read,
533 },
534 {
535 .compatible = "rockchip,rk3399-efuse",
536 .data = (void *)&rockchip_rk3399_efuse_read,
537 },
538 { /* sentinel */},
539 };
540 MODULE_DEVICE_TABLE(of, rockchip_efuse_match);
541
rockchip_efuse_probe(struct platform_device * pdev)542 static int rockchip_efuse_probe(struct platform_device *pdev)
543 {
544 struct resource *res;
545 struct nvmem_device *nvmem;
546 struct rockchip_efuse_chip *efuse;
547 const void *data;
548 struct device *dev = &pdev->dev;
549
550 data = of_device_get_match_data(dev);
551 if (!data) {
552 dev_err(dev, "failed to get match data\n");
553 return -EINVAL;
554 }
555
556 efuse = devm_kzalloc(dev, sizeof(struct rockchip_efuse_chip),
557 GFP_KERNEL);
558 if (!efuse)
559 return -ENOMEM;
560
561 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
562 efuse->phys = res->start;
563 efuse->base = devm_ioremap_resource(dev, res);
564 if (IS_ERR(efuse->base))
565 return PTR_ERR(efuse->base);
566
567 efuse->num_clks = devm_clk_bulk_get_all(dev, &efuse->clks);
568 if (efuse->num_clks < 1)
569 return -ENODEV;
570
571 mutex_init(&efuse->mutex);
572
573 efuse->dev = dev;
574 if (of_property_read_u32(dev->of_node, "rockchip,efuse-size",
575 &econfig.size))
576 econfig.size = resource_size(res);
577 econfig.reg_read = data;
578 econfig.priv = efuse;
579 econfig.dev = efuse->dev;
580 nvmem = devm_nvmem_register(dev, &econfig);
581
582 return PTR_ERR_OR_ZERO(nvmem);
583 }
584
585 static struct platform_driver rockchip_efuse_driver = {
586 .probe = rockchip_efuse_probe,
587 .driver = {
588 .name = "rockchip-efuse",
589 .of_match_table = rockchip_efuse_match,
590 },
591 };
592
rockchip_efuse_init(void)593 static int __init rockchip_efuse_init(void)
594 {
595 int ret;
596
597 ret = platform_driver_register(&rockchip_efuse_driver);
598 if (ret) {
599 pr_err("failed to register efuse driver\n");
600 return ret;
601 }
602
603 return 0;
604 }
605
rockchip_efuse_exit(void)606 static void __exit rockchip_efuse_exit(void)
607 {
608 return platform_driver_unregister(&rockchip_efuse_driver);
609 }
610
611 subsys_initcall(rockchip_efuse_init);
612 module_exit(rockchip_efuse_exit);
613
614 MODULE_DESCRIPTION("rockchip_efuse driver");
615 MODULE_LICENSE("GPL v2");
616