xref: /OK3568_Linux_fs/kernel/drivers/nvmem/rk628-efuse.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * RK628 eFuse Driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author: Weixin Zhou <zwx@rock-chips.com>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/clk.h>
11*4882a593Smuzhiyun #include <linux/clk-provider.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/device.h>
14*4882a593Smuzhiyun #include <linux/io.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/nvmem-provider.h>
17*4882a593Smuzhiyun #include <linux/slab.h>
18*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
19*4882a593Smuzhiyun #include <linux/of.h>
20*4882a593Smuzhiyun #include <linux/of_platform.h>
21*4882a593Smuzhiyun #include <linux/platform_device.h>
22*4882a593Smuzhiyun #include <linux/regmap.h>
23*4882a593Smuzhiyun #include <linux/mfd/rk628.h>
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #define EFUSE_SIZE		64
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define T_CSB_P_S		0
28*4882a593Smuzhiyun #define T_PGENB_P_S		(15 + 200)
29*4882a593Smuzhiyun #define T_LOAD_P_S		0
30*4882a593Smuzhiyun #define T_ADDR_P_S		(15 + 200 + 5)
31*4882a593Smuzhiyun #define T_STROBE_P_S		((150 + 2000 + 100) / 9)
32*4882a593Smuzhiyun #define T_CSB_P_L		0
33*4882a593Smuzhiyun #define T_PGENB_P_L		(15 + 200 + 10 + 200 + 190 + 10)
34*4882a593Smuzhiyun #define T_LOAD_P_L		(15 + 200 + 200 + 190 + 10 + 100 + 15)
35*4882a593Smuzhiyun #define T_ADDR_P_L		(15 + 200 + 5 + 200 + 5)
36*4882a593Smuzhiyun #define T_STROBE_P_L		((150 + 2000 + 100 + 2000) / 9)
37*4882a593Smuzhiyun #define T_CSB_R_S		0
38*4882a593Smuzhiyun #define T_PGENB_R_S		0
39*4882a593Smuzhiyun #define T_LOAD_R_S		15
40*4882a593Smuzhiyun #define T_ADDR_R_S		(15 + 9)
41*4882a593Smuzhiyun #define T_STROBE_R_S		((150 + 100) / 9)
42*4882a593Smuzhiyun #define T_CSB_R_L		0
43*4882a593Smuzhiyun #define T_PGENB_R_L		0
44*4882a593Smuzhiyun #define T_LOAD_R_L		(15 + 5 + 5 + 10 + 15)
45*4882a593Smuzhiyun #define T_ADDR_R_L		(15 + 10 + 5 + 1)
46*4882a593Smuzhiyun #define T_STROBE_R_L		((150 + 100 + 50) / 8)
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #define T_CSB_P			0x28
49*4882a593Smuzhiyun #define T_PGENB_P		0x2c
50*4882a593Smuzhiyun #define T_LOAD_P		0x30
51*4882a593Smuzhiyun #define T_ADDR_P		0x34
52*4882a593Smuzhiyun #define T_STROBE_P		0x38
53*4882a593Smuzhiyun #define T_CSB_R			0x3c
54*4882a593Smuzhiyun #define T_PGENB_R		0x40
55*4882a593Smuzhiyun #define T_LOAD_R		0x44
56*4882a593Smuzhiyun #define T_ADDR_R		0x48
57*4882a593Smuzhiyun #define T_STROBE_R		0x4c
58*4882a593Smuzhiyun #define EFUSE_REVISION		0x50
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun #define RK628_EFUSE_BASE	0xb0000
61*4882a593Smuzhiyun #define RK628_MOD		0x00
62*4882a593Smuzhiyun #define RK628_INT_STATUS	0x0018
63*4882a593Smuzhiyun #define RK628_DOUT		0x0020
64*4882a593Smuzhiyun #define RK628_AUTO_CTRL		0x0024
65*4882a593Smuzhiyun #define RK628_USER_MODE		BIT(0)
66*4882a593Smuzhiyun #define RK628_INT_FINISH	BIT(0)
67*4882a593Smuzhiyun #define RK628_AUTO_ENB		BIT(0)
68*4882a593Smuzhiyun #define RK628_AUTO_RD		BIT(1)
69*4882a593Smuzhiyun #define RK628_ADDR_ROW		16
70*4882a593Smuzhiyun #define RK628_ADDR_COL		22
71*4882a593Smuzhiyun #define RK628_A_SHIFT		16
72*4882a593Smuzhiyun #define RK628_A_MASK		0x3ff
73*4882a593Smuzhiyun #define RK628_NBYTES		1
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun #define REG_EFUSE_CTRL		0x0000
76*4882a593Smuzhiyun #define REG_EFUSE_DOUT		0x0004
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun struct rk628_efuse_chip {
79*4882a593Smuzhiyun 	struct device *dev;
80*4882a593Smuzhiyun 	u32 base;
81*4882a593Smuzhiyun 	struct clk *clk;
82*4882a593Smuzhiyun 	struct regmap *regmap;
83*4882a593Smuzhiyun 	struct gpio_desc *avdd_gpio;
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun 
rk628_read(struct regmap * regmap,u32 reg)86*4882a593Smuzhiyun static int rk628_read(struct regmap *regmap, u32 reg)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun 	int ret;
89*4882a593Smuzhiyun 	u32 val;
90*4882a593Smuzhiyun 	struct rk628_efuse_chip *efuse = container_of(regmap, struct rk628_efuse_chip, regmap);
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	ret = regmap_read(regmap, reg, &val);
93*4882a593Smuzhiyun 	if (ret) {
94*4882a593Smuzhiyun 		dev_err(efuse->dev, "rk628-efuse:failed to read reg 0x%x\n", reg);
95*4882a593Smuzhiyun 		return ret;
96*4882a593Smuzhiyun 	}
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	return val;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun 
rk628_write(struct regmap * regmap,u32 val,u32 reg)101*4882a593Smuzhiyun static int rk628_write(struct regmap *regmap, u32 val, u32 reg)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun 	int ret;
104*4882a593Smuzhiyun 	struct rk628_efuse_chip *efuse = container_of(regmap, struct rk628_efuse_chip, regmap);
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	ret = regmap_write(regmap, reg, val);
107*4882a593Smuzhiyun 	if (ret)
108*4882a593Smuzhiyun 		dev_err(efuse->dev, "rk628-efuse:failed to write reg 0x%x\n", reg);
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	return ret;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun 
rk628_efuse_timing_init(struct rk628_efuse_chip * efuse)113*4882a593Smuzhiyun static void rk628_efuse_timing_init(struct rk628_efuse_chip *efuse)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun 	u32 base = efuse->base;
116*4882a593Smuzhiyun 	/* enable auto mode */
117*4882a593Smuzhiyun 	rk628_write(efuse->regmap,
118*4882a593Smuzhiyun 		    rk628_read(efuse->regmap, base + RK628_MOD) & (~RK628_USER_MODE),
119*4882a593Smuzhiyun 		    base + RK628_MOD);
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	/* setup efuse timing */
122*4882a593Smuzhiyun 	rk628_write(efuse->regmap, (T_CSB_P_S << 16) | T_CSB_P_L, base + T_CSB_P);
123*4882a593Smuzhiyun 	rk628_write(efuse->regmap, (T_PGENB_P_S << 16) | T_PGENB_P_L, base + T_PGENB_P);
124*4882a593Smuzhiyun 	rk628_write(efuse->regmap, (T_LOAD_P_S << 16) | T_LOAD_P_L, base + T_LOAD_P);
125*4882a593Smuzhiyun 	rk628_write(efuse->regmap, (T_ADDR_P_S << 16) | T_ADDR_P_L, base + T_ADDR_P);
126*4882a593Smuzhiyun 	rk628_write(efuse->regmap, (T_STROBE_P_S << 16) | T_STROBE_P_L, base + T_STROBE_P);
127*4882a593Smuzhiyun 	rk628_write(efuse->regmap, (T_CSB_R_S << 16) | T_CSB_R_L, base + T_CSB_R);
128*4882a593Smuzhiyun 	rk628_write(efuse->regmap, (T_PGENB_R_S << 16) | T_PGENB_R_L, base + T_PGENB_R);
129*4882a593Smuzhiyun 	rk628_write(efuse->regmap, (T_LOAD_R_S << 16) | T_LOAD_R_L, base + T_LOAD_R);
130*4882a593Smuzhiyun 	rk628_write(efuse->regmap, (T_ADDR_R_S << 16) | T_ADDR_R_L, base + T_ADDR_R);
131*4882a593Smuzhiyun 	rk628_write(efuse->regmap, (T_STROBE_R_S << 16) | T_STROBE_R_L, base + T_STROBE_R);
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun 
rk628_efuse_timing_deinit(struct rk628_efuse_chip * efuse)134*4882a593Smuzhiyun static void rk628_efuse_timing_deinit(struct rk628_efuse_chip *efuse)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun 	u32 base = efuse->base;
137*4882a593Smuzhiyun 	/* disable auto mode */
138*4882a593Smuzhiyun 	rk628_write(efuse->regmap,
139*4882a593Smuzhiyun 		    rk628_read(efuse->regmap, base + RK628_MOD) | RK628_USER_MODE, base + RK628_MOD);
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	/* clear efuse timing */
142*4882a593Smuzhiyun 	rk628_write(efuse->regmap, 0, base + T_CSB_P);
143*4882a593Smuzhiyun 	rk628_write(efuse->regmap, 0, base + T_PGENB_P);
144*4882a593Smuzhiyun 	rk628_write(efuse->regmap, 0, base + T_LOAD_P);
145*4882a593Smuzhiyun 	rk628_write(efuse->regmap, 0, base + T_ADDR_P);
146*4882a593Smuzhiyun 	rk628_write(efuse->regmap, 0, base + T_STROBE_P);
147*4882a593Smuzhiyun 	rk628_write(efuse->regmap, 0, base + T_CSB_R);
148*4882a593Smuzhiyun 	rk628_write(efuse->regmap, 0, base + T_PGENB_R);
149*4882a593Smuzhiyun 	rk628_write(efuse->regmap, 0, base + T_LOAD_R);
150*4882a593Smuzhiyun 	rk628_write(efuse->regmap, 0, base + T_ADDR_R);
151*4882a593Smuzhiyun 	rk628_write(efuse->regmap, 0, base + T_STROBE_R);
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun 
rk628_efuse_read(void * context,unsigned int offset,void * val,size_t bytes)154*4882a593Smuzhiyun static int rk628_efuse_read(void *context, unsigned int offset,
155*4882a593Smuzhiyun 				      void *val, size_t bytes)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun 	struct rk628_efuse_chip *efuse = context;
158*4882a593Smuzhiyun 	unsigned int addr_start, addr_end, addr_offset, addr_len;
159*4882a593Smuzhiyun 	u32 out_value, status;
160*4882a593Smuzhiyun 	u8 *buf;
161*4882a593Smuzhiyun 	int ret, i = 0;
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	ret = clk_prepare_enable(efuse->clk);
164*4882a593Smuzhiyun 	if (ret < 0) {
165*4882a593Smuzhiyun 		dev_err(efuse->dev, "failed to prepare/enable efuse pclk\n");
166*4882a593Smuzhiyun 		return ret;
167*4882a593Smuzhiyun 	}
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	addr_start = rounddown(offset, RK628_NBYTES) / RK628_NBYTES;
170*4882a593Smuzhiyun 	addr_end = roundup(offset + bytes, RK628_NBYTES) / RK628_NBYTES;
171*4882a593Smuzhiyun 	addr_offset = offset % RK628_NBYTES;
172*4882a593Smuzhiyun 	addr_len = addr_end - addr_start;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	buf = kzalloc(sizeof(*buf) * addr_len * RK628_NBYTES, GFP_KERNEL);
175*4882a593Smuzhiyun 	if (!buf) {
176*4882a593Smuzhiyun 		ret = -ENOMEM;
177*4882a593Smuzhiyun 		goto nomem;
178*4882a593Smuzhiyun 	}
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	rk628_efuse_timing_init(efuse);
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	while (addr_len--) {
183*4882a593Smuzhiyun 		rk628_write(efuse->regmap, RK628_AUTO_RD | RK628_AUTO_ENB |
184*4882a593Smuzhiyun 		       ((addr_start++ & RK628_A_MASK) << RK628_A_SHIFT),
185*4882a593Smuzhiyun 		       efuse->base + RK628_AUTO_CTRL);
186*4882a593Smuzhiyun 		udelay(2);
187*4882a593Smuzhiyun 		status = rk628_read(efuse->regmap, efuse->base + RK628_INT_STATUS);
188*4882a593Smuzhiyun 		if (!(status & RK628_INT_FINISH)) {
189*4882a593Smuzhiyun 			ret = -EIO;
190*4882a593Smuzhiyun 			goto err;
191*4882a593Smuzhiyun 		}
192*4882a593Smuzhiyun 		out_value = rk628_read(efuse->regmap, efuse->base + RK628_DOUT);
193*4882a593Smuzhiyun 		rk628_write(efuse->regmap, RK628_INT_FINISH, efuse->base + RK628_INT_STATUS);
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 		memcpy(&buf[i], &out_value, RK628_NBYTES);
196*4882a593Smuzhiyun 		i += RK628_NBYTES;
197*4882a593Smuzhiyun 	}
198*4882a593Smuzhiyun 	memcpy(val, buf + addr_offset, bytes);
199*4882a593Smuzhiyun err:
200*4882a593Smuzhiyun 	rk628_efuse_timing_deinit(efuse);
201*4882a593Smuzhiyun 	kfree(buf);
202*4882a593Smuzhiyun nomem:
203*4882a593Smuzhiyun 	clk_disable_unprepare(efuse->clk);
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	return ret;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun static struct nvmem_config econfig = {
209*4882a593Smuzhiyun 	.name = "rk628-efuse",
210*4882a593Smuzhiyun 	.owner = THIS_MODULE,
211*4882a593Smuzhiyun 	.stride = 1,
212*4882a593Smuzhiyun 	.word_size = 1,
213*4882a593Smuzhiyun 	.read_only = true,
214*4882a593Smuzhiyun };
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun static const struct regmap_range rk628_efuse_readable_ranges[] = {
217*4882a593Smuzhiyun 	regmap_reg_range(RK628_EFUSE_BASE, RK628_EFUSE_BASE + EFUSE_REVISION),
218*4882a593Smuzhiyun };
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun static const struct regmap_access_table rk628_efuse_readable_table = {
221*4882a593Smuzhiyun 	.yes_ranges     = rk628_efuse_readable_ranges,
222*4882a593Smuzhiyun 	.n_yes_ranges   = ARRAY_SIZE(rk628_efuse_readable_ranges),
223*4882a593Smuzhiyun };
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun static const struct regmap_config rk628_efuse_regmap_config = {
226*4882a593Smuzhiyun 	.name = "rk628-efuse",
227*4882a593Smuzhiyun 	.reg_bits = 32,
228*4882a593Smuzhiyun 	.val_bits = 32,
229*4882a593Smuzhiyun 	.reg_stride = 4,
230*4882a593Smuzhiyun 	.max_register = RK628_EFUSE_BASE + EFUSE_REVISION,
231*4882a593Smuzhiyun 	.reg_format_endian = REGMAP_ENDIAN_LITTLE,
232*4882a593Smuzhiyun 	.val_format_endian = REGMAP_ENDIAN_LITTLE,
233*4882a593Smuzhiyun 	.rd_table = &rk628_efuse_readable_table,
234*4882a593Smuzhiyun };
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun static const struct of_device_id rk628_efuse_match[] = {
237*4882a593Smuzhiyun 	{
238*4882a593Smuzhiyun 		.compatible = "rockchip,rk628-efuse",
239*4882a593Smuzhiyun 	},
240*4882a593Smuzhiyun 	{ /* sentinel */ },
241*4882a593Smuzhiyun };
242*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, rk628_efuse_match);
243*4882a593Smuzhiyun 
rk628_efuse_probe(struct platform_device * pdev)244*4882a593Smuzhiyun static int __init rk628_efuse_probe(struct platform_device *pdev)
245*4882a593Smuzhiyun {
246*4882a593Smuzhiyun 	struct nvmem_device *nvmem;
247*4882a593Smuzhiyun 	struct rk628_efuse_chip *efuse;
248*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
249*4882a593Smuzhiyun 	struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
250*4882a593Smuzhiyun 	int ret;
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	efuse = devm_kzalloc(&pdev->dev, sizeof(struct rk628_efuse_chip),
253*4882a593Smuzhiyun 			     GFP_KERNEL);
254*4882a593Smuzhiyun 	if (!efuse)
255*4882a593Smuzhiyun 		return -ENOMEM;
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	efuse->regmap = devm_regmap_init_i2c(rk628->client,
258*4882a593Smuzhiyun 					&rk628_efuse_regmap_config);
259*4882a593Smuzhiyun 	if (IS_ERR(efuse->regmap)) {
260*4882a593Smuzhiyun 		ret = PTR_ERR(efuse->regmap);
261*4882a593Smuzhiyun 		dev_err(dev, "failed to allocate register map: %d\n",
262*4882a593Smuzhiyun 				   ret);
263*4882a593Smuzhiyun 		return ret;
264*4882a593Smuzhiyun 	}
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	efuse->clk = devm_clk_get(&pdev->dev, "pclk");
267*4882a593Smuzhiyun 	if (IS_ERR(efuse->clk)) {
268*4882a593Smuzhiyun 		dev_err(dev, "failed to get pclk: %ld\n", PTR_ERR(efuse->clk));
269*4882a593Smuzhiyun 		return PTR_ERR(efuse->clk);
270*4882a593Smuzhiyun 	}
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	efuse->avdd_gpio = devm_gpiod_get_optional(dev, "efuse", GPIOD_OUT_LOW);
273*4882a593Smuzhiyun 	efuse->base = RK628_EFUSE_BASE;
274*4882a593Smuzhiyun 	efuse->dev = &pdev->dev;
275*4882a593Smuzhiyun 	econfig.size = EFUSE_SIZE;
276*4882a593Smuzhiyun 	econfig.reg_read = (void *)&rk628_efuse_read;
277*4882a593Smuzhiyun 	econfig.priv = efuse;
278*4882a593Smuzhiyun 	econfig.dev = efuse->dev;
279*4882a593Smuzhiyun 	nvmem = devm_nvmem_register(&econfig);
280*4882a593Smuzhiyun 	if (IS_ERR(nvmem))
281*4882a593Smuzhiyun 		return PTR_ERR(nvmem);
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun 	platform_set_drvdata(pdev, nvmem);
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 	return 0;
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun static struct platform_driver rk628_efuse_driver = {
289*4882a593Smuzhiyun 	.probe = rk628_efuse_probe,
290*4882a593Smuzhiyun 	.driver = {
291*4882a593Smuzhiyun 		.name = "rk628-efuse",
292*4882a593Smuzhiyun 		.of_match_table = rk628_efuse_match,
293*4882a593Smuzhiyun 	},
294*4882a593Smuzhiyun };
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun module_platform_driver(rk628_efuse_driver);
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun MODULE_DESCRIPTION("rk628_efuse driver");
299*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
300