1 /* 2 * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. 3 * Copyright (c) 2015 iComm Corporation 4 * 5 * This program is free software: you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation, either version 3 of the License, or 8 * (at your option) any later version. 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 12 * See the GNU General Public License for more details. 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef _SSV6200_COMMON_H_ 18 #define _SSV6200_COMMON_H_ 19 #define FW_VERSION_REG ADR_TX_SEG 20 #define M_ENG_CPU 0x00 21 #define M_ENG_HWHCI 0x01 22 #define M_ENG_EMPTY 0x02 23 #define M_ENG_ENCRYPT 0x03 24 #define M_ENG_MACRX 0x04 25 #define M_ENG_MIC 0x05 26 #define M_ENG_TX_EDCA0 0x06 27 #define M_ENG_TX_EDCA1 0x07 28 #define M_ENG_TX_EDCA2 0x08 29 #define M_ENG_TX_EDCA3 0x09 30 #define M_ENG_TX_MNG 0x0A 31 #define M_ENG_ENCRYPT_SEC 0x0B 32 #define M_ENG_MIC_SEC 0x0C 33 #define M_ENG_RESERVED_1 0x0D 34 #define M_ENG_RESERVED_2 0x0E 35 #define M_ENG_TRASH_CAN 0x0F 36 #define M_ENG_MAX (M_ENG_TRASH_CAN+1) 37 #define M_CPU_HWENG 0x00 38 #define M_CPU_TXL34CS 0x01 39 #define M_CPU_RXL34CS 0x02 40 #define M_CPU_DEFRAG 0x03 41 #define M_CPU_EDCATX 0x04 42 #define M_CPU_RXDATA 0x05 43 #define M_CPU_RXMGMT 0x06 44 #define M_CPU_RXCTRL 0x07 45 #define M_CPU_FRAG 0x08 46 #define M_CPU_TXTPUT 0x09 47 #ifndef ID_TRAP_SW_TXTPUT 48 #define ID_TRAP_SW_TXTPUT 50 49 #endif 50 #define M0_TXREQ 0 51 #define M1_TXREQ 1 52 #define M2_TXREQ 2 53 #define M0_RXEVENT 3 54 #define M2_RXEVENT 4 55 #define HOST_CMD 5 56 #define HOST_EVENT 6 57 #define TEST_CMD 7 58 #define SSV6XXX_RX_DESC_LEN \ 59 (sizeof(struct ssv6200_rx_desc) + \ 60 sizeof(struct ssv6200_rxphy_info)) 61 #define SSV6XXX_TX_DESC_LEN \ 62 (sizeof(struct ssv6200_tx_desc) + 0) 63 #define TXPB_OFFSET 80 64 #define RXPB_OFFSET 80 65 #define SSV6200_TX_PKT_RSVD_SETTING 0x3 66 #define SSV6200_TX_PKT_RSVD SSV6200_TX_PKT_RSVD_SETTING*16 67 #define SSV6200_ALLOC_RSVD TXPB_OFFSET+SSV6200_TX_PKT_RSVD 68 #define SSV62XX_TX_MAX_RATES 3 69 70 enum ssv6xxx_sr_bhvr { 71 SUSPEND_RESUME_0, 72 SUSPEND_RESUME_1, 73 SUSPEND_RESUME_MAX 74 }; 75 76 enum ssv6xxx_reboot_bhvr { 77 SSV_SYS_REBOOT = 1, 78 SSV_SYS_HALF, 79 SSV_SYS_POWER_OFF 80 }; 81 82 struct fw_rc_retry_params { 83 u32 count:4; 84 u32 drate:6; 85 u32 crate:6; 86 u32 rts_cts_nav:16; 87 u32 frame_consume_time:10; 88 u32 dl_length:12; 89 u32 RSVD:10; 90 } __attribute__((packed)); 91 struct ssv6200_tx_desc 92 { 93 u32 len:16; 94 u32 c_type:3; 95 u32 f80211:1; 96 u32 qos:1; 97 u32 ht:1; 98 u32 use_4addr:1; 99 u32 RSVD_0:3; 100 u32 bc_que:1; 101 u32 security:1; 102 u32 more_data:1; 103 u32 stype_b5b4:2; 104 u32 extra_info:1; 105 u32 fCmd; 106 u32 hdr_offset:8; 107 u32 frag:1; 108 u32 unicast:1; 109 u32 hdr_len:6; 110 u32 tx_report:1; 111 u32 tx_burst:1; 112 u32 ack_policy:2; 113 u32 aggregation:1; 114 u32 RSVD_1:3; 115 u32 do_rts_cts:2; 116 u32 reason:6; 117 u32 payload_offset:8; 118 u32 RSVD_4:7; 119 u32 RSVD_2:1; 120 u32 fCmdIdx:3; 121 u32 wsid:4; 122 u32 txq_idx:3; 123 u32 TxF_ID:6; 124 u32 rts_cts_nav:16; 125 u32 frame_consume_time:10; 126 u32 crate_idx:6; 127 u32 drate_idx:6; 128 u32 dl_length:12; 129 u32 RSVD_3:14; 130 u32 RESERVED[8]; 131 struct fw_rc_retry_params rc_params[SSV62XX_TX_MAX_RATES]; 132 }; 133 struct ssv6200_rx_desc 134 { 135 u32 len:16; 136 u32 c_type:3; 137 u32 f80211:1; 138 u32 qos:1; 139 u32 ht:1; 140 u32 use_4addr:1; 141 u32 l3cs_err:1; 142 u32 l4cs_err:1; 143 u32 align2:1; 144 u32 RSVD_0:2; 145 u32 psm:1; 146 u32 stype_b5b4:2; 147 u32 extra_info:1; 148 u32 edca0_used:4; 149 u32 edca1_used:5; 150 u32 edca2_used:5; 151 u32 edca3_used:5; 152 u32 mng_used:4; 153 u32 tx_page_used:9; 154 u32 hdr_offset:8; 155 u32 frag:1; 156 u32 unicast:1; 157 u32 hdr_len:6; 158 u32 RxResult:8; 159 u32 wildcard_bssid:1; 160 u32 RSVD_1:1; 161 u32 reason:6; 162 u32 payload_offset:8; 163 u32 tx_id_used:8; 164 u32 fCmdIdx:3; 165 u32 wsid:4; 166 u32 RSVD_3:3; 167 u32 rate_idx:6; 168 }; 169 struct ssv6200_rxphy_info { 170 u32 len:16; 171 u32 rsvd0:16; 172 u32 mode:3; 173 u32 ch_bw:3; 174 u32 preamble:1; 175 u32 ht_short_gi:1; 176 u32 rate:7; 177 u32 rsvd1:1; 178 u32 smoothing:1; 179 u32 no_sounding:1; 180 u32 aggregate:1; 181 u32 stbc:2; 182 u32 fec:1; 183 u32 n_ess:2; 184 u32 rsvd2:8; 185 u32 l_length:12; 186 u32 l_rate:3; 187 u32 rsvd3:17; 188 u32 rsvd4; 189 u32 rpci:8; 190 u32 snr:8; 191 u32 service:16; 192 }; 193 struct ssv6200_rxphy_info_padding { 194 u32 rpci:8; 195 u32 snr:8; 196 u32 RSVD:16; 197 }; 198 struct ssv6200_txphy_info { 199 u32 rsvd[7]; 200 }; 201 #ifdef CONFIG_P2P_NOA 202 struct ssv6xxx_p2p_noa_param { 203 u32 duration; 204 u32 interval; 205 u32 start_time; 206 u32 enable:8; 207 u32 count:8; 208 u8 addr[6]; 209 u8 vif_id; 210 }__attribute__((packed)); 211 #endif 212 typedef struct cfg_host_cmd { 213 u32 len:16; 214 u32 c_type:3; 215 u32 RSVD0:5; 216 u32 h_cmd:8; 217 u32 cmd_seq_no; 218 union { 219 u32 dummy; 220 u8 dat8[0]; 221 u16 dat16[0]; 222 u32 dat32[0]; 223 }; 224 } HDR_HostCmd; 225 #define HOST_CMD_HDR_LEN ((size_t)(((HDR_HostCmd *)100)->dat8)-100U) 226 struct sdio_rxtput_cfg { 227 u32 size_per_frame; 228 u32 total_frames; 229 }; 230 typedef enum{ 231 SSV6XXX_HOST_CMD_START = 0 , 232 SSV6XXX_HOST_CMD_LOG , 233 SSV6XXX_HOST_CMD_PS , 234 SSV6XXX_HOST_CMD_INIT_CALI , 235 SSV6XXX_HOST_CMD_RX_TPUT , 236 SSV6XXX_HOST_CMD_TX_TPUT , 237 SSV6XXX_HOST_CMD_WATCHDOG_START, 238 SSV6XXX_HOST_CMD_WATCHDOG_STOP, 239 #ifdef FW_WSID_WATCH_LIST 240 SSV6XXX_HOST_CMD_WSID_OP , 241 #endif 242 #ifdef CONFIG_P2P_NOA 243 SSV6XXX_HOST_CMD_SET_NOA , 244 #endif 245 SSV6XXX_HOST_SOC_CMD_MAXID , 246 }ssv6xxx_host_cmd_id; 247 #define SSV_NUM_HW_STA 2 248 typedef struct cfg_host_event { 249 u32 len:16; 250 u32 c_type:3; 251 u32 RSVD0:5; 252 u32 h_event:8; 253 u32 evt_seq_no; 254 u8 dat[0]; 255 } HDR_HostEvent; 256 typedef enum{ 257 #ifdef USE_CMD_RESP 258 SOC_EVT_CMD_RESP , 259 SOC_EVT_SCAN_RESULT , 260 SOC_EVT_DEAUTH , 261 #else 262 SOC_EVT_GET_REG_RESP , 263 #endif 264 SOC_EVT_NO_BA , 265 SOC_EVT_RC_MPDU_REPORT , 266 SOC_EVT_RC_AMPDU_REPORT , 267 SOC_EVT_LOG , 268 #ifdef CONFIG_P2P_NOA 269 SOC_EVT_NOA , 270 #endif 271 SOC_EVT_USER_END , 272 SOC_EVT_SDIO_TEST_COMMAND , 273 SOC_EVT_RESET_HOST , 274 SOC_EVT_SDIO_TXTPUT_RESULT , 275 SOC_EVT_WATCHDOG_TRIGGER , 276 SOC_EVT_TXLOOPBK_RESULT , 277 SOC_EVT_MAXID , 278 } ssv6xxx_soc_event; 279 #ifdef CONFIG_P2P_NOA 280 typedef enum{ 281 SSV6XXX_NOA_START = 0 , 282 SSV6XXX_NOA_STOP , 283 }ssv6xxx_host_noa_event; 284 struct ssv62xx_noa_evt { 285 u8 evt_id; 286 u8 vif; 287 } __attribute__((packed)); 288 #endif 289 typedef enum{ 290 SSV6XXX_RC_COUNTER_CLEAR = 1 , 291 SSV6XXX_RC_REPORT , 292 }ssv6xxx_host_rate_control_event; 293 #define MAX_AGGR_NUM (24) 294 struct ssv62xx_tx_rate { 295 s8 data_rate; 296 u8 count; 297 } __attribute__((packed)); 298 struct ampdu_ba_notify_data { 299 u8 wsid; 300 struct ssv62xx_tx_rate tried_rates[SSV62XX_TX_MAX_RATES]; 301 u16 seq_no[MAX_AGGR_NUM]; 302 } __attribute__((packed)); 303 struct firmware_rate_control_report_data{ 304 u8 wsid; 305 struct ssv62xx_tx_rate rates[SSV62XX_TX_MAX_RATES]; 306 u16 ampdu_len; 307 u16 ampdu_ack_len; 308 int ack_signal; 309 } __attribute__((packed)); 310 #define RC_RETRY_PARAM_OFFSET ((sizeof(struct fw_rc_retry_params))*SSV62XX_TX_MAX_RATES) 311 #define SSV_RC_RATE_MAX 39 312 #ifdef FW_WSID_WATCH_LIST 313 enum SSV6XXX_WSID_OPS 314 { 315 SSV6XXX_WSID_OPS_ADD, 316 SSV6XXX_WSID_OPS_DEL, 317 SSV6XXX_WSID_OPS_RESETALL, 318 SSV6XXX_WSID_OPS_ENABLE_CAPS, 319 SSV6XXX_WSID_OPS_DISABLE_CAPS, 320 SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE, 321 SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE, 322 SSV6XXX_WSID_OPS_MAX 323 }; 324 enum SSV6XXX_WSID_SEC 325 { 326 SSV6XXX_WSID_SEC_NONE = 0, 327 SSV6XXX_WSID_SEC_PAIRWISE = 1<<0, 328 SSV6XXX_WSID_SEC_GROUP = 1<<1, 329 }; 330 enum SSV6XXX_WSID_SEC_TYPE 331 { 332 SSV6XXX_WSID_SEC_SW, 333 SSV6XXX_WSID_SEC_HW, 334 SSV6XXX_WSID_SEC_TYPE_MAX 335 }; 336 enum SSV6XXX_RETURN_STATE 337 { 338 SSV6XXX_STATE_OK, 339 SSV6XXX_STATE_NG, 340 SSV6XXX_STATE_MAX 341 }; 342 struct ssv6xxx_wsid_params 343 { 344 u8 cmd; 345 u8 wsid_idx; 346 u8 target_wsid[6]; 347 u8 hw_security; 348 }; 349 #endif 350 struct ssv6xxx_iqk_cfg { 351 u32 cfg_xtal:8; 352 u32 cfg_pa:8; 353 u32 cfg_pabias_ctrl:8; 354 u32 cfg_pacascode_ctrl:8; 355 u32 cfg_tssi_trgt:8; 356 u32 cfg_tssi_div:8; 357 u32 cfg_def_tx_scale_11b:8; 358 u32 cfg_def_tx_scale_11b_p0d5:8; 359 u32 cfg_def_tx_scale_11g:8; 360 u32 cfg_def_tx_scale_11g_p0d5:8; 361 u32 cmd_sel; 362 union { 363 u32 fx_sel; 364 u32 argv; 365 }; 366 u32 phy_tbl_size; 367 u32 rf_tbl_size; 368 }; 369 #define PHY_SETTING_SIZE sizeof(phy_setting) 370 #ifdef CONFIG_SSV_CABRIO_E 371 struct ssv6xxx_ch_cfg { 372 u32 reg_addr; 373 u32 ch1_12_value; 374 u32 ch13_14_value; 375 }; 376 #define IQK_CFG_LEN (sizeof(struct ssv6xxx_iqk_cfg)) 377 #define RF_SETTING_SIZE (sizeof(asic_rf_setting)) 378 #endif 379 #define MAX_PHY_SETTING_TABLE_SIZE 1920 380 #define MAX_RF_SETTING_TABLE_SIZE 512 381 typedef enum { 382 SSV6XXX_VOLT_DCDC_CONVERT = 0, 383 SSV6XXX_VOLT_LDO_CONVERT, 384 } ssv6xxx_cfg_volt; 385 typedef enum { 386 SSV6XXX_VOLT_33V = 0, 387 SSV6XXX_VOLT_42V, 388 } ssv6xxx_cfg_volt_value; 389 typedef enum { 390 SSV6XXX_IQK_CFG_XTAL_26M = 0, 391 SSV6XXX_IQK_CFG_XTAL_40M, 392 SSV6XXX_IQK_CFG_XTAL_24M, 393 SSV6XXX_IQK_CFG_XTAL_MAX, 394 } ssv6xxx_iqk_cfg_xtal; 395 typedef enum { 396 SSV6XXX_IQK_CFG_PA_DEF = 0, 397 SSV6XXX_IQK_CFG_PA_LI_MPB, 398 SSV6XXX_IQK_CFG_PA_LI_EVB, 399 SSV6XXX_IQK_CFG_PA_HP, 400 } ssv6xxx_iqk_cfg_pa; 401 typedef enum { 402 SSV6XXX_IQK_CMD_INIT_CALI = 0, 403 SSV6XXX_IQK_CMD_RTBL_LOAD, 404 SSV6XXX_IQK_CMD_RTBL_LOAD_DEF, 405 SSV6XXX_IQK_CMD_RTBL_RESET, 406 SSV6XXX_IQK_CMD_RTBL_SET, 407 SSV6XXX_IQK_CMD_RTBL_EXPORT, 408 SSV6XXX_IQK_CMD_TK_EVM, 409 SSV6XXX_IQK_CMD_TK_TONE, 410 SSV6XXX_IQK_CMD_TK_CHCH, 411 } ssv6xxx_iqk_cmd_sel; 412 #define SSV6XXX_IQK_TEMPERATURE 0x00000004 413 #define SSV6XXX_IQK_RXDC 0x00000008 414 #define SSV6XXX_IQK_RXRC 0x00000010 415 #define SSV6XXX_IQK_TXDC 0x00000020 416 #define SSV6XXX_IQK_TXIQ 0x00000040 417 #define SSV6XXX_IQK_RXIQ 0x00000080 418 #define SSV6XXX_IQK_TSSI 0x00000100 419 #define SSV6XXX_IQK_PAPD 0x00000200 420 typedef struct ssv_cabrio_reg_st { 421 u32 address; 422 u32 data; 423 } ssv_cabrio_reg; 424 typedef enum __PBuf_Type_E { 425 NOTYPE_BUF = 0, 426 TX_BUF = 1, 427 RX_BUF = 2 428 } PBuf_Type_E; 429 struct SKB_info_st 430 { 431 struct ieee80211_sta *sta; 432 u16 mpdu_retry_counter; 433 unsigned long aggr_timestamp; 434 u16 ampdu_tx_status; 435 u16 ampdu_tx_final_retry_count; 436 u16 lowest_rate; 437 struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES]; 438 #ifdef CONFIG_DEBUG_SKB_TIMESTAMP 439 ktime_t timestamp; 440 #endif 441 #ifdef MULTI_THREAD_ENCRYPT 442 volatile u8 crypt_st; 443 #endif 444 }; 445 typedef struct SKB_info_st SKB_info; 446 typedef struct SKB_info_st *p_SKB_info; 447 #define SSV_SKB_info_size (sizeof(struct SKB_info_st)) 448 #ifdef MULTI_THREAD_ENCRYPT 449 enum ssv_pkt_crypt_status 450 { 451 PKT_CRYPT_ST_DEC_PRE, 452 PKT_CRYPT_ST_ENC_PRE, 453 PKT_CRYPT_ST_DEC_DONE, 454 PKT_CRYPT_ST_ENC_DONE, 455 PKT_CRYPT_ST_FAIL, 456 PKT_CRYPT_ST_NOT_SUPPORT 457 }; 458 #endif 459 #ifdef CONFIG_DEBUG_SKB_TIMESTAMP 460 #define SKB_DURATION_TIMEOUT_MS 100 461 enum ssv_debug_skb_timestamp 462 { 463 SKB_DURATION_STAGE_TX_ENQ, 464 SKB_DURATION_STAGE_TO_SDIO, 465 SKB_DURATION_STAGE_IN_HWQ, 466 SKB_DURATION_STAGE_END 467 }; 468 #endif 469 #define SSV6051Q_P1 0x00000000 470 #define SSV6051Q_P2 0x70000000 471 #define SSV6051Z 0x71000000 472 #define SSV6051Q 0x73000000 473 #define SSV6051P 0x75000000 474 #ifdef CONFIG_SSV_CABRIO_E 475 struct ssv6xxx_tx_loopback { 476 u32 reg; 477 u32 val; 478 u32 restore_val; 479 u8 restore; 480 u8 delay_ms; 481 }; 482 #endif 483 #endif 484