1 /****************************************************************************** 2 * 3 * Copyright(c) 2015 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifdef CONFIG_MCC_MODE 16 17 #ifndef _RTW_MCC_H_ 18 #define _RTW_MCC_H_ 19 20 #include <drv_types.h> /* PADAPTER */ 21 22 #define MCC_STATUS_PROCESS_MCC_START_SETTING BIT0 23 #define MCC_STATUS_PROCESS_MCC_STOP_SETTING BIT1 24 #define MCC_STATUS_NEED_MCC BIT2 25 #define MCC_STATUS_DOING_MCC BIT3 26 27 28 #define MCC_SWCH_FW_EARLY_TIME 10 /* ms */ 29 #define MCC_EXPIRE_TIME 50 /* ms */ 30 #define MCC_TOLERANCE_TIME 2 /* 2*2 = 4s */ 31 #define MCC_UPDATE_PARAMETER_THRESHOLD 5 /* ms */ 32 33 #define MCC_ROLE_STA_GC_MGMT_QUEUE_MACID 0 34 #define MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID 1 35 36 /* Lower for stop, Higher for start */ 37 #define MCC_SETCMD_STATUS_STOP_DISCONNECT 0x0 38 #define MCC_SETCMD_STATUS_STOP_SCAN_START 0x1 39 #define MCC_SETCMD_STATUS_START_CONNECT 0x80 40 #define MCC_SETCMD_STATUS_START_SCAN_DONE 0x81 41 42 /* 43 * depenad platform or customer requirement(TP unit:Mbps), 44 * must be provided by PM or sales or product document 45 * too large value means not to limit tx bytes (current for ap mode) 46 * NOTE: following values ref from test results 47 */ 48 #define MCC_AP_BW20_TARGET_TX_TP (300) 49 #define MCC_AP_BW40_TARGET_TX_TP (300) 50 #define MCC_AP_BW80_TARGET_TX_TP (300) 51 #define MCC_STA_BW20_TARGET_TX_TP (35) 52 #define MCC_STA_BW40_TARGET_TX_TP (70) 53 #define MCC_STA_BW80_TARGET_TX_TP (140) 54 #define MCC_SINGLE_TX_CRITERIA 5 /* Mbps */ 55 56 #define MAX_MCC_NUM 2 57 #define DBG_MCC_REG_NUM 4 58 #define DBG_MCC_RF_REG_NUM 1 59 60 #define MCC_STOP(adapter) (adapter->mcc_adapterpriv.mcc_tx_stop) 61 #define MCC_EN(adapter) (adapter_to_dvobj(adapter)->mcc_objpriv.en_mcc) 62 #define adapter_to_mccobjpriv(adapter) (&(adapter_to_dvobj(adapter)->mcc_objpriv)) 63 #define SET_MCC_EN_FLAG(adapter, flag)\ 64 do { \ 65 adapter_to_dvobj(adapter)->mcc_objpriv.en_mcc = (flag); \ 66 } while (0) 67 #define SET_MCC_DURATION(adapter, val)\ 68 do { \ 69 adapter_to_dvobj(adapter)->mcc_objpriv.duration = (val); \ 70 } while (0) 71 #define SET_MCC_RUNTIME_DURATION(adapter, flag)\ 72 do { \ 73 adapter_to_dvobj(adapter)->mcc_objpriv.enable_runtime_duration = (flag); \ 74 } while (0) 75 76 #define SET_MCC_PHYDM_OFFLOAD(adapter, flag)\ 77 do { \ 78 adapter_to_dvobj(adapter)->mcc_objpriv.mcc_phydm_offload = (flag); \ 79 } while (0) 80 81 #ifdef CONFIG_MCC_PHYDM_OFFLOAD 82 enum mcc_cfg_phydm_ops { 83 MCC_CFG_PHYDM_OFFLOAD = 0, 84 MCC_CFG_PHYDM_RF_CH, 85 MCC_CFG_PHYDM_ADD_CLIENT, 86 MCC_CFG_PHYDM_REMOVE_CLIENT, 87 MCC_CFG_PHYDM_START, 88 MCC_CFG_PHYDM_STOP, 89 MCC_CFG_PHYDM_DUMP, 90 MCC_CFG_PHYDM_MAX, 91 }; 92 #endif 93 94 enum rtw_mcc_cmd_id { 95 MCC_CMD_WK_CID = 0, 96 MCC_SET_DURATION_WK_CID, 97 MCC_GET_DBG_REG_WK_CID, 98 #ifdef CONFIG_MCC_PHYDM_OFFLOAD 99 MCC_SET_PHYDM_OFFLOAD_WK_CID, 100 #endif 101 }; 102 103 /* Represent Channel Tx Null setting */ 104 enum mcc_channel_tx_null { 105 MCC_ENABLE_TX_NULL = 0, 106 MCC_DISABLE_TX_NULL = 1, 107 }; 108 109 /* Represent C2H Report setting */ 110 enum mcc_c2h_report { 111 MCC_C2H_REPORT_DISABLE = 0, 112 MCC_C2H_REPORT_FAIL_STATUS = 1, 113 MCC_C2H_REPORT_ALL_STATUS = 2, 114 }; 115 116 /* Represent Channel Scan */ 117 enum mcc_channel_scan { 118 MCC_CHIDX = 0, 119 MCC_SCANCH_RSVD_LOC = 1, 120 }; 121 122 /* Represent FW status report of channel switch */ 123 enum mcc_status_rpt { 124 MCC_RPT_SUCCESS = 0, 125 MCC_RPT_TXNULL_FAIL = 1, 126 MCC_RPT_STOPMCC = 2, 127 MCC_RPT_READY = 3, 128 MCC_RPT_SWICH_CHANNEL_NOTIFY = 7, 129 MCC_RPT_UPDATE_NOA_START_TIME = 8, 130 MCC_RPT_TSF = 9, 131 MCC_RPT_MAX, 132 }; 133 134 enum mcc_role { 135 MCC_ROLE_STA = 0, 136 MCC_ROLE_AP = 1, 137 MCC_ROLE_GC = 2, 138 MCC_ROLE_GO = 3, 139 MCC_ROLE_MAX, 140 }; 141 142 struct mcc_iqk_backup { 143 u16 TX_X; 144 u16 TX_Y; 145 u16 RX_X; 146 u16 RX_Y; 147 }; 148 149 enum mcc_duration_setting { 150 MCC_DURATION_MAPPING = 0, 151 MCC_DURATION_DIRECET = 1, 152 }; 153 154 enum mcc_sched_mode { 155 MCC_FAIR_SCHEDULE = 0, 156 MCC_FAVOR_STA = 1, 157 MCC_FAVOR_P2P = 2, 158 }; 159 160 /* mcc data for adapter */ 161 struct mcc_adapter_priv { 162 u8 order; /* FW document, softap/AP must be 0 */ 163 enum mcc_role role; /* MCC role(AP,STA,GO,GC) */ 164 u8 mcc_duration; /* channel stay period, UNIT:1TU */ 165 166 /* flow control */ 167 u8 mcc_tx_stop; /* check if tp stop or not */ 168 u8 mcc_tp_limit; /* check if tp limit or not */ 169 u32 mcc_target_tx_bytes_to_port; /* customer require */ 170 u32 mcc_tx_bytes_to_port; /* already tx to tx fifo (write port) */ 171 172 /* data from kernel to check if enqueue data or netif stop queue */ 173 u32 mcc_tp; 174 u64 mcc_tx_bytes_from_kernel; 175 u64 mcc_last_tx_bytes_from_kernel; 176 177 /* Backup IQK value for MCC */ 178 struct mcc_iqk_backup mcc_iqk_arr[MAX_RF_PATH]; 179 180 /* mgmt queue macid to avoid RA issue */ 181 u8 mgmt_queue_macid; 182 183 /* set macid bitmap to let fw know which macid should be tx pause */ 184 /* all interface share total 16 macid */ 185 u16 mcc_macid_bitmap; 186 187 /* use for NoA start time (unit: mircoseconds) */ 188 u32 noa_start_time; 189 190 u8 p2p_go_noa_ie[MAX_P2P_IE_LEN]; 191 u32 p2p_go_noa_ie_len; 192 u64 tsf; 193 #ifdef CONFIG_TDLS 194 u8 backup_tdls_en; 195 #endif /* CONFIG_TDLS */ 196 197 u8 null_early; 198 u8 null_rty_num; 199 }; 200 201 struct mcc_obj_priv { 202 u8 en_mcc; /* enable MCC or not */ 203 u8 duration; /* store duration(%) from registry, for primary adapter */ 204 u8 interval; 205 u8 start_time; 206 u8 mcc_c2h_status; 207 u8 cur_mcc_success_cnt; /* used for check mcc switch channel success */ 208 u8 prev_mcc_success_cnt; /* used for check mcc switch channel success */ 209 u8 mcc_tolerance_time; /* used for detect mcc switch channel success */ 210 u8 mcc_loc_rsvd_paga[MAX_MCC_NUM]; /* mcc rsvd page */ 211 u8 mcc_status; /* mcc status stop or start .... */ 212 u8 policy_index; 213 u8 mcc_stop_threshold; 214 u8 current_order; 215 u8 last_tsfdiff; 216 systime mcc_launch_time; /* mcc launch time, used for starting detect mcc switch channel success */ 217 _mutex mcc_mutex; 218 _lock mcc_lock; 219 PADAPTER iface[MAX_MCC_NUM]; /* by order, use for mcc parameter cmd */ 220 struct submit_ctx mcc_sctx; 221 struct submit_ctx mcc_tsf_req_sctx; 222 _mutex mcc_tsf_req_mutex; 223 u8 mcc_tsf_req_sctx_order; /* record current order for mcc_tsf_req_sctx */ 224 #ifdef CONFIG_MCC_MODE_V2 225 u8 mcc_iqk_value_rsvd_page[3]; 226 #endif /* CONFIG_MCC_MODE_V2 */ 227 u8 mcc_pwr_idx_rsvd_page[MAX_MCC_NUM]; 228 u8 enable_runtime_duration; 229 /* for LG */ 230 u8 mchan_sched_mode; 231 232 _mutex mcc_dbg_reg_mutex; 233 u32 dbg_reg[DBG_MCC_REG_NUM]; 234 u32 dbg_reg_val[DBG_MCC_REG_NUM]; 235 u32 dbg_rf_reg[DBG_MCC_RF_REG_NUM]; 236 u32 dbg_rf_reg_val[DBG_MCC_RF_REG_NUM][MAX_RF_PATH]; 237 u8 mcc_phydm_offload; 238 }; 239 240 /* backup IQK val */ 241 void rtw_hal_mcc_restore_iqk_val(PADAPTER padapter); 242 243 /* check mcc status */ 244 u8 rtw_hal_check_mcc_status(PADAPTER padapter, u8 mcc_status); 245 246 /* set mcc status */ 247 void rtw_hal_set_mcc_status(PADAPTER padapter, u8 mcc_status); 248 249 /* clear mcc status */ 250 void rtw_hal_clear_mcc_status(PADAPTER padapter, u8 mcc_status); 251 252 /* dl mcc rsvd page */ 253 u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index 254 , u8 tx_desc, u32 page_size, u8 *total_page_num, RSVDPAGE_LOC *rsvd_page_loc, u8 *page_num); 255 256 /* handle C2H */ 257 void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf); 258 259 /* switch channel successfully or not */ 260 void rtw_hal_mcc_sw_status_check(PADAPTER padapter); 261 262 /* change some scan flags under site survey */ 263 u8 rtw_hal_mcc_change_scan_flag(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset); 264 265 /* record data kernel TX to driver to check MCC concurrent TX */ 266 void rtw_hal_mcc_calc_tx_bytes_from_kernel(PADAPTER padapter, u32 len); 267 268 /* record data to port to let driver do flow ctrl */ 269 void rtw_hal_mcc_calc_tx_bytes_to_port(PADAPTER padapter, u32 len); 270 271 /* check stop write port or not */ 272 u8 rtw_hal_mcc_stop_tx_bytes_to_port(PADAPTER padapter); 273 274 u8 rtw_hal_set_mcc_setting_scan_start(PADAPTER padapter); 275 276 u8 rtw_hal_set_mcc_setting_scan_complete(PADAPTER padapter); 277 278 u8 rtw_hal_set_mcc_setting_start_bss_network(PADAPTER padapter, u8 chbw_grouped); 279 280 u8 rtw_hal_set_mcc_setting_disconnect(PADAPTER padapter); 281 282 u8 rtw_hal_set_mcc_setting_join_done_chk_ch(PADAPTER padapter); 283 284 u8 rtw_hal_set_mcc_setting_chk_start_clnt_join(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset, u8 chbw_allow); 285 286 void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj); 287 288 void update_mcc_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib); 289 290 u8 rtw_hal_mcc_link_status_chk(_adapter *padapter, const char *msg); 291 292 void rtw_hal_mcc_issue_null_data(_adapter *padapter, u8 chbw_allow, u8 ps_mode); 293 294 u8 *rtw_hal_mcc_append_go_p2p_ie(PADAPTER padapter, u8 *pframe, u32 *len); 295 296 void rtw_hal_dump_mcc_policy_table(void *sel); 297 298 void rtw_hal_mcc_update_macid_bitmap(PADAPTER padapter, int mac_id, u8 add); 299 300 void rtw_hal_mcc_process_noa(PADAPTER padapter); 301 302 void rtw_hal_mcc_parameter_init(PADAPTER padapter); 303 304 u8 rtw_mcc_cmd_hdl(PADAPTER adapter, u8 type, const u8 *val); 305 306 u8 rtw_set_mcc_duration_cmd(_adapter *adapter, u8 type, u8 val); 307 #ifdef CONFIG_MCC_PHYDM_OFFLOAD 308 u8 rtw_set_mcc_phydm_offload_enable_cmd(PADAPTER adapter, u8 enable, u8 enqueue); 309 #endif /* CONFIG_MCC_PHYDM_OFFLOAD */ 310 #endif /* _RTW_MCC_H_ */ 311 #endif /* CONFIG_MCC_MODE */ 312