1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __HAL_DATA_H__ 16 #define __HAL_DATA_H__ 17 18 #if 1/* def CONFIG_SINGLE_IMG */ 19 20 #include "../hal/phydm/phydm_precomp.h" 21 #ifdef CONFIG_BT_COEXIST 22 #include <hal_btcoex.h> 23 #endif 24 #include <hal_btcoex_wifionly.h> 25 26 #ifdef CONFIG_SDIO_HCI 27 #include <hal_sdio.h> 28 #endif 29 #ifdef CONFIG_GSPI_HCI 30 #include <hal_gspi.h> 31 #endif 32 33 #if defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR) 34 #include "../hal/hal_dm_acs.h" 35 #endif 36 37 /* 38 * <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. 39 * */ 40 typedef enum _RT_MULTI_FUNC { 41 RT_MULTI_FUNC_NONE = 0x00, 42 RT_MULTI_FUNC_WIFI = 0x01, 43 RT_MULTI_FUNC_BT = 0x02, 44 RT_MULTI_FUNC_GPS = 0x04, 45 } RT_MULTI_FUNC, *PRT_MULTI_FUNC; 46 /* 47 * <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. 48 * */ 49 typedef enum _RT_POLARITY_CTL { 50 RT_POLARITY_LOW_ACT = 0, 51 RT_POLARITY_HIGH_ACT = 1, 52 } RT_POLARITY_CTL, *PRT_POLARITY_CTL; 53 54 /* For RTL8723 regulator mode. by tynli. 2011.01.14. */ 55 typedef enum _RT_REGULATOR_MODE { 56 RT_SWITCHING_REGULATOR = 0, 57 RT_LDO_REGULATOR = 1, 58 } RT_REGULATOR_MODE, *PRT_REGULATOR_MODE; 59 60 /* 61 * Interface type. 62 * */ 63 typedef enum _INTERFACE_SELECT_PCIE { 64 INTF_SEL0_SOLO_MINICARD = 0, /* WiFi solo-mCard */ 65 INTF_SEL1_BT_COMBO_MINICARD = 1, /* WiFi+BT combo-mCard */ 66 INTF_SEL2_PCIe = 2, /* PCIe Card */ 67 } INTERFACE_SELECT_PCIE, *PINTERFACE_SELECT_PCIE; 68 69 70 typedef enum _INTERFACE_SELECT_USB { 71 INTF_SEL0_USB = 0, /* USB */ 72 INTF_SEL1_USB_High_Power = 1, /* USB with high power PA */ 73 INTF_SEL2_MINICARD = 2, /* Minicard */ 74 INTF_SEL3_USB_Solo = 3, /* USB solo-Slim module */ 75 INTF_SEL4_USB_Combo = 4, /* USB Combo-Slim module */ 76 INTF_SEL5_USB_Combo_MF = 5, /* USB WiFi+BT Multi-Function Combo, i.e., Proprietary layout(AS-VAU) which is the same as SDIO card */ 77 } INTERFACE_SELECT_USB, *PINTERFACE_SELECT_USB; 78 79 typedef enum _RT_AMPDU_BRUST_MODE { 80 RT_AMPDU_BRUST_NONE = 0, 81 RT_AMPDU_BRUST_92D = 1, 82 RT_AMPDU_BRUST_88E = 2, 83 RT_AMPDU_BRUST_8812_4 = 3, 84 RT_AMPDU_BRUST_8812_8 = 4, 85 RT_AMPDU_BRUST_8812_12 = 5, 86 RT_AMPDU_BRUST_8812_15 = 6, 87 RT_AMPDU_BRUST_8723B = 7, 88 } RT_AMPDU_BRUST, *PRT_AMPDU_BRUST_MODE; 89 90 /* Tx Power Limit Table Size */ 91 #define MAX_REGULATION_NUM 4 92 #define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE 4 93 #define MAX_2_4G_BANDWIDTH_NUM 2 94 #define MAX_RATE_SECTION_NUM 10 95 #define MAX_5G_BANDWIDTH_NUM 4 96 97 #define NUM_OF_TARGET_TXPWR_2G 10 /* CCK:1, OFDM:1, HT:4, VHT:4 */ 98 #define NUM_OF_TARGET_TXPWR_5G 9 /* OFDM:1, HT:4, VHT:4 */ 99 100 #ifdef RTW_RX_AGGREGATION 101 typedef enum _RX_AGG_MODE { 102 RX_AGG_DISABLE, 103 RX_AGG_DMA, 104 RX_AGG_USB, 105 RX_AGG_MIX 106 } RX_AGG_MODE; 107 108 /* #define MAX_RX_DMA_BUFFER_SIZE 10240 */ /* 10K for 8192C RX DMA buffer */ 109 110 #endif /* RTW_RX_AGGREGATION */ 111 112 /* E-Fuse */ 113 #ifdef CONFIG_RTL8188E 114 #define EFUSE_MAP_SIZE 512 115 #endif 116 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) 117 #define EFUSE_MAP_SIZE 512 118 #endif 119 #ifdef CONFIG_RTL8192E 120 #define EFUSE_MAP_SIZE 512 121 #endif 122 #ifdef CONFIG_RTL8723B 123 #define EFUSE_MAP_SIZE 512 124 #endif 125 #ifdef CONFIG_RTL8814A 126 #define EFUSE_MAP_SIZE 512 127 #endif 128 #ifdef CONFIG_RTL8703B 129 #define EFUSE_MAP_SIZE 512 130 #endif 131 #ifdef CONFIG_RTL8723D 132 #define EFUSE_MAP_SIZE 512 133 #endif 134 #ifdef CONFIG_RTL8188F 135 #define EFUSE_MAP_SIZE 512 136 #endif 137 #ifdef CONFIG_RTL8188GTV 138 #define EFUSE_MAP_SIZE 512 139 #endif 140 #ifdef CONFIG_RTL8710B 141 #define EFUSE_MAP_SIZE 512 142 #endif 143 #ifdef CONFIG_RTL8192F 144 #define EFUSE_MAP_SIZE 512 145 #endif 146 147 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8814B) 148 #define EFUSE_MAX_SIZE 1024 149 #elif defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8710B) 150 #define EFUSE_MAX_SIZE 256 151 #else 152 #define EFUSE_MAX_SIZE 512 153 #endif 154 /* end of E-Fuse */ 155 156 #define Mac_OFDM_OK 0x00000000 157 #define Mac_OFDM_Fail 0x10000000 158 #define Mac_OFDM_FasleAlarm 0x20000000 159 #define Mac_CCK_OK 0x30000000 160 #define Mac_CCK_Fail 0x40000000 161 #define Mac_CCK_FasleAlarm 0x50000000 162 #define Mac_HT_OK 0x60000000 163 #define Mac_HT_Fail 0x70000000 164 #define Mac_HT_FasleAlarm 0x90000000 165 #define Mac_DropPacket 0xA0000000 166 167 #ifdef CONFIG_RF_POWER_TRIM 168 #if defined(CONFIG_RTL8723B) 169 #define REG_RF_BB_GAIN_OFFSET 0x7f 170 #define RF_GAIN_OFFSET_MASK 0xfffff 171 #elif defined(CONFIG_RTL8188E) 172 #define REG_RF_BB_GAIN_OFFSET 0x55 173 #define RF_GAIN_OFFSET_MASK 0xfffff 174 #else 175 #define REG_RF_BB_GAIN_OFFSET 0x55 176 #define RF_GAIN_OFFSET_MASK 0xfffff 177 #endif /* CONFIG_RTL8723B */ 178 #endif /*CONFIG_RF_POWER_TRIM*/ 179 180 /* For store initial value of BB register */ 181 typedef struct _BB_INIT_REGISTER { 182 u16 offset; 183 u32 value; 184 185 } BB_INIT_REGISTER, *PBB_INIT_REGISTER; 186 187 #define PAGE_SIZE_128 128 188 #define PAGE_SIZE_256 256 189 #define PAGE_SIZE_512 512 190 191 #define HCI_SUS_ENTER 0 192 #define HCI_SUS_LEAVING 1 193 #define HCI_SUS_LEAVE 2 194 #define HCI_SUS_ENTERING 3 195 #define HCI_SUS_ERR 4 196 197 #define EFUSE_FILE_UNUSED 0 198 #define EFUSE_FILE_FAILED 1 199 #define EFUSE_FILE_LOADED 2 200 201 #define MACADDR_FILE_UNUSED 0 202 #define MACADDR_FILE_FAILED 1 203 #define MACADDR_FILE_LOADED 2 204 205 #define MAX_IQK_INFO_BACKUP_CHNL_NUM 5 206 #define MAX_IQK_INFO_BACKUP_REG_NUM 10 207 208 struct kfree_data_t { 209 u8 flag; 210 s8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX]; 211 212 #if CONFIG_IEEE80211_BAND_5GHZ 213 s8 pa_bias_5g[RF_PATH_MAX]; 214 s8 pad_bias_5g[RF_PATH_MAX]; 215 #endif 216 s8 thermal; 217 }; 218 219 bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data); 220 221 struct hal_spec_t { 222 char *ic_name; 223 u8 macid_num; 224 225 u8 sec_cam_ent_num; 226 u8 sec_cap; 227 228 u8 rfpath_num_2g:4; /* used for tx power index path */ 229 u8 rfpath_num_5g:4; /* used for tx power index path */ 230 u8 rf_reg_path_num; 231 u8 max_tx_cnt; 232 233 u8 tx_nss_num:4; 234 u8 rx_nss_num:4; 235 236 u8 band_cap; /* value of BAND_CAP_XXX */ 237 u8 bw_cap; /* value of BW_CAP_XXX */ 238 u8 port_num; 239 u8 proto_cap; /* value of PROTO_CAP_XXX */ 240 241 u8 txgi_max; /* maximum tx power gain index */ 242 u8 txgi_pdbm; /* tx power gain index per dBm */ 243 244 u8 wl_func; /* value of WL_FUNC_XXX */ 245 246 #if CONFIG_TX_AC_LIFETIME 247 u8 tx_aclt_unit_factor; /* how many 32us */ 248 #endif 249 250 u8 rx_tsf_filter:1; 251 252 u8 pg_txpwr_saddr; /* starting address of PG tx power info */ 253 u8 pg_txgi_diff_factor; /* PG tx power gain index diff to tx power gain index */ 254 255 u8 hci_type; /* value of HCI Type */ 256 }; 257 258 #define HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) ((_spec)->rfpath_num_2g > (_path)) 259 #define HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) ((_spec)->rfpath_num_5g > (_path)) 260 #define HAL_SPEC_CHK_RF_PATH(_spec, _band, _path) ( \ 261 _band == BAND_ON_2_4G ? HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) : \ 262 _band == BAND_ON_5G ? HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) : 0) 263 264 #ifdef CONFIG_PHY_CAPABILITY_QUERY 265 struct phy_spec_t { 266 u32 trx_cap; 267 u32 stbc_cap; 268 u32 ldpc_cap; 269 u32 txbf_param; 270 u32 txbf_cap; 271 }; 272 #endif 273 struct hal_iqk_reg_backup { 274 u8 central_chnl; 275 u8 bw_mode; 276 u32 reg_backup[MAX_RF_PATH][MAX_IQK_INFO_BACKUP_REG_NUM]; 277 }; 278 279 280 typedef struct hal_p2p_ps_para { 281 /*DW0*/ 282 u8 offload_en:1; 283 u8 role:1; 284 u8 ctwindow_en:1; 285 u8 noa_en:1; 286 u8 noa_sel:1; 287 u8 all_sta_sleep:1; 288 u8 discovery:1; 289 u8 disable_close_rf:1; 290 u8 p2p_port_id; 291 u8 p2p_group; 292 u8 p2p_macid; 293 294 /*DW1*/ 295 u8 ctwindow_length; 296 u8 rsvd3; 297 u8 rsvd4; 298 u8 rsvd5; 299 300 /*DW2*/ 301 u32 noa_duration_para; 302 303 /*DW3*/ 304 u32 noa_interval_para; 305 306 /*DW4*/ 307 u32 noa_start_time_para; 308 309 /*DW5*/ 310 u32 noa_count_para; 311 } HAL_P2P_PS_PARA, *PHAL_P2P_PS_PARA; 312 313 #define TXPWR_LMT_RS_CCK 0 314 #define TXPWR_LMT_RS_OFDM 1 315 #define TXPWR_LMT_RS_HT 2 316 #define TXPWR_LMT_RS_VHT 3 317 #define TXPWR_LMT_RS_NUM 4 318 319 #define TXPWR_LMT_RS_NUM_2G 4 /* CCK, OFDM, HT, VHT */ 320 #define TXPWR_LMT_RS_NUM_5G 3 /* OFDM, HT, VHT */ 321 322 #if CONFIG_TXPWR_LIMIT 323 extern const char *const _txpwr_lmt_rs_str[]; 324 #define txpwr_lmt_rs_str(rs) (((rs) >= TXPWR_LMT_RS_NUM) ? _txpwr_lmt_rs_str[TXPWR_LMT_RS_NUM] : _txpwr_lmt_rs_str[(rs)]) 325 326 struct txpwr_lmt_ent { 327 _list list; 328 329 s8 lmt_2g[MAX_2_4G_BANDWIDTH_NUM] 330 [TXPWR_LMT_RS_NUM_2G] 331 [CENTER_CH_2G_NUM] 332 [MAX_TX_COUNT]; 333 334 #if CONFIG_IEEE80211_BAND_5GHZ 335 s8 lmt_5g[MAX_5G_BANDWIDTH_NUM] 336 [TXPWR_LMT_RS_NUM_5G] 337 [CENTER_CH_5G_ALL_NUM] 338 [MAX_TX_COUNT]; 339 #endif 340 341 char regd_name[0]; 342 }; 343 #endif /* CONFIG_TXPWR_LIMIT */ 344 345 typedef struct hal_com_data { 346 HAL_VERSION version_id; 347 RT_MULTI_FUNC MultiFunc; /* For multi-function consideration. */ 348 RT_POLARITY_CTL PolarityCtl; /* For Wifi PDn Polarity control. */ 349 RT_REGULATOR_MODE RegulatorMode; /* switching regulator or LDO */ 350 u8 hw_init_completed; 351 /****** FW related ******/ 352 u32 firmware_size; 353 u16 firmware_version; 354 u16 FirmwareVersionRev; 355 u16 firmware_sub_version; 356 u16 FirmwareSignature; 357 u8 RegFWOffload; 358 u8 bFWReady; 359 u8 bBTFWReady; 360 u8 fw_ractrl; 361 u8 LastHMEBoxNum; /* H2C - for host message to fw */ 362 #ifdef CONFIG_LPS_1T1R 363 u8 lps_1t1r; 364 #endif 365 366 /****** current WIFI_PHY values ******/ 367 WIRELESS_MODE CurrentWirelessMode; 368 enum channel_width current_channel_bw; 369 BAND_TYPE current_band_type; /* 0:2.4G, 1:5G */ 370 BAND_TYPE BandSet; 371 u8 current_channel; 372 u8 cch_20; 373 u8 cch_40; 374 u8 cch_80; 375 u8 CurrentCenterFrequencyIndex1; 376 u8 nCur40MhzPrimeSC; /* Control channel sub-carrier */ 377 u8 nCur80MhzPrimeSC; /* used for primary 40MHz of 80MHz mode */ 378 BOOLEAN bSwChnlAndSetBWInProgress; 379 u8 bDisableSWChannelPlan; /* flag of disable software change channel plan */ 380 u16 BasicRateSet; 381 u32 ReceiveConfig; 382 u32 rcr_backup; /* used for switching back from monitor mode */ 383 u8 rx_tsf_addr_filter_config; /* for 8822B/8821C USE */ 384 BOOLEAN bSwChnl; 385 BOOLEAN bSetChnlBW; 386 BOOLEAN bSWToBW40M; 387 BOOLEAN bSWToBW80M; 388 BOOLEAN bChnlBWInitialized; 389 390 #ifdef CONFIG_RTW_ACS 391 struct auto_chan_sel acs; 392 #endif 393 #ifdef CONFIG_BCN_RECOVERY 394 u8 issue_bcn_fail; 395 #endif /*CONFIG_BCN_RECOVERY*/ 396 397 /****** rf_ctrl *****/ 398 u8 rf_chip; 399 400 u8 trx_path_bmp; /* [7:4]TX path bmp, [0:3]RX path bmp */ 401 u8 rf_type; /*enum rf_type , is RF_PATH - GET_HAL_RFPATH*/ 402 u8 NumTotalRFPath; /*GET_HAL_RFPATH_NUM*/ 403 u8 max_tx_cnt; 404 u8 tx_nss; /*tx Spatial Streams - GET_HAL_TX_NSS*/ 405 u8 rx_nss; /*rx Spatial Streams - GET_HAL_RX_NSS*/ 406 407 u8 PackageType; 408 u8 antenna_test; 409 410 /* runtime TRX path setting */ 411 enum bb_path txpath; /* TX path bmp */ 412 enum bb_path rxpath; /* RX path bmp */ 413 enum bb_path txpath_nss[4]; /* path bmp for NSS TX, [0] for 1SS, [3] for 4SS */ 414 u8 txpath_num_nss[4]; /* path num for NSS TX, [0] for 1SS, [3] for 4SS */ 415 416 /****** Debug ******/ 417 u16 ForcedDataRate; /* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */ 418 u8 bDumpRxPkt; 419 u8 bDumpTxPkt; 420 u8 dis_turboedca; /* 1: disable turboedca, 421 2: disable turboedca and setting EDCA parameter based on the input parameter*/ 422 u32 edca_param_mode; 423 424 /****** EEPROM setting.******/ 425 u8 bautoload_fail_flag; 426 u8 efuse_file_status; 427 u8 macaddr_file_status; 428 u8 EepromOrEfuse; 429 u8 efuse_eeprom_data[EEPROM_MAX_SIZE]; /*92C:256bytes, 88E:512bytes, we use union set (512bytes)*/ 430 u8 InterfaceSel; /* board type kept in eFuse */ 431 u16 CustomerID; 432 433 u16 EEPROMVID; 434 u16 EEPROMSVID; 435 #ifdef CONFIG_USB_HCI 436 u8 EEPROMUsbSwitch; 437 u16 EEPROMPID; 438 u16 EEPROMSDID; 439 #endif 440 #ifdef CONFIG_PCI_HCI 441 u16 EEPROMDID; 442 u16 EEPROMSMID; 443 #endif 444 445 u8 EEPROMCustomerID; 446 u8 EEPROMSubCustomerID; 447 u8 EEPROMVersion; 448 u8 EEPROMRegulatory; 449 u8 eeprom_thermal_meter; 450 u8 EEPROMBluetoothCoexist; 451 u8 EEPROMBluetoothType; 452 u8 EEPROMBluetoothAntNum; 453 u8 EEPROMBluetoothAntIsolation; 454 u8 EEPROMBluetoothRadioShared; 455 u8 EEPROMMACAddr[ETH_ALEN]; 456 457 u8 eeprom_trx_path_bmp; /* [7:4]TX path bmp, [0:3]RX path bmp. 0x00:not specified */ 458 u8 eeprom_max_tx_cnt; /* 0: not specified */ 459 460 u8 tx_bbswing_24G; 461 u8 tx_bbswing_5G; 462 u8 efuse0x3d7; /* efuse[0x3D7] */ 463 u8 efuse0x3d8; /* efuse[0x3D8] */ 464 465 #ifdef CONFIG_RF_POWER_TRIM 466 u8 EEPROMRFGainOffset; 467 u8 EEPROMRFGainVal; 468 struct kfree_data_t kfree_data; 469 #endif /*CONFIG_RF_POWER_TRIM*/ 470 471 #ifdef CONFIG_RTL8814A 472 u32 BackUp_BB_REG_4_2nd_CCA[3]; 473 #endif 474 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || \ 475 defined(CONFIG_RTL8723D) || \ 476 defined(CONFIG_RTL8192F) 477 478 u8 adjuseVoltageVal; 479 u8 need_restore; 480 #endif 481 u8 EfuseUsedPercentage; 482 u16 EfuseUsedBytes; 483 /*u8 EfuseMap[2][HWSET_MAX_SIZE_JAGUAR];*/ 484 EFUSE_HAL EfuseHal; 485 486 u8 txpwr_pg_mode; /* enum txpwr_pg_mode */ 487 488 /*---------------------------------------------------------------------------------*/ 489 #ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX 490 /* 2.4G TX power info for target TX power*/ 491 u8 Index24G_CCK_Base[MAX_RF_PATH][CENTER_CH_2G_NUM]; 492 u8 Index24G_BW40_Base[MAX_RF_PATH][CENTER_CH_2G_NUM]; 493 s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 494 s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 495 s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 496 s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 497 498 /* 5G TX power info for target TX power*/ 499 #if CONFIG_IEEE80211_BAND_5GHZ 500 u8 Index5G_BW40_Base[MAX_RF_PATH][CENTER_CH_5G_ALL_NUM]; 501 u8 Index5G_BW80_Base[MAX_RF_PATH][CENTER_CH_5G_80M_NUM]; 502 s8 OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 503 s8 BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 504 s8 BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 505 s8 BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 506 #endif 507 #endif /* CONFIG_TXPWR_PG_WITH_PWR_IDX */ 508 509 u8 txpwr_by_rate_undefined_band_path[TX_PWR_BY_RATE_NUM_BAND] 510 [TX_PWR_BY_RATE_NUM_RF]; 511 512 s8 TxPwrByRate[TX_PWR_BY_RATE_NUM_BAND] 513 [TX_PWR_BY_RATE_NUM_RF] 514 [TX_PWR_BY_RATE_NUM_RATE]; 515 516 /* Store the target power for each rate section and rf path */ 517 u8 target_txpwr_2g[TX_PWR_BY_RATE_NUM_RF] 518 [NUM_OF_TARGET_TXPWR_2G]; 519 u8 target_txpwr_5g[TX_PWR_BY_RATE_NUM_RF] 520 [NUM_OF_TARGET_TXPWR_5G]; 521 522 #if defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B) 523 u32 txagc_set_buf; 524 #endif 525 526 u8 txpwr_by_rate_loaded:1; 527 u8 txpwr_by_rate_from_file:1; 528 u8 txpwr_limit_loaded:1; 529 u8 txpwr_limit_from_file:1; 530 531 /* Read/write are allow for following hardware information variables */ 532 u8 crystal_cap; 533 534 u8 PAType_2G; 535 u8 PAType_5G; 536 u8 LNAType_2G; 537 u8 LNAType_5G; 538 u8 ExternalPA_2G; 539 u8 ExternalLNA_2G; 540 u8 external_pa_5g; 541 u8 external_lna_5g; 542 u16 TypeGLNA; 543 u16 TypeGPA; 544 u16 TypeALNA; 545 u16 TypeAPA; 546 u16 rfe_type; 547 548 u8 bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */ 549 u32 ac_param_be; /* Original parameter for BE, use for EDCA turbo. */ 550 u8 is_turbo_edca; 551 u8 prv_traffic_idx; 552 BB_REGISTER_DEFINITION_T PHYRegDef[MAX_RF_PATH]; /* Radio A/B/C/D */ 553 554 u32 RfRegChnlVal[MAX_RF_PATH]; 555 556 /* RDG enable */ 557 BOOLEAN bRDGEnable; 558 559 #if defined (CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) 560 u32 RegRRSR; 561 #endif 562 563 /****** antenna diversity ******/ 564 u8 AntDivCfg; 565 u8 with_extenal_ant_switch; 566 u8 b_fix_tx_ant; 567 u8 AntDetection; 568 u8 TRxAntDivType; 569 u8 ant_path; /* for 8723B s0/s1 selection */ 570 u32 antenna_tx_path; /* Antenna path Tx */ 571 u32 AntennaRxPath; /* Antenna path Rx */ 572 u8 sw_antdiv_bl_state; 573 574 /******** PHY DM & DM Section **********/ 575 _lock IQKSpinLock; 576 u8 INIDATA_RATE[MACID_NUM_SW_LIMIT]; 577 578 struct dm_struct odmpriv; 579 u64 bk_rf_ability; 580 u8 bIQKInitialized; 581 u8 bNeedIQK; 582 u8 neediqk_24g; 583 u8 IQK_MP_Switch; 584 u8 bScanInProcess; 585 /******** PHY DM & DM Section **********/ 586 587 588 589 /* 2010/08/09 MH Add CU power down mode. */ 590 BOOLEAN pwrdown; 591 592 #ifdef CONFIG_P2P 593 #ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP 594 u16 p2p_ps_offload; 595 #else 596 u8 p2p_ps_offload; 597 #endif 598 #endif 599 /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */ 600 u8 bMacPwrCtrlOn; 601 u8 hci_sus_state; 602 603 u8 RegIQKFWOffload; 604 struct submit_ctx iqk_sctx; 605 u8 ch_switch_offload; 606 struct submit_ctx chsw_sctx; 607 608 RT_AMPDU_BRUST AMPDUBurstMode; /* 92C maybe not use, but for compile successfully */ 609 610 u8 OutEpQueueSel; 611 u8 OutEpNumber; 612 613 #ifdef RTW_RX_AGGREGATION 614 RX_AGG_MODE rxagg_mode; 615 616 /* For RX Aggregation DMA Mode */ 617 u8 rxagg_dma_size; 618 u8 rxagg_dma_timeout; 619 #endif /* RTW_RX_AGGREGATION */ 620 621 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) 622 /* */ 623 /* For SDIO Interface HAL related */ 624 /* */ 625 626 /* */ 627 /* SDIO ISR Related */ 628 /* 629 * u32 IntrMask[1]; 630 * u32 IntrMaskToSet[1]; 631 * LOG_INTERRUPT InterruptLog; */ 632 u32 sdio_himr; 633 u32 sdio_hisr; 634 #ifndef RTW_HALMAC 635 /* */ 636 /* SDIO Tx FIFO related. */ 637 /* */ 638 /* HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg */ 639 #ifdef CONFIG_RTL8192F 640 u16 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE]; 641 #else 642 u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE]; 643 #endif/*CONFIG_RTL8192F*/ 644 #ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT 645 u8 sdio_avail_int_en_q; 646 #endif 647 _lock SdioTxFIFOFreePageLock; 648 u8 SdioTxOQTMaxFreeSpace; 649 u8 SdioTxOQTFreeSpace; 650 #else /* RTW_HALMAC */ 651 u16 SdioTxOQTFreeSpace; 652 #endif /* RTW_HALMAC */ 653 654 /* */ 655 /* SDIO Rx FIFO related. */ 656 /* */ 657 u8 SdioRxFIFOCnt; 658 #ifdef CONFIG_RTL8822C 659 u32 SdioRxFIFOSize; 660 #else 661 u16 SdioRxFIFOSize; 662 #endif 663 664 #ifndef RTW_HALMAC 665 u32 sdio_tx_max_len[SDIO_MAX_TX_QUEUE];/* H, N, L, used for sdio tx aggregation max length per queue */ 666 #else 667 #ifdef CONFIG_RTL8821C 668 u16 tx_high_page; 669 u16 tx_low_page; 670 u16 tx_normal_page; 671 u16 tx_extra_page; 672 u16 tx_pub_page; 673 u8 max_oqt_size; 674 #ifdef XMIT_BUF_SIZE 675 u32 max_xmit_size_vovi; 676 u32 max_xmit_size_bebk; 677 #endif /*XMIT_BUF_SIZE*/ 678 u16 max_xmit_page; 679 u16 max_xmit_page_vo; 680 u16 max_xmit_page_vi; 681 u16 max_xmit_page_be; 682 u16 max_xmit_page_bk; 683 684 #endif /*#ifdef CONFIG_RTL8821C*/ 685 #endif /* !RTW_HALMAC */ 686 #endif /* CONFIG_SDIO_HCI */ 687 688 #ifdef CONFIG_USB_HCI 689 690 /* 2010/12/10 MH Add for USB aggreation mode dynamic shceme. */ 691 BOOLEAN UsbRxHighSpeedMode; 692 BOOLEAN UsbTxVeryHighSpeedMode; 693 u32 UsbBulkOutSize; 694 BOOLEAN bSupportUSB3; 695 u8 usb_intf_start; 696 697 /* Interrupt relatd register information. */ 698 u32 IntArray[3];/* HISR0,HISR1,HSISR */ 699 u32 IntrMask[3]; 700 #ifdef CONFIG_USB_TX_AGGREGATION 701 u8 UsbTxAggMode; 702 u8 UsbTxAggDescNum; 703 #endif /* CONFIG_USB_TX_AGGREGATION */ 704 705 #ifdef CONFIG_USB_RX_AGGREGATION 706 u16 HwRxPageSize; /* Hardware setting */ 707 708 /* For RX Aggregation USB Mode */ 709 u8 rxagg_usb_size; 710 u8 rxagg_usb_timeout; 711 #endif/* CONFIG_USB_RX_AGGREGATION */ 712 #endif /* CONFIG_USB_HCI */ 713 714 715 #ifdef CONFIG_PCI_HCI 716 /* */ 717 /* EEPROM setting. */ 718 /* */ 719 u32 TransmitConfig; 720 u32 IntrMaskToSet[2]; 721 u32 IntArray[4]; 722 u32 IntrMask[4]; 723 u32 SysIntArray[1]; 724 u32 SysIntrMask[1]; 725 u32 IntrMaskReg[2]; 726 u32 IntrMaskDefault[4]; 727 728 u32 pci_backdoor_ctrl; 729 730 u8 bDefaultAntenna; 731 732 u8 bInterruptMigration; 733 u8 bDisableTxInt; 734 735 u16 RxTag; 736 #endif /* CONFIG_PCI_HCI */ 737 738 739 #ifdef DBG_CONFIG_ERROR_DETECT 740 struct sreset_priv srestpriv; 741 #endif /* #ifdef DBG_CONFIG_ERROR_DETECT */ 742 743 #ifdef CONFIG_BT_COEXIST 744 /* For bluetooth co-existance */ 745 BT_COEXIST bt_coexist; 746 #endif /* CONFIG_BT_COEXIST */ 747 748 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) \ 749 || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D)|| defined(CONFIG_RTL8192F) 750 #ifndef CONFIG_PCI_HCI /* mutual exclusive with PCI -- so they're SDIO and GSPI */ 751 /* Interrupt relatd register information. */ 752 u32 SysIntrStatus; 753 u32 SysIntrMask; 754 #endif 755 #endif /*endif CONFIG_RTL8723B */ 756 757 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE 758 char para_file_buf[MAX_PARA_FILE_BUF_LEN]; 759 char *mac_reg; 760 u32 mac_reg_len; 761 char *bb_phy_reg; 762 u32 bb_phy_reg_len; 763 char *bb_agc_tab; 764 u32 bb_agc_tab_len; 765 char *bb_phy_reg_pg; 766 u32 bb_phy_reg_pg_len; 767 char *bb_phy_reg_mp; 768 u32 bb_phy_reg_mp_len; 769 char *rf_radio_a; 770 u32 rf_radio_a_len; 771 char *rf_radio_b; 772 u32 rf_radio_b_len; 773 char *rf_tx_pwr_track; 774 u32 rf_tx_pwr_track_len; 775 char *rf_tx_pwr_lmt; 776 u32 rf_tx_pwr_lmt_len; 777 #endif 778 779 #ifdef CONFIG_BACKGROUND_NOISE_MONITOR 780 struct noise_monitor nm; 781 #endif 782 783 struct hal_spec_t hal_spec; 784 #ifdef CONFIG_PHY_CAPABILITY_QUERY 785 struct phy_spec_t phy_spec; 786 #endif 787 u8 RfKFreeEnable; 788 u8 RfKFree_ch_group; 789 BOOLEAN bCCKinCH14; 790 BB_INIT_REGISTER RegForRecover[5]; 791 792 #if defined(CONFIG_PCI_HCI) && defined(RTL8814AE_SW_BCN) 793 BOOLEAN bCorrectBCN; 794 #endif 795 #ifdef CONFIG_RTL8814A 796 u32 RxGainOffset[4]; /*{2G, 5G_Low, 5G_Middle, G_High}*/ 797 u8 BackUp_IG_REG_4_Chnl_Section[4]; /*{A,B,C,D}*/ 798 #endif 799 struct hal_iqk_reg_backup iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM]; 800 801 #ifdef RTW_HALMAC 802 u16 drv_rsvd_page_number; 803 #endif 804 805 #ifdef CONFIG_BEAMFORMING 806 u8 backup_snd_ptcl_ctrl; 807 #ifdef RTW_BEAMFORMING_VERSION_2 808 struct beamforming_info beamforming_info; 809 #endif /* RTW_BEAMFORMING_VERSION_2 */ 810 #endif /* CONFIG_BEAMFORMING */ 811 812 u8 not_xmitframe_fw_dl; /*not use xmitframe to download fw*/ 813 u8 phydm_op_mode; 814 815 u8 in_cta_test; 816 817 #ifdef CONFIG_RTW_LED 818 struct led_priv led; 819 #endif 820 /* for multi channel case (ex: MCC/TDLS) */ 821 u8 multi_ch_switch_mode; 822 823 #ifdef CONFIG_RTL8814B 824 u8 dma_ch_map[32]; /* TXDESC qsel maximum size */ 825 #endif 826 827 } HAL_DATA_COMMON, *PHAL_DATA_COMMON; 828 829 typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE; 830 #define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)(((struct _ADAPTER*)__pAdapter)->HalData)) 831 #define GET_HAL_SPEC(__pAdapter) (&(GET_HAL_DATA((__pAdapter))->hal_spec)) 832 #define adapter_to_led(adapter) (&(GET_HAL_DATA(adapter)->led)) 833 834 #define RT_GetInterfaceSelection(_Adapter) (GET_HAL_DATA(_Adapter)->InterfaceSel) 835 836 #define GET_KFREE_DATA(_adapter) (&(GET_HAL_DATA((_adapter))->kfree_data)) 837 838 #define SUPPORT_HW_RADIO_DETECT(Adapter) (RT_GetInterfaceSelection(Adapter) == INTF_SEL2_MINICARD || \ 839 RT_GetInterfaceSelection(Adapter) == INTF_SEL3_USB_Solo || \ 840 RT_GetInterfaceSelection(Adapter) == INTF_SEL4_USB_Combo) 841 842 #define get_hal_mac_addr(adapter) (GET_HAL_DATA(adapter)->EEPROMMACAddr) 843 #define is_boot_from_eeprom(adapter) (GET_HAL_DATA(adapter)->EepromOrEfuse) 844 #define rtw_get_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed) 845 #define rtw_set_hw_init_completed(adapter, cmp) (GET_HAL_DATA(adapter)->hw_init_completed = cmp) 846 #define rtw_is_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed == _TRUE) 847 848 /* refer to (hal_data->version_id.RFType / registrypriv->rf_path / 8814a from efuse or registrypriv)*/ 849 #define GET_HAL_RFPATH(adapter) (GET_HAL_DATA(adapter)->rf_type) 850 #define GET_HAL_RFPATH_NUM(adapter) (GET_HAL_DATA(adapter)->NumTotalRFPath) 851 #define GET_HAL_TX_PATH_BMP(adapter) ((GET_HAL_DATA(adapter)->trx_path_bmp & 0xF0) >> 4) 852 #define GET_HAL_RX_PATH_BMP(adapter) (GET_HAL_DATA(adapter)->trx_path_bmp & 0x0F) 853 854 /* refer to (registrypriv-> tx_nss,rx_nss / hal_spec->tx_nss_num,rx_nss_num)*/ 855 #define GET_HAL_TX_NSS(adapter) (GET_HAL_DATA(adapter)->tx_nss) 856 #define GET_HAL_RX_NSS(adapter) (GET_HAL_DATA(adapter)->rx_nss) 857 858 #endif 859 860 #ifdef RTW_HALMAC 861 int rtw_halmac_deinit_adapter(struct dvobj_priv *); 862 #endif /* RTW_HALMAC */ 863 864 #endif /* __HAL_DATA_H__ */ 865