1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 ************************************************************/
29
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 const u16 phy_rate_table[] = {
34 /*@20M*/
35 1, 2, 5, 11,
36 6, 9, 12, 18, 24, 36, 48, 54,
37 6, 13, 19, 26, 39, 52, 58, 65, /*@MCS0~7*/
38 13, 26, 39, 52, 78, 104, 117, 130, /*@MCS8~15*/
39 19, 39, 58, 78, 117, 156, 175, 195, /*@MCS16~23*/
40 26, 52, 78, 104, 156, 208, 234, 260, /*@MCS24~31*/
41 6, 13, 19, 26, 39, 52, 58, 65, 78, 90, /*@1ss MCS0~9*/
42 13, 26, 39, 52, 78, 104, 117, 130, 156, 180, /*@2ss MCS0~9*/
43 19, 39, 58, 78, 117, 156, 175, 195, 234, 260, /*@3ss MCS0~9*/
44 26, 52, 78, 104, 156, 208, 234, 260, 312, 360 /*@4ss MCS0~9*/
45 };
46
phydm_traffic_load_decision(void * dm_void)47 void phydm_traffic_load_decision(void *dm_void)
48 {
49 struct dm_struct *dm = (struct dm_struct *)dm_void;
50 u8 shift = 0;
51
52 /*@---TP & Trafic-load calculation---*/
53
54 if (dm->last_tx_ok_cnt > *dm->num_tx_bytes_unicast)
55 dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
56
57 if (dm->last_rx_ok_cnt > *dm->num_rx_bytes_unicast)
58 dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
59
60 dm->cur_tx_ok_cnt = *dm->num_tx_bytes_unicast - dm->last_tx_ok_cnt;
61 dm->cur_rx_ok_cnt = *dm->num_rx_bytes_unicast - dm->last_rx_ok_cnt;
62 dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
63 dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
64
65 /*@AP: <<3(8bit), >>20(10^6,M), >>0(1sec)*/
66 shift = 17 + (PHYDM_WATCH_DOG_PERIOD - 1);
67 /*@WIN&CE: <<3(8bit), >>20(10^6,M), >>1(2sec)*/
68
69 dm->tx_tp = (dm->tx_tp >> 1) + (u32)((dm->cur_tx_ok_cnt >> shift) >> 1);
70 dm->rx_tp = (dm->rx_tp >> 1) + (u32)((dm->cur_rx_ok_cnt >> shift) >> 1);
71
72 dm->total_tp = dm->tx_tp + dm->rx_tp;
73
74 /*@[Calculate TX/RX state]*/
75 if (dm->tx_tp > (dm->rx_tp << 1))
76 dm->txrx_state_all = TX_STATE;
77 else if (dm->rx_tp > (dm->tx_tp << 1))
78 dm->txrx_state_all = RX_STATE;
79 else
80 dm->txrx_state_all = BI_DIRECTION_STATE;
81
82 /*@[Traffic load decision]*/
83 dm->pre_traffic_load = dm->traffic_load;
84
85 if (dm->cur_tx_ok_cnt > 1875000 || dm->cur_rx_ok_cnt > 1875000) {
86 /* @( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/
87 dm->traffic_load = TRAFFIC_HIGH;
88 } else if (dm->cur_tx_ok_cnt > 500000 || dm->cur_rx_ok_cnt > 500000) {
89 /*@( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/
90 dm->traffic_load = TRAFFIC_MID;
91 } else if (dm->cur_tx_ok_cnt > 100000 || dm->cur_rx_ok_cnt > 100000) {
92 /*@( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/
93 dm->traffic_load = TRAFFIC_LOW;
94 } else if (dm->cur_tx_ok_cnt > 25000 || dm->cur_rx_ok_cnt > 25000) {
95 /*@( 0.025M * 8bit ) / 2sec = 0.1M bits /sec )*/
96 dm->traffic_load = TRAFFIC_ULTRA_LOW;
97 } else {
98 dm->traffic_load = TRAFFIC_NO_TP;
99 }
100
101 /*@[Calculate consecutive idlel time]*/
102 if (dm->traffic_load == 0)
103 dm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD;
104 else
105 dm->consecutive_idlel_time = 0;
106
107 #if 0
108 PHYDM_DBG(dm, DBG_COMMON_FLOW,
109 "cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n",
110 dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt, dm->last_tx_ok_cnt,
111 dm->last_rx_ok_cnt);
112
113 PHYDM_DBG(dm, DBG_COMMON_FLOW, "tx_tp = %d, rx_tp = %d\n", dm->tx_tp,
114 dm->rx_tp);
115 #endif
116 }
117
phydm_cck_new_agc_chk(struct dm_struct * dm)118 void phydm_cck_new_agc_chk(struct dm_struct *dm)
119 {
120 u32 new_agc_addr = 0x0;
121
122 dm->cck_new_agc = false;
123 #if (RTL8723D_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT ||\
124 RTL8197F_SUPPORT || RTL8710B_SUPPORT || RTL8192F_SUPPORT ||\
125 RTL8195B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\
126 RTL8721D_SUPPORT || RTL8710C_SUPPORT)
127 if (dm->support_ic_type & (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8821C |
128 ODM_RTL8197F | ODM_RTL8710B | ODM_RTL8192F | ODM_RTL8195B |
129 ODM_RTL8721D | ODM_RTL8710C)) {
130 new_agc_addr = R_0xa9c;
131 } else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C |
132 ODM_RTL8814B | ODM_RTL8197G)) {
133 new_agc_addr = R_0x1a9c;
134 }
135
136 /*@1: new agc 0: old agc*/
137 dm->cck_new_agc = (boolean)odm_get_bb_reg(dm, new_agc_addr, BIT(17));
138 #endif
139 }
140
141 /*select 3 or 4 bit LNA */
phydm_cck_lna_bit_num_chk(struct dm_struct * dm)142 void phydm_cck_lna_bit_num_chk(struct dm_struct *dm)
143 {
144 boolean report_type = 0;
145 #if (RTL8192E_SUPPORT)
146 u32 value_824, value_82c;
147 #endif
148
149 #if (RTL8192E_SUPPORT)
150 if (dm->support_ic_type & (ODM_RTL8192E)) {
151 /* @0x824[9] = 0x82C[9] = 0xA80[7] those registers setting
152 * should be equal or CCK RSSI report may be incorrect
153 */
154 value_824 = odm_get_bb_reg(dm, R_0x824, BIT(9));
155 value_82c = odm_get_bb_reg(dm, R_0x82c, BIT(9));
156
157 if (value_824 != value_82c)
158 odm_set_bb_reg(dm, R_0x82c, BIT(9), value_824);
159 odm_set_bb_reg(dm, R_0xa80, BIT(7), value_824);
160 report_type = (boolean)value_824;
161 }
162 #endif
163
164 #if (RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8710B_SUPPORT)
165 if (dm->support_ic_type &
166 (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
167 report_type = (boolean)odm_get_bb_reg(dm, R_0x950, BIT(11));
168
169 if (report_type != 1)
170 pr_debug("[Warning] CCK should be 4bit LNA\n");
171 }
172 #endif
173
174 #if (RTL8821C_SUPPORT)
175 if (dm->support_ic_type & ODM_RTL8821C) {
176 if (dm->default_rf_set_8821c == SWITCH_TO_BTG)
177 report_type = 1;
178 }
179 #endif
180
181 dm->cck_agc_report_type = report_type;
182
183 PHYDM_DBG(dm, ODM_COMP_INIT, "cck_agc_report_type=((%d))\n",
184 dm->cck_agc_report_type);
185 }
186
phydm_init_cck_setting(struct dm_struct * dm)187 void phydm_init_cck_setting(struct dm_struct *dm)
188 {
189 u32 reg_tmp = 0;
190 u32 mask_tmp = 0;
191
192 phydm_cck_new_agc_chk(dm);
193
194 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
195 return;
196
197 reg_tmp = ODM_REG(CCK_RPT_FORMAT, dm);
198 mask_tmp = ODM_BIT(CCK_RPT_FORMAT, dm);
199 dm->is_cck_high_power = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
200
201 PHYDM_DBG(dm, ODM_COMP_INIT, "ext_lna_gain=((%d))\n", dm->ext_lna_gain);
202
203 phydm_config_cck_rx_antenna_init(dm);
204
205 if (dm->support_ic_type & ODM_RTL8192F)
206 phydm_config_cck_rx_path(dm, BB_PATH_AB);
207 else if (dm->valid_path_set == BB_PATH_A)
208 phydm_config_cck_rx_path(dm, BB_PATH_A);
209 else if (dm->valid_path_set == BB_PATH_B)
210 phydm_config_cck_rx_path(dm, BB_PATH_B);
211
212 phydm_cck_lna_bit_num_chk(dm);
213 phydm_get_cck_rssi_table_from_reg(dm);
214 }
215
216 #ifdef CONFIG_RFE_BY_HW_INFO
phydm_init_hw_info_by_rfe(struct dm_struct * dm)217 void phydm_init_hw_info_by_rfe(struct dm_struct *dm)
218 {
219 #if (RTL8821C_SUPPORT)
220 if (dm->support_ic_type & ODM_RTL8821C)
221 phydm_init_hw_info_by_rfe_type_8821c(dm);
222 #endif
223 #if (RTL8197F_SUPPORT)
224 if (dm->support_ic_type & ODM_RTL8197F)
225 phydm_init_hw_info_by_rfe_type_8197f(dm);
226 #endif
227 #if (RTL8814B_SUPPORT)
228 if (dm->support_ic_type & ODM_RTL8814B)
229 phydm_init_hw_info_by_rfe_type_8814b(dm);
230 #endif
231 }
232 #endif
233
phydm_common_info_self_init(struct dm_struct * dm)234 void phydm_common_info_self_init(struct dm_struct *dm)
235 {
236 u32 reg_tmp = 0;
237 u32 mask_tmp = 0;
238
239 dm->run_in_drv_fw = RUN_IN_DRIVER;
240
241 /*@BB IP Generation*/
242 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
243 dm->ic_ip_series = PHYDM_IC_JGR3;
244 else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
245 dm->ic_ip_series = PHYDM_IC_AC;
246 else if (dm->support_ic_type & ODM_IC_11N_SERIES)
247 dm->ic_ip_series = PHYDM_IC_N;
248
249 /*@BB phy-status Generation*/
250 if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC)
251 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_3;
252 else if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC)
253 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_2;
254 else
255 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_1;
256
257 phydm_init_cck_setting(dm);
258
259 reg_tmp = ODM_REG(BB_RX_PATH, dm);
260 mask_tmp = ODM_BIT(BB_RX_PATH, dm);
261 dm->rf_path_rx_enable = (u8)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
262 #if (DM_ODM_SUPPORT_TYPE != ODM_CE)
263 dm->is_net_closed = &dm->BOOLEAN_temp;
264
265 phydm_init_debug_setting(dm);
266 #endif
267 phydm_init_soft_ml_setting(dm);
268
269 dm->phydm_sys_up_time = 0;
270
271 if (dm->support_ic_type & ODM_IC_1SS)
272 dm->num_rf_path = 1;
273 else if (dm->support_ic_type & ODM_IC_2SS)
274 dm->num_rf_path = 2;
275 #if 0
276 /* @RTK do not has IC which is equipped with 3 RF paths,
277 * so ODM_IC_3SS is an enpty macro and result in coverity check errors
278 */
279 else if (dm->support_ic_type & ODM_IC_3SS)
280 dm->num_rf_path = 3;
281 #endif
282 else if (dm->support_ic_type & ODM_IC_4SS)
283 dm->num_rf_path = 4;
284 else
285 dm->num_rf_path = 1;
286
287 phydm_trx_antenna_setting_init(dm, dm->num_rf_path);
288
289 dm->tx_rate = 0xFF;
290 dm->rssi_min_by_path = 0xFF;
291
292 dm->number_linked_client = 0;
293 dm->pre_number_linked_client = 0;
294 dm->number_active_client = 0;
295 dm->pre_number_active_client = 0;
296
297 dm->last_tx_ok_cnt = 0;
298 dm->last_rx_ok_cnt = 0;
299 dm->tx_tp = 0;
300 dm->rx_tp = 0;
301 dm->total_tp = 0;
302 dm->traffic_load = TRAFFIC_LOW;
303
304 dm->nbi_set_result = 0;
305 dm->is_init_hw_info_by_rfe = false;
306 dm->pre_dbg_priority = DBGPORT_RELEASE;
307 dm->tp_active_th = 5;
308 dm->disable_phydm_watchdog = 0;
309
310 dm->u8_dummy = 0xf;
311 dm->u16_dummy = 0xffff;
312 dm->u32_dummy = 0xffffffff;
313
314 dm->pause_lv_table.lv_cckpd = PHYDM_PAUSE_RELEASE;
315 dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
316 dm->pre_is_linked = false;
317 dm->is_linked = false;
318 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
319 if (!(dm->is_fcs_mode_enable)) {
320 dm->is_fcs_mode_enable = &dm->boolean_dummy;
321 pr_debug("[Warning] is_fcs_mode_enable=NULL\n");
322 }
323 #endif
324 }
325
phydm_cmn_sta_info_update(void * dm_void,u8 macid)326 void phydm_cmn_sta_info_update(void *dm_void, u8 macid)
327 {
328 struct dm_struct *dm = (struct dm_struct *)dm_void;
329 struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
330 struct ra_sta_info *ra = NULL;
331
332 if (is_sta_active(sta)) {
333 ra = &sta->ra_info;
334 } else {
335 PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid sta_info\n",
336 __func__);
337 return;
338 }
339
340 PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
341 PHYDM_DBG(dm, DBG_RA_MASK, "MACID=%d\n", sta->mac_id);
342
343 /*@[Calculate TX/RX state]*/
344 if (sta->tx_moving_average_tp > (sta->rx_moving_average_tp << 1))
345 ra->txrx_state = TX_STATE;
346 else if (sta->rx_moving_average_tp > (sta->tx_moving_average_tp << 1))
347 ra->txrx_state = RX_STATE;
348 else
349 ra->txrx_state = BI_DIRECTION_STATE;
350
351 ra->is_noisy = dm->noisy_decision;
352 }
353
phydm_common_info_self_update(struct dm_struct * dm)354 void phydm_common_info_self_update(struct dm_struct *dm)
355 {
356 u8 sta_cnt = 0, num_active_client = 0;
357 u32 i, one_entry_macid = 0;
358 u32 ma_rx_tp = 0;
359 u32 tp_diff = 0;
360 struct cmn_sta_info *sta;
361 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
362 PADAPTER adapter = (PADAPTER)dm->adapter;
363 PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
364
365 sta = dm->phydm_sta_info[0];
366
367 #if 0
368 if (mgnt_info->mAssoc) {
369 sta->dm_ctrl |= STA_DM_CTRL_ACTIVE;
370 for (i = 0; i < 6; i++)
371 sta->mac_addr[i] = mgnt_info->Bssid[i];
372 } else if (GetFirstClientPort(adapter)) {
373 struct _ADAPTER *client_adapter = GetFirstClientPort(adapter);
374
375 sta->dm_ctrl |= STA_DM_CTRL_ACTIVE;
376 for (i = 0; i < 6; i++)
377 sta->mac_addr[i] = client_adapter->MgntInfo.Bssid[i];
378 } else {
379 sta->dm_ctrl = sta->dm_ctrl & (~STA_DM_CTRL_ACTIVE);
380 for (i = 0; i < 6; i++)
381 sta->mac_addr[i] = 0;
382 }
383 #endif
384
385 /* STA mode is linked to AP */
386 if (is_sta_active(sta) && !ACTING_AS_AP(adapter))
387 dm->bsta_state = true;
388 else
389 dm->bsta_state = false;
390 #endif
391
392 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
393 sta = dm->phydm_sta_info[i];
394 if (is_sta_active(sta)) {
395 sta_cnt++;
396
397 if (sta_cnt == 1)
398 one_entry_macid = i;
399
400 phydm_cmn_sta_info_update(dm, (u8)i);
401 #ifdef PHYDM_BEAMFORMING_SUPPORT
402 /*@phydm_get_txbf_device_num(dm, (u8)i);*/
403 #endif
404
405 ma_rx_tp = sta->rx_moving_average_tp +
406 sta->tx_moving_average_tp;
407
408 PHYDM_DBG(dm, DBG_COMMON_FLOW,
409 "TP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp);
410
411 if (ma_rx_tp > ACTIVE_TP_THRESHOLD)
412 num_active_client++;
413 }
414 }
415
416 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
417 dm->is_linked = (sta_cnt != 0) ? true : false;
418 #endif
419
420 if (sta_cnt == 1) {
421 dm->is_one_entry_only = true;
422 dm->one_entry_macid = one_entry_macid;
423 dm->one_entry_tp = ma_rx_tp;
424
425 dm->tp_active_occur = 0;
426
427 PHYDM_DBG(dm, DBG_COMMON_FLOW,
428 "one_entry_tp=((%d)), pre_one_entry_tp=((%d))\n",
429 dm->one_entry_tp, dm->pre_one_entry_tp);
430
431 if (dm->one_entry_tp > dm->pre_one_entry_tp &&
432 dm->pre_one_entry_tp <= 2) {
433 tp_diff = dm->one_entry_tp - dm->pre_one_entry_tp;
434
435 if (tp_diff > dm->tp_active_th)
436 dm->tp_active_occur = 1;
437 }
438 dm->pre_one_entry_tp = dm->one_entry_tp;
439 } else {
440 dm->is_one_entry_only = false;
441 }
442
443 dm->pre_number_linked_client = dm->number_linked_client;
444 dm->pre_number_active_client = dm->number_active_client;
445
446 dm->number_linked_client = sta_cnt;
447 dm->number_active_client = num_active_client;
448
449 /*Traffic load information update*/
450 phydm_traffic_load_decision(dm);
451
452 dm->phydm_sys_up_time += PHYDM_WATCH_DOG_PERIOD;
453
454 dm->is_dfs_band = phydm_is_dfs_band(dm);
455 dm->phy_dbg_info.show_phy_sts_cnt = 0;
456
457 /*[Link Status Check]*/
458 dm->first_connect = dm->is_linked && !dm->pre_is_linked;
459 dm->first_disconnect = !dm->is_linked && dm->pre_is_linked;
460 dm->pre_is_linked = dm->is_linked;
461 }
462
phydm_common_info_self_reset(struct dm_struct * dm)463 void phydm_common_info_self_reset(struct dm_struct *dm)
464 {
465 struct odm_phy_dbg_info *dbg_t = &dm->phy_dbg_info;
466
467 dbg_t->beacon_cnt_in_period = dbg_t->num_qry_beacon_pkt;
468 dbg_t->num_qry_beacon_pkt = 0;
469
470 dm->rxsc_l = 0xff;
471 dm->rxsc_20 = 0xff;
472 dm->rxsc_40 = 0xff;
473 dm->rxsc_80 = 0xff;
474 }
475
476 void *
phydm_get_structure(struct dm_struct * dm,u8 structure_type)477 phydm_get_structure(struct dm_struct *dm, u8 structure_type)
478
479 {
480 void *structure = NULL;
481
482 switch (structure_type) {
483 case PHYDM_FALSEALMCNT:
484 structure = &dm->false_alm_cnt;
485 break;
486
487 case PHYDM_CFOTRACK:
488 structure = &dm->dm_cfo_track;
489 break;
490
491 case PHYDM_ADAPTIVITY:
492 structure = &dm->adaptivity;
493 break;
494
495 case PHYDM_DFS:
496 structure = &dm->dfs;
497 break;
498
499 default:
500 break;
501 }
502
503 return structure;
504 }
505
phydm_phy_info_update(struct dm_struct * dm)506 void phydm_phy_info_update(struct dm_struct *dm)
507 {
508 #if (RTL8822B_SUPPORT)
509 if (dm->support_ic_type == ODM_RTL8822B)
510 dm->phy_dbg_info.condi_num = phydm_get_condi_num_8822b(dm);
511 #endif
512 }
513
phydm_hw_setting(struct dm_struct * dm)514 void phydm_hw_setting(struct dm_struct *dm)
515 {
516 #if (RTL8821A_SUPPORT)
517 if (dm->support_ic_type & ODM_RTL8821)
518 odm_hw_setting_8821a(dm);
519 #endif
520
521 #if (RTL8814A_SUPPORT)
522 if (dm->support_ic_type & ODM_RTL8814A)
523 phydm_hwsetting_8814a(dm);
524 #endif
525
526 #if (RTL8822B_SUPPORT)
527 if (dm->support_ic_type & ODM_RTL8822B)
528 phydm_hwsetting_8822b(dm);
529 #endif
530
531 #if (RTL8812A_SUPPORT)
532 if (dm->support_ic_type & ODM_RTL8812)
533 phydm_hwsetting_8812a(dm);
534 #endif
535
536 #if (RTL8197F_SUPPORT)
537 if (dm->support_ic_type & ODM_RTL8197F)
538 phydm_hwsetting_8197f(dm);
539 #endif
540
541 #if (RTL8192F_SUPPORT)
542 if (dm->support_ic_type & ODM_RTL8192F)
543 phydm_hwsetting_8192f(dm);
544 #endif
545
546 #if (RTL8822C_SUPPORT)
547 if (dm->support_ic_type & ODM_RTL8822C)
548 phydm_hwsetting_8822c(dm);
549 #endif
550
551 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
552 phydm_cck_rx_pathdiv_watchdog(dm);
553 #endif
554 }
555
556 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
phydm_supportability_init_win(void * dm_void)557 u64 phydm_supportability_init_win(
558 void *dm_void)
559 {
560 struct dm_struct *dm = (struct dm_struct *)dm_void;
561 u64 support_ability = 0;
562
563 switch (dm->support_ic_type) {
564 /*@---------------N Series--------------------*/
565 #if (RTL8188E_SUPPORT)
566 case ODM_RTL8188E:
567 support_ability |=
568 ODM_BB_DIG |
569 ODM_BB_RA_MASK |
570 /*ODM_BB_DYNAMIC_TXPWR |*/
571 ODM_BB_FA_CNT |
572 ODM_BB_RSSI_MONITOR |
573 ODM_BB_CCK_PD |
574 /*ODM_BB_PWR_TRAIN |*/
575 ODM_BB_RATE_ADAPTIVE |
576 ODM_BB_ADAPTIVITY |
577 ODM_BB_CFO_TRACKING |
578 ODM_BB_ENV_MONITOR |
579 ODM_BB_PRIMARY_CCA;
580 break;
581 #endif
582
583 #if (RTL8192E_SUPPORT)
584 case ODM_RTL8192E:
585 support_ability |=
586 ODM_BB_DIG |
587 ODM_BB_RA_MASK |
588 /*ODM_BB_DYNAMIC_TXPWR |*/
589 ODM_BB_FA_CNT |
590 ODM_BB_RSSI_MONITOR |
591 ODM_BB_CCK_PD |
592 /*ODM_BB_PWR_TRAIN |*/
593 ODM_BB_RATE_ADAPTIVE |
594 ODM_BB_ADAPTIVITY |
595 ODM_BB_CFO_TRACKING |
596 ODM_BB_ENV_MONITOR |
597 ODM_BB_PRIMARY_CCA;
598 break;
599 #endif
600
601 #if (RTL8723B_SUPPORT)
602 case ODM_RTL8723B:
603 support_ability |=
604 ODM_BB_DIG |
605 ODM_BB_RA_MASK |
606 /*ODM_BB_DYNAMIC_TXPWR |*/
607 ODM_BB_FA_CNT |
608 ODM_BB_RSSI_MONITOR |
609 ODM_BB_CCK_PD |
610 /*ODM_BB_PWR_TRAIN |*/
611 ODM_BB_RATE_ADAPTIVE |
612 ODM_BB_ADAPTIVITY |
613 ODM_BB_CFO_TRACKING |
614 ODM_BB_ENV_MONITOR |
615 ODM_BB_PRIMARY_CCA;
616 break;
617 #endif
618
619 #if (RTL8703B_SUPPORT)
620 case ODM_RTL8703B:
621 support_ability |=
622 ODM_BB_DIG |
623 ODM_BB_RA_MASK |
624 /*ODM_BB_DYNAMIC_TXPWR |*/
625 ODM_BB_FA_CNT |
626 ODM_BB_RSSI_MONITOR |
627 ODM_BB_CCK_PD |
628 /*ODM_BB_PWR_TRAIN |*/
629 ODM_BB_RATE_ADAPTIVE |
630 ODM_BB_ADAPTIVITY |
631 ODM_BB_CFO_TRACKING |
632 ODM_BB_ENV_MONITOR;
633 break;
634 #endif
635
636 #if (RTL8723D_SUPPORT)
637 case ODM_RTL8723D:
638 support_ability |=
639 ODM_BB_DIG |
640 ODM_BB_RA_MASK |
641 /*ODM_BB_DYNAMIC_TXPWR |*/
642 ODM_BB_FA_CNT |
643 ODM_BB_RSSI_MONITOR |
644 ODM_BB_CCK_PD |
645 ODM_BB_PWR_TRAIN |
646 ODM_BB_RATE_ADAPTIVE |
647 ODM_BB_ADAPTIVITY |
648 ODM_BB_CFO_TRACKING |
649 ODM_BB_ENV_MONITOR;
650 break;
651 #endif
652
653 #if (RTL8710B_SUPPORT)
654 case ODM_RTL8710B:
655 support_ability |=
656 ODM_BB_DIG |
657 ODM_BB_RA_MASK |
658 /*ODM_BB_DYNAMIC_TXPWR |*/
659 ODM_BB_FA_CNT |
660 ODM_BB_RSSI_MONITOR |
661 ODM_BB_CCK_PD |
662 ODM_BB_PWR_TRAIN |
663 ODM_BB_RATE_ADAPTIVE |
664 ODM_BB_ADAPTIVITY |
665 ODM_BB_CFO_TRACKING |
666 ODM_BB_ENV_MONITOR;
667 break;
668 #endif
669
670 #if (RTL8188F_SUPPORT)
671 case ODM_RTL8188F:
672 support_ability |=
673 ODM_BB_DIG |
674 ODM_BB_RA_MASK |
675 /*ODM_BB_DYNAMIC_TXPWR |*/
676 ODM_BB_FA_CNT |
677 ODM_BB_RSSI_MONITOR |
678 ODM_BB_CCK_PD |
679 /*ODM_BB_PWR_TRAIN |*/
680 ODM_BB_RATE_ADAPTIVE |
681 ODM_BB_ADAPTIVITY |
682 ODM_BB_CFO_TRACKING |
683 ODM_BB_ENV_MONITOR;
684 break;
685 #endif
686
687 #if (RTL8192F_SUPPORT)
688 case ODM_RTL8192F:
689 support_ability |=
690 ODM_BB_DIG |
691 ODM_BB_RA_MASK |
692 ODM_BB_FA_CNT |
693 ODM_BB_RSSI_MONITOR |
694 ODM_BB_CCK_PD |
695 ODM_BB_PWR_TRAIN |
696 ODM_BB_RATE_ADAPTIVE |
697 /*ODM_BB_PATH_DIV |*/
698 ODM_BB_ADAPTIVITY |
699 ODM_BB_CFO_TRACKING |
700 ODM_BB_ADAPTIVE_SOML |
701 ODM_BB_ENV_MONITOR;
702 /*ODM_BB_LNA_SAT_CHK |*/
703 /*ODM_BB_PRIMARY_CCA*/
704
705 break;
706 #endif
707
708 /*@---------------AC Series-------------------*/
709
710 #if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
711 case ODM_RTL8812:
712 case ODM_RTL8821:
713 support_ability |=
714 ODM_BB_DIG |
715 ODM_BB_RA_MASK |
716 ODM_BB_DYNAMIC_TXPWR |
717 ODM_BB_FA_CNT |
718 ODM_BB_RSSI_MONITOR |
719 ODM_BB_CCK_PD |
720 /*ODM_BB_PWR_TRAIN |*/
721 ODM_BB_RATE_ADAPTIVE |
722 ODM_BB_ADAPTIVITY |
723 ODM_BB_CFO_TRACKING |
724 ODM_BB_ENV_MONITOR;
725 break;
726 #endif
727
728 #if (RTL8814A_SUPPORT)
729 case ODM_RTL8814A:
730 support_ability |=
731 ODM_BB_DIG |
732 ODM_BB_RA_MASK |
733 ODM_BB_DYNAMIC_TXPWR |
734 ODM_BB_FA_CNT |
735 ODM_BB_RSSI_MONITOR |
736 ODM_BB_CCK_PD |
737 /*ODM_BB_PWR_TRAIN |*/
738 ODM_BB_RATE_ADAPTIVE |
739 ODM_BB_ADAPTIVITY |
740 ODM_BB_CFO_TRACKING |
741 ODM_BB_ENV_MONITOR;
742 break;
743 #endif
744
745 #if (RTL8822B_SUPPORT)
746 case ODM_RTL8822B:
747 support_ability |=
748 ODM_BB_DIG |
749 ODM_BB_RA_MASK |
750 /*ODM_BB_DYNAMIC_TXPWR |*/
751 ODM_BB_FA_CNT |
752 ODM_BB_RSSI_MONITOR |
753 ODM_BB_CCK_PD |
754 /*ODM_BB_PWR_TRAIN |*/
755 /*ODM_BB_ADAPTIVE_SOML |*/
756 ODM_BB_RATE_ADAPTIVE |
757 /*ODM_BB_PATH_DIV |*/
758 ODM_BB_ADAPTIVITY |
759 ODM_BB_CFO_TRACKING |
760 ODM_BB_ENV_MONITOR;
761 break;
762 #endif
763
764 #if (RTL8821C_SUPPORT)
765 case ODM_RTL8821C:
766 support_ability |=
767 ODM_BB_DIG |
768 ODM_BB_RA_MASK |
769 /*ODM_BB_DYNAMIC_TXPWR |*/
770 ODM_BB_FA_CNT |
771 ODM_BB_RSSI_MONITOR |
772 ODM_BB_CCK_PD |
773 /*ODM_BB_PWR_TRAIN |*/
774 ODM_BB_RATE_ADAPTIVE |
775 ODM_BB_ADAPTIVITY |
776 ODM_BB_CFO_TRACKING |
777 ODM_BB_ENV_MONITOR;
778 break;
779 #endif
780
781 /*@---------------JGR3 Series-------------------*/
782
783 #if (RTL8822C_SUPPORT)
784 case ODM_RTL8822C:
785 support_ability |=
786 ODM_BB_DIG |
787 ODM_BB_RA_MASK |
788 /* ODM_BB_DYNAMIC_TXPWR |*/
789 ODM_BB_FA_CNT |
790 ODM_BB_RSSI_MONITOR |
791 ODM_BB_CCK_PD |
792 ODM_BB_RATE_ADAPTIVE |
793 ODM_BB_PATH_DIV |
794 ODM_BB_ADAPTIVITY |
795 ODM_BB_CFO_TRACKING |
796 ODM_BB_ENV_MONITOR;
797 break;
798 #endif
799
800 #if (RTL8814B_SUPPORT)
801 case ODM_RTL8814B:
802 support_ability |=
803 ODM_BB_DIG |
804 ODM_BB_RA_MASK |
805 /*ODM_BB_DYNAMIC_TXPWR |*/
806 ODM_BB_FA_CNT |
807 ODM_BB_RSSI_MONITOR |
808 ODM_BB_CCK_PD |
809 /*ODM_BB_PWR_TRAIN |*/
810 ODM_BB_RATE_ADAPTIVE |
811 ODM_BB_ADAPTIVITY |
812 ODM_BB_CFO_TRACKING;
813 /*ODM_BB_ENV_MONITOR;*/
814 break;
815 #endif
816
817 default:
818 support_ability |=
819 ODM_BB_DIG |
820 ODM_BB_RA_MASK |
821 /*ODM_BB_DYNAMIC_TXPWR |*/
822 ODM_BB_FA_CNT |
823 ODM_BB_RSSI_MONITOR |
824 ODM_BB_CCK_PD |
825 /*ODM_BB_PWR_TRAIN |*/
826 ODM_BB_RATE_ADAPTIVE |
827 ODM_BB_ADAPTIVITY |
828 ODM_BB_CFO_TRACKING |
829 ODM_BB_ENV_MONITOR;
830
831 pr_debug("[Warning] Supportability Init Warning !!!\n");
832 break;
833 }
834
835 return support_ability;
836 }
837 #endif
838
839 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
phydm_supportability_init_ce(void * dm_void)840 u64 phydm_supportability_init_ce(void *dm_void)
841 {
842 struct dm_struct *dm = (struct dm_struct *)dm_void;
843 u64 support_ability = 0;
844
845 switch (dm->support_ic_type) {
846 /*@---------------N Series--------------------*/
847 #if (RTL8188E_SUPPORT)
848 case ODM_RTL8188E:
849 support_ability |=
850 ODM_BB_DIG |
851 ODM_BB_RA_MASK |
852 /*@ODM_BB_DYNAMIC_TXPWR |*/
853 ODM_BB_FA_CNT |
854 ODM_BB_RSSI_MONITOR |
855 ODM_BB_CCK_PD |
856 /*@ODM_BB_PWR_TRAIN |*/
857 ODM_BB_RATE_ADAPTIVE |
858 ODM_BB_ADAPTIVITY |
859 ODM_BB_CFO_TRACKING |
860 ODM_BB_ENV_MONITOR |
861 ODM_BB_PRIMARY_CCA;
862 break;
863 #endif
864
865 #if (RTL8192E_SUPPORT)
866 case ODM_RTL8192E:
867 support_ability |=
868 ODM_BB_DIG |
869 ODM_BB_RA_MASK |
870 /*@ODM_BB_DYNAMIC_TXPWR |*/
871 ODM_BB_FA_CNT |
872 ODM_BB_RSSI_MONITOR |
873 ODM_BB_CCK_PD |
874 /*@ODM_BB_PWR_TRAIN |*/
875 ODM_BB_RATE_ADAPTIVE |
876 ODM_BB_ADAPTIVITY |
877 ODM_BB_CFO_TRACKING |
878 ODM_BB_ENV_MONITOR |
879 ODM_BB_PRIMARY_CCA;
880 break;
881 #endif
882
883 #if (RTL8723B_SUPPORT)
884 case ODM_RTL8723B:
885 support_ability |=
886 ODM_BB_DIG |
887 ODM_BB_RA_MASK |
888 /*@ODM_BB_DYNAMIC_TXPWR |*/
889 ODM_BB_FA_CNT |
890 ODM_BB_RSSI_MONITOR |
891 ODM_BB_CCK_PD |
892 /*@ODM_BB_PWR_TRAIN |*/
893 ODM_BB_RATE_ADAPTIVE |
894 ODM_BB_ADAPTIVITY |
895 ODM_BB_CFO_TRACKING |
896 ODM_BB_ENV_MONITOR |
897 ODM_BB_PRIMARY_CCA;
898 break;
899 #endif
900
901 #if (RTL8703B_SUPPORT)
902 case ODM_RTL8703B:
903 support_ability |=
904 ODM_BB_DIG |
905 ODM_BB_RA_MASK |
906 /*@ODM_BB_DYNAMIC_TXPWR |*/
907 ODM_BB_FA_CNT |
908 ODM_BB_RSSI_MONITOR |
909 ODM_BB_CCK_PD |
910 /*@ODM_BB_PWR_TRAIN |*/
911 ODM_BB_RATE_ADAPTIVE |
912 ODM_BB_ADAPTIVITY |
913 ODM_BB_CFO_TRACKING |
914 ODM_BB_ENV_MONITOR;
915 break;
916 #endif
917
918 #if (RTL8723D_SUPPORT)
919 case ODM_RTL8723D:
920 support_ability |=
921 ODM_BB_DIG |
922 ODM_BB_RA_MASK |
923 /*@ODM_BB_DYNAMIC_TXPWR |*/
924 ODM_BB_FA_CNT |
925 ODM_BB_RSSI_MONITOR |
926 ODM_BB_CCK_PD |
927 ODM_BB_PWR_TRAIN |
928 ODM_BB_RATE_ADAPTIVE |
929 ODM_BB_ADAPTIVITY |
930 ODM_BB_CFO_TRACKING |
931 ODM_BB_ENV_MONITOR;
932 break;
933 #endif
934
935 #if (RTL8710B_SUPPORT)
936 case ODM_RTL8710B:
937 support_ability |=
938 ODM_BB_DIG |
939 ODM_BB_RA_MASK |
940 /*@ODM_BB_DYNAMIC_TXPWR |*/
941 ODM_BB_FA_CNT |
942 ODM_BB_RSSI_MONITOR |
943 ODM_BB_CCK_PD |
944 /*@ODM_BB_PWR_TRAIN |*/
945 ODM_BB_RATE_ADAPTIVE |
946 ODM_BB_ADAPTIVITY |
947 ODM_BB_CFO_TRACKING |
948 ODM_BB_ENV_MONITOR;
949 break;
950 #endif
951
952 #if (RTL8188F_SUPPORT)
953 case ODM_RTL8188F:
954 support_ability |=
955 ODM_BB_DIG |
956 ODM_BB_RA_MASK |
957 /*@ODM_BB_DYNAMIC_TXPWR |*/
958 ODM_BB_FA_CNT |
959 ODM_BB_RSSI_MONITOR |
960 ODM_BB_CCK_PD |
961 /*@ODM_BB_PWR_TRAIN |*/
962 ODM_BB_RATE_ADAPTIVE |
963 ODM_BB_ADAPTIVITY |
964 ODM_BB_CFO_TRACKING |
965 ODM_BB_ENV_MONITOR;
966 break;
967 #endif
968
969 #if (RTL8192F_SUPPORT)
970 case ODM_RTL8192F:
971 support_ability |=
972 ODM_BB_DIG |
973 ODM_BB_RA_MASK |
974 ODM_BB_FA_CNT |
975 ODM_BB_RSSI_MONITOR |
976 ODM_BB_CCK_PD |
977 ODM_BB_PWR_TRAIN |
978 ODM_BB_RATE_ADAPTIVE |
979 /*ODM_BB_PATH_DIV |*/
980 ODM_BB_ADAPTIVITY |
981 ODM_BB_CFO_TRACKING |
982 /*@ODM_BB_ADAPTIVE_SOML |*/
983 ODM_BB_ENV_MONITOR;
984 /*@ODM_BB_LNA_SAT_CHK |*/
985 /*@ODM_BB_PRIMARY_CCA*/
986 break;
987 #endif
988 /*@---------------AC Series-------------------*/
989
990 #if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
991 case ODM_RTL8812:
992 case ODM_RTL8821:
993 support_ability |=
994 ODM_BB_DIG |
995 ODM_BB_RA_MASK |
996 /*@ODM_BB_DYNAMIC_TXPWR |*/
997 ODM_BB_FA_CNT |
998 ODM_BB_RSSI_MONITOR |
999 ODM_BB_CCK_PD |
1000 /*@ODM_BB_PWR_TRAIN |*/
1001 ODM_BB_RATE_ADAPTIVE |
1002 ODM_BB_ADAPTIVITY |
1003 ODM_BB_CFO_TRACKING |
1004 ODM_BB_ENV_MONITOR;
1005 break;
1006 #endif
1007
1008 #if (RTL8814A_SUPPORT)
1009 case ODM_RTL8814A:
1010 support_ability |=
1011 ODM_BB_DIG |
1012 ODM_BB_RA_MASK |
1013 /*@ODM_BB_DYNAMIC_TXPWR |*/
1014 ODM_BB_FA_CNT |
1015 ODM_BB_RSSI_MONITOR |
1016 ODM_BB_CCK_PD |
1017 /*@ODM_BB_PWR_TRAIN |*/
1018 ODM_BB_RATE_ADAPTIVE |
1019 ODM_BB_ADAPTIVITY |
1020 ODM_BB_CFO_TRACKING |
1021 ODM_BB_ENV_MONITOR;
1022 break;
1023 #endif
1024
1025 #if (RTL8822B_SUPPORT)
1026 case ODM_RTL8822B:
1027 support_ability |=
1028 ODM_BB_DIG |
1029 ODM_BB_RA_MASK |
1030 ODM_BB_DYNAMIC_TXPWR |
1031 ODM_BB_FA_CNT |
1032 ODM_BB_RSSI_MONITOR |
1033 ODM_BB_CCK_PD |
1034 /*@ODM_BB_PWR_TRAIN |*/
1035 ODM_BB_RATE_ADAPTIVE |
1036 /*ODM_BB_PATH_DIV |*/
1037 ODM_BB_ADAPTIVITY |
1038 ODM_BB_CFO_TRACKING |
1039 ODM_BB_ENV_MONITOR;
1040 break;
1041 #endif
1042
1043 #if (RTL8821C_SUPPORT)
1044 case ODM_RTL8821C:
1045 support_ability |=
1046 ODM_BB_DIG |
1047 ODM_BB_RA_MASK |
1048 /*@ODM_BB_DYNAMIC_TXPWR |*/
1049 ODM_BB_FA_CNT |
1050 ODM_BB_RSSI_MONITOR |
1051 ODM_BB_CCK_PD |
1052 /*@ODM_BB_PWR_TRAIN |*/
1053 ODM_BB_RATE_ADAPTIVE |
1054 ODM_BB_ADAPTIVITY |
1055 ODM_BB_CFO_TRACKING |
1056 ODM_BB_ENV_MONITOR;
1057 break;
1058 #endif
1059
1060 /*@---------------JGR3 Series-------------------*/
1061
1062 #if (RTL8822C_SUPPORT)
1063 case ODM_RTL8822C:
1064 support_ability |=
1065 ODM_BB_DIG |
1066 ODM_BB_RA_MASK |
1067 /* ODM_BB_DYNAMIC_TXPWR |*/
1068 ODM_BB_FA_CNT |
1069 ODM_BB_RSSI_MONITOR |
1070 ODM_BB_CCK_PD |
1071 ODM_BB_RATE_ADAPTIVE |
1072 ODM_BB_PATH_DIV |
1073 ODM_BB_ADAPTIVITY |
1074 ODM_BB_CFO_TRACKING |
1075 ODM_BB_ENV_MONITOR;
1076 break;
1077 #endif
1078
1079 #if (RTL8814B_SUPPORT)
1080 case ODM_RTL8814B:
1081 support_ability |=
1082 ODM_BB_DIG |
1083 ODM_BB_RA_MASK |
1084 /*@ODM_BB_DYNAMIC_TXPWR |*/
1085 ODM_BB_FA_CNT |
1086 ODM_BB_RSSI_MONITOR |
1087 ODM_BB_CCK_PD |
1088 /*@ODM_BB_PWR_TRAIN |*/
1089 /*ODM_BB_RATE_ADAPTIVE |*/
1090 ODM_BB_ADAPTIVITY;
1091 /*ODM_BB_CFO_TRACKING |*/
1092 /*ODM_BB_ENV_MONITOR;*/
1093 break;
1094 #endif
1095
1096 default:
1097 support_ability |=
1098 ODM_BB_DIG |
1099 ODM_BB_RA_MASK |
1100 /*@ODM_BB_DYNAMIC_TXPWR |*/
1101 ODM_BB_FA_CNT |
1102 ODM_BB_RSSI_MONITOR |
1103 ODM_BB_CCK_PD |
1104 /*@ODM_BB_PWR_TRAIN |*/
1105 ODM_BB_RATE_ADAPTIVE |
1106 ODM_BB_ADAPTIVITY |
1107 ODM_BB_CFO_TRACKING |
1108 ODM_BB_ENV_MONITOR;
1109
1110 pr_debug("[Warning] Supportability Init Warning !!!\n");
1111 break;
1112 }
1113
1114 return support_ability;
1115 }
1116 #endif
1117
1118 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
phydm_supportability_init_ap(void * dm_void)1119 u64 phydm_supportability_init_ap(
1120 void *dm_void)
1121 {
1122 struct dm_struct *dm = (struct dm_struct *)dm_void;
1123 u64 support_ability = 0;
1124
1125 switch (dm->support_ic_type) {
1126 /*@---------------N Series--------------------*/
1127 #if (RTL8188E_SUPPORT)
1128 case ODM_RTL8188E:
1129 support_ability |=
1130 ODM_BB_DIG |
1131 ODM_BB_RA_MASK |
1132 ODM_BB_FA_CNT |
1133 ODM_BB_RSSI_MONITOR |
1134 ODM_BB_CCK_PD |
1135 /*ODM_BB_PWR_TRAIN |*/
1136 ODM_BB_RATE_ADAPTIVE |
1137 ODM_BB_ADAPTIVITY |
1138 ODM_BB_CFO_TRACKING |
1139 ODM_BB_ENV_MONITOR |
1140 ODM_BB_PRIMARY_CCA;
1141 break;
1142 #endif
1143
1144 #if (RTL8192E_SUPPORT)
1145 case ODM_RTL8192E:
1146 support_ability |=
1147 ODM_BB_DIG |
1148 ODM_BB_RA_MASK |
1149 ODM_BB_FA_CNT |
1150 ODM_BB_RSSI_MONITOR |
1151 ODM_BB_CCK_PD |
1152 /*ODM_BB_PWR_TRAIN |*/
1153 ODM_BB_RATE_ADAPTIVE |
1154 ODM_BB_ADAPTIVITY |
1155 ODM_BB_CFO_TRACKING |
1156 ODM_BB_ENV_MONITOR |
1157 ODM_BB_PRIMARY_CCA;
1158 break;
1159 #endif
1160
1161 #if (RTL8723B_SUPPORT)
1162 case ODM_RTL8723B:
1163 support_ability |=
1164 ODM_BB_DIG |
1165 ODM_BB_RA_MASK |
1166 ODM_BB_FA_CNT |
1167 ODM_BB_RSSI_MONITOR |
1168 ODM_BB_CCK_PD |
1169 /*ODM_BB_PWR_TRAIN |*/
1170 ODM_BB_RATE_ADAPTIVE |
1171 ODM_BB_ADAPTIVITY |
1172 ODM_BB_CFO_TRACKING |
1173 ODM_BB_ENV_MONITOR;
1174 break;
1175 #endif
1176
1177 #if (RTL8198F_SUPPORT || RTL8197F_SUPPORT)
1178 case ODM_RTL8198F:
1179 support_ability |=
1180 /*ODM_BB_DIG |*/
1181 ODM_BB_RA_MASK |
1182 ODM_BB_FA_CNT |
1183 ODM_BB_RSSI_MONITOR |
1184 ODM_BB_CCK_PD |
1185 /*ODM_BB_PWR_TRAIN |*/
1186 /*ODM_BB_RATE_ADAPTIVE |*/
1187 ODM_BB_ADAPTIVITY;
1188 /*ODM_BB_CFO_TRACKING |*/
1189 /*ODM_BB_ADAPTIVE_SOML |*/
1190 /*ODM_BB_ENV_MONITOR |*/
1191 /*ODM_BB_LNA_SAT_CHK |*/
1192 /*ODM_BB_PRIMARY_CCA;*/
1193 break;
1194 case ODM_RTL8197F:
1195 support_ability |=
1196 ODM_BB_DIG |
1197 ODM_BB_RA_MASK |
1198 ODM_BB_FA_CNT |
1199 ODM_BB_RSSI_MONITOR |
1200 ODM_BB_CCK_PD |
1201 /*ODM_BB_PWR_TRAIN |*/
1202 ODM_BB_RATE_ADAPTIVE |
1203 ODM_BB_ADAPTIVITY |
1204 ODM_BB_CFO_TRACKING |
1205 ODM_BB_ADAPTIVE_SOML |
1206 ODM_BB_ENV_MONITOR |
1207 ODM_BB_LNA_SAT_CHK |
1208 ODM_BB_PRIMARY_CCA;
1209 break;
1210 #endif
1211
1212 #if (RTL8192F_SUPPORT)
1213 case ODM_RTL8192F:
1214 support_ability |=
1215 ODM_BB_DIG |
1216 ODM_BB_RA_MASK |
1217 ODM_BB_FA_CNT |
1218 ODM_BB_RSSI_MONITOR |
1219 ODM_BB_CCK_PD |
1220 /*ODM_BB_PWR_TRAIN |*/
1221 ODM_BB_RATE_ADAPTIVE |
1222 ODM_BB_ADAPTIVITY |
1223 /*ODM_BB_CFO_TRACKING |*/
1224 ODM_BB_ADAPTIVE_SOML |
1225 /*ODM_BB_PATH_DIV |*/
1226 ODM_BB_ENV_MONITOR |
1227 /*ODM_BB_LNA_SAT_CHK |*/
1228 /*ODM_BB_PRIMARY_CCA |*/
1229 0;
1230 break;
1231 #endif
1232
1233 /*@---------------AC Series-------------------*/
1234
1235 #if (RTL8881A_SUPPORT)
1236 case ODM_RTL8881A:
1237 support_ability |=
1238 ODM_BB_DIG |
1239 ODM_BB_RA_MASK |
1240 ODM_BB_FA_CNT |
1241 ODM_BB_RSSI_MONITOR |
1242 ODM_BB_CCK_PD |
1243 /*ODM_BB_PWR_TRAIN |*/
1244 ODM_BB_RATE_ADAPTIVE |
1245 ODM_BB_ADAPTIVITY |
1246 ODM_BB_CFO_TRACKING |
1247 ODM_BB_ENV_MONITOR;
1248 break;
1249 #endif
1250
1251 #if (RTL8814A_SUPPORT)
1252 case ODM_RTL8814A:
1253 support_ability |=
1254 ODM_BB_DIG |
1255 ODM_BB_RA_MASK |
1256 ODM_BB_FA_CNT |
1257 ODM_BB_RSSI_MONITOR |
1258 ODM_BB_CCK_PD |
1259 /*ODM_BB_PWR_TRAIN |*/
1260 ODM_BB_RATE_ADAPTIVE |
1261 ODM_BB_ADAPTIVITY |
1262 ODM_BB_CFO_TRACKING |
1263 ODM_BB_ENV_MONITOR;
1264 break;
1265 #endif
1266
1267 #if (RTL8822B_SUPPORT)
1268 case ODM_RTL8822B:
1269 support_ability |=
1270 ODM_BB_DIG |
1271 ODM_BB_RA_MASK |
1272 ODM_BB_FA_CNT |
1273 ODM_BB_RSSI_MONITOR |
1274 ODM_BB_CCK_PD |
1275 /*ODM_BB_PWR_TRAIN |*/
1276 /*ODM_BB_ADAPTIVE_SOML |*/
1277 ODM_BB_RATE_ADAPTIVE |
1278 ODM_BB_ADAPTIVITY |
1279 ODM_BB_CFO_TRACKING |
1280 ODM_BB_ENV_MONITOR;
1281 break;
1282 #endif
1283
1284 #if (RTL8821C_SUPPORT)
1285 case ODM_RTL8821C:
1286 support_ability |=
1287 ODM_BB_DIG |
1288 ODM_BB_RA_MASK |
1289 ODM_BB_FA_CNT |
1290 ODM_BB_RSSI_MONITOR |
1291 ODM_BB_CCK_PD |
1292 /*ODM_BB_PWR_TRAIN |*/
1293 ODM_BB_RATE_ADAPTIVE |
1294 ODM_BB_ADAPTIVITY |
1295 ODM_BB_CFO_TRACKING |
1296 ODM_BB_ENV_MONITOR;
1297
1298 break;
1299 #endif
1300
1301 /*@---------------JGR3 Series-------------------*/
1302
1303 #if (RTL8814B_SUPPORT)
1304 case ODM_RTL8814B:
1305 support_ability |=
1306 ODM_BB_DIG |
1307 ODM_BB_RA_MASK |
1308 ODM_BB_FA_CNT |
1309 ODM_BB_RSSI_MONITOR |
1310 ODM_BB_CCK_PD |
1311 /*ODM_BB_PWR_TRAIN |*/
1312 /*ODM_BB_RATE_ADAPTIVE |*/
1313 ODM_BB_ADAPTIVITY;
1314 /*ODM_BB_CFO_TRACKING |*/
1315 /*ODM_BB_ENV_MONITOR;*/
1316 break;
1317 #endif
1318
1319 #if (RTL8197G_SUPPORT)
1320 case ODM_RTL8197G:
1321 support_ability |=
1322 ODM_BB_DIG |
1323 ODM_BB_RA_MASK |
1324 ODM_BB_FA_CNT |
1325 ODM_BB_RSSI_MONITOR |
1326 ODM_BB_CCK_PD |
1327 /*ODM_BB_PWR_TRAIN |*/
1328 ODM_BB_RATE_ADAPTIVE |
1329 ODM_BB_ADAPTIVITY |
1330 ODM_BB_CFO_TRACKING |
1331 ODM_BB_ENV_MONITOR;
1332 break;
1333 #endif
1334
1335 #if (RTL8812F_SUPPORT)
1336 case ODM_RTL8812F:
1337 support_ability |=
1338 ODM_BB_DIG |
1339 ODM_BB_RA_MASK |
1340 ODM_BB_FA_CNT |
1341 ODM_BB_RSSI_MONITOR |
1342 /*ODM_BB_CCK_PD |*/
1343 /*ODM_BB_PWR_TRAIN |*/
1344 ODM_BB_RATE_ADAPTIVE |
1345 ODM_BB_ADAPTIVITY |
1346 ODM_BB_CFO_TRACKING |
1347 ODM_BB_ENV_MONITOR;
1348 break;
1349 #endif
1350
1351 default:
1352 support_ability |=
1353 ODM_BB_DIG |
1354 ODM_BB_RA_MASK |
1355 ODM_BB_FA_CNT |
1356 ODM_BB_RSSI_MONITOR |
1357 ODM_BB_CCK_PD |
1358 /*ODM_BB_PWR_TRAIN |*/
1359 ODM_BB_RATE_ADAPTIVE |
1360 ODM_BB_ADAPTIVITY |
1361 ODM_BB_CFO_TRACKING |
1362 ODM_BB_ENV_MONITOR;
1363
1364 pr_debug("[Warning] Supportability Init Warning !!!\n");
1365 break;
1366 }
1367
1368 #if 0
1369 /*@[Config Antenna Diveristy]*/
1370 if (*dm->enable_antdiv)
1371 support_ability |= ODM_BB_ANT_DIV;
1372
1373 /*@[Config Adaptivity]*/
1374 if (*dm->edcca_mode)
1375 support_ability |= ODM_BB_ADAPTIVITY;
1376 #endif
1377
1378 return support_ability;
1379 }
1380 #endif
1381
1382 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
phydm_supportability_init_iot(void * dm_void)1383 u64 phydm_supportability_init_iot(
1384 void *dm_void)
1385 {
1386 struct dm_struct *dm = (struct dm_struct *)dm_void;
1387 u64 support_ability = 0;
1388
1389 switch (dm->support_ic_type) {
1390 #if (RTL8710B_SUPPORT)
1391 case ODM_RTL8710B:
1392 support_ability |=
1393 ODM_BB_DIG |
1394 ODM_BB_RA_MASK |
1395 /*ODM_BB_DYNAMIC_TXPWR |*/
1396 ODM_BB_FA_CNT |
1397 ODM_BB_RSSI_MONITOR |
1398 ODM_BB_CCK_PD |
1399 /*ODM_BB_PWR_TRAIN |*/
1400 ODM_BB_RATE_ADAPTIVE |
1401 ODM_BB_CFO_TRACKING |
1402 ODM_BB_ENV_MONITOR;
1403 break;
1404 #endif
1405
1406 #if (RTL8195A_SUPPORT)
1407 case ODM_RTL8195A:
1408 support_ability |=
1409 ODM_BB_DIG |
1410 ODM_BB_RA_MASK |
1411 /*ODM_BB_DYNAMIC_TXPWR |*/
1412 ODM_BB_FA_CNT |
1413 ODM_BB_RSSI_MONITOR |
1414 ODM_BB_CCK_PD |
1415 /*ODM_BB_PWR_TRAIN |*/
1416 ODM_BB_RATE_ADAPTIVE |
1417 ODM_BB_CFO_TRACKING |
1418 ODM_BB_ENV_MONITOR;
1419 break;
1420 #endif
1421
1422 #if (RTL8195B_SUPPORT)
1423 case ODM_RTL8195B:
1424 support_ability |=
1425 ODM_BB_DIG |
1426 ODM_BB_RA_MASK |
1427 /*ODM_BB_DYNAMIC_TXPWR |*/
1428 ODM_BB_FA_CNT |
1429 ODM_BB_RSSI_MONITOR |
1430 ODM_BB_CCK_PD |
1431 /*ODM_BB_PWR_TRAIN |*/
1432 ODM_BB_RATE_ADAPTIVE |
1433 ODM_BB_ADAPTIVITY |
1434 ODM_BB_CFO_TRACKING;
1435 /*ODM_BB_ENV_MONITOR*/
1436 break;
1437 #endif
1438
1439 #if (RTL8721D_SUPPORT)
1440 case ODM_RTL8721D:
1441 support_ability |=
1442 ODM_BB_DIG |
1443 ODM_BB_RA_MASK |
1444 /*ODM_BB_DYNAMIC_TXPWR |*/
1445 ODM_BB_FA_CNT |
1446 ODM_BB_RSSI_MONITOR |
1447 ODM_BB_CCK_PD |
1448 /*ODM_BB_PWR_TRAIN |*/
1449 ODM_BB_RATE_ADAPTIVE |
1450 ODM_BB_ADAPTIVITY |
1451 ODM_BB_CFO_TRACKING |
1452 ODM_BB_ENV_MONITOR;
1453 break;
1454 #endif
1455
1456 #if (RTL8710C_SUPPORT)
1457 case ODM_RTL8710C:
1458 support_ability |=
1459 ODM_BB_DIG |
1460 ODM_BB_RA_MASK |
1461 /*ODM_BB_DYNAMIC_TXPWR |*/
1462 ODM_BB_FA_CNT |
1463 ODM_BB_RSSI_MONITOR |
1464 ODM_BB_CCK_PD |
1465 /*ODM_BB_PWR_TRAIN |*/
1466 ODM_BB_RATE_ADAPTIVE |
1467 ODM_BB_ADAPTIVITY |
1468 ODM_BB_CFO_TRACKING |
1469 ODM_BB_ENV_MONITOR;
1470 break;
1471 #endif
1472 default:
1473 support_ability |=
1474 ODM_BB_DIG |
1475 ODM_BB_RA_MASK |
1476 /*ODM_BB_DYNAMIC_TXPWR |*/
1477 ODM_BB_FA_CNT |
1478 ODM_BB_RSSI_MONITOR |
1479 ODM_BB_CCK_PD |
1480 /*ODM_BB_PWR_TRAIN |*/
1481 ODM_BB_RATE_ADAPTIVE |
1482 ODM_BB_CFO_TRACKING |
1483 ODM_BB_ENV_MONITOR;
1484
1485 pr_debug("[Warning] Supportability Init Warning !!!\n");
1486 break;
1487 }
1488
1489 return support_ability;
1490 }
1491 #endif
1492
phydm_fwoffload_ability_init(struct dm_struct * dm,enum phydm_offload_ability offload_ability)1493 void phydm_fwoffload_ability_init(struct dm_struct *dm,
1494 enum phydm_offload_ability offload_ability)
1495 {
1496 switch (offload_ability) {
1497 case PHYDM_PHY_PARAM_OFFLOAD:
1498 if (dm->support_ic_type &
1499 (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
1500 dm->fw_offload_ability |= PHYDM_PHY_PARAM_OFFLOAD;
1501 break;
1502
1503 case PHYDM_RF_IQK_OFFLOAD:
1504 dm->fw_offload_ability |= PHYDM_RF_IQK_OFFLOAD;
1505 break;
1506
1507 default:
1508 PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
1509 break;
1510 }
1511
1512 PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
1513 dm->fw_offload_ability);
1514 }
1515
phydm_fwoffload_ability_clear(struct dm_struct * dm,enum phydm_offload_ability offload_ability)1516 void phydm_fwoffload_ability_clear(struct dm_struct *dm,
1517 enum phydm_offload_ability offload_ability)
1518 {
1519 switch (offload_ability) {
1520 case PHYDM_PHY_PARAM_OFFLOAD:
1521 if (dm->support_ic_type &
1522 (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
1523 dm->fw_offload_ability &= (~PHYDM_PHY_PARAM_OFFLOAD);
1524 break;
1525
1526 case PHYDM_RF_IQK_OFFLOAD:
1527 dm->fw_offload_ability &= (~PHYDM_RF_IQK_OFFLOAD);
1528 break;
1529
1530 default:
1531 PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
1532 break;
1533 }
1534
1535 PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
1536 dm->fw_offload_ability);
1537 }
1538
phydm_supportability_init(void * dm_void)1539 void phydm_supportability_init(void *dm_void)
1540 {
1541 struct dm_struct *dm = (struct dm_struct *)dm_void;
1542 u64 support_ability;
1543
1544 if (dm->manual_supportability &&
1545 *dm->manual_supportability != 0xffffffff) {
1546 support_ability = *dm->manual_supportability;
1547 } else if (*dm->mp_mode) {
1548 support_ability = 0;
1549 } else {
1550 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1551 support_ability = phydm_supportability_init_win(dm);
1552 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1553 support_ability = phydm_supportability_init_ap(dm);
1554 #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
1555 support_ability = phydm_supportability_init_ce(dm);
1556 #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
1557 support_ability = phydm_supportability_init_iot(dm);
1558 #endif
1559
1560 /*@[Config Antenna Diversity]*/
1561 if (IS_FUNC_EN(dm->enable_antdiv))
1562 support_ability |= ODM_BB_ANT_DIV;
1563
1564 /*@[Config TXpath Diversity]*/
1565 if (IS_FUNC_EN(dm->enable_pathdiv))
1566 support_ability |= ODM_BB_PATH_DIV;
1567
1568 /*@[Config Adaptive SOML]*/
1569 if (IS_FUNC_EN(dm->en_adap_soml))
1570 support_ability |= ODM_BB_ADAPTIVE_SOML;
1571
1572 }
1573 dm->support_ability = support_ability;
1574 PHYDM_DBG(dm, ODM_COMP_INIT, "IC=0x%x, mp=%d, Supportability=0x%llx\n",
1575 dm->support_ic_type, *dm->mp_mode, dm->support_ability);
1576 }
1577
phydm_rfe_init(void * dm_void)1578 void phydm_rfe_init(void *dm_void)
1579 {
1580 struct dm_struct *dm = (struct dm_struct *)dm_void;
1581
1582 PHYDM_DBG(dm, ODM_COMP_INIT, "RFE_Init\n");
1583 #if (RTL8822B_SUPPORT == 1)
1584 if (dm->support_ic_type == ODM_RTL8822B)
1585 phydm_rfe_8822b_init(dm);
1586 #endif
1587 }
1588
phydm_dm_early_init(struct dm_struct * dm)1589 void phydm_dm_early_init(struct dm_struct *dm)
1590 {
1591 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1592 phydm_init_debug_setting(dm);
1593 #endif
1594 }
1595
odm_dm_init(struct dm_struct * dm)1596 void odm_dm_init(struct dm_struct *dm)
1597 {
1598 halrf_init(dm);
1599 phydm_supportability_init(dm);
1600 phydm_rfe_init(dm);
1601 phydm_common_info_self_init(dm);
1602 phydm_rx_phy_status_init(dm);
1603 #ifdef PHYDM_AUTO_DEGBUG
1604 phydm_auto_dbg_engine_init(dm);
1605 #endif
1606 phydm_dig_init(dm);
1607 #ifdef PHYDM_SUPPORT_CCKPD
1608 phydm_cck_pd_init(dm);
1609 #endif
1610 phydm_env_monitor_init(dm);
1611 phydm_adaptivity_init(dm);
1612 phydm_ra_info_init(dm);
1613 phydm_rssi_monitor_init(dm);
1614 phydm_cfo_tracking_init(dm);
1615 phydm_rf_init(dm);
1616 phydm_dc_cancellation(dm);
1617 #ifdef PHYDM_TXA_CALIBRATION
1618 phydm_txcurrentcalibration(dm);
1619 phydm_get_pa_bias_offset(dm);
1620 #endif
1621 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1622 odm_antenna_diversity_init(dm);
1623 #endif
1624 #ifdef CONFIG_ADAPTIVE_SOML
1625 phydm_adaptive_soml_init(dm);
1626 #endif
1627 #ifdef CONFIG_PATH_DIVERSITY
1628 phydm_tx_path_diversity_init(dm);
1629 #endif
1630 #ifdef CONFIG_DYNAMIC_TX_TWR
1631 phydm_dynamic_tx_power_init(dm);
1632 #endif
1633 #if (PHYDM_LA_MODE_SUPPORT)
1634 phydm_la_init(dm);
1635 #endif
1636
1637 #ifdef PHYDM_BEAMFORMING_VERSION1
1638 phydm_beamforming_init(dm);
1639 #endif
1640
1641 #if (RTL8188E_SUPPORT)
1642 odm_ra_info_init_all(dm);
1643 #endif
1644 #ifdef PHYDM_PRIMARY_CCA
1645 phydm_primary_cca_init(dm);
1646 #endif
1647 #ifdef CONFIG_PSD_TOOL
1648 phydm_psd_init(dm);
1649 #endif
1650
1651 #ifdef CONFIG_SMART_ANTENNA
1652 phydm_smt_ant_init(dm);
1653 #endif
1654 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
1655 phydm_lna_sat_check_init(dm);
1656 #endif
1657 #ifdef CONFIG_MCC_DM
1658 phydm_mcc_init(dm);
1659 #endif
1660
1661 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
1662 phydm_cck_rx_pathdiv_init(dm);
1663 #endif
1664
1665 #ifdef CONFIG_MU_RSOML
1666 phydm_mu_rsoml_init(dm);
1667 #endif
1668 }
1669
odm_dm_reset(struct dm_struct * dm)1670 void odm_dm_reset(struct dm_struct *dm)
1671 {
1672 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1673 odm_ant_div_reset(dm);
1674 #endif
1675 phydm_set_edcca_threshold_api(dm);
1676 }
1677
phydm_supportability_en(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)1678 void phydm_supportability_en(void *dm_void, char input[][16], u32 *_used,
1679 char *output, u32 *_out_len)
1680 {
1681 struct dm_struct *dm = (struct dm_struct *)dm_void;
1682 u32 dm_value[10] = {0};
1683 u64 pre_support_ability, one = 1;
1684 u64 comp = 0;
1685 u32 used = *_used;
1686 u32 out_len = *_out_len;
1687 u8 i;
1688
1689 for (i = 0; i < 5; i++) {
1690 if (input[i + 1])
1691 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);
1692 }
1693
1694 pre_support_ability = dm->support_ability;
1695 comp = dm->support_ability;
1696
1697 PDM_SNPF(out_len, used, output + used, out_len - used,
1698 "\n================================\n");
1699
1700 if (dm_value[0] == 100) {
1701 PDM_SNPF(out_len, used, output + used, out_len - used,
1702 "[Supportability] PhyDM Selection\n");
1703 PDM_SNPF(out_len, used, output + used, out_len - used,
1704 "================================\n");
1705 PDM_SNPF(out_len, used, output + used, out_len - used,
1706 "00. (( %s ))DIG\n",
1707 ((comp & ODM_BB_DIG) ? ("V") : (".")));
1708 PDM_SNPF(out_len, used, output + used, out_len - used,
1709 "01. (( %s ))RA_MASK\n",
1710 ((comp & ODM_BB_RA_MASK) ? ("V") : (".")));
1711 PDM_SNPF(out_len, used, output + used, out_len - used,
1712 "02. (( %s ))DYN_TXPWR\n",
1713 ((comp & ODM_BB_DYNAMIC_TXPWR) ? ("V") : (".")));
1714 PDM_SNPF(out_len, used, output + used, out_len - used,
1715 "03. (( %s ))FA_CNT\n",
1716 ((comp & ODM_BB_FA_CNT) ? ("V") : (".")));
1717 PDM_SNPF(out_len, used, output + used, out_len - used,
1718 "04. (( %s ))RSSI_MNTR\n",
1719 ((comp & ODM_BB_RSSI_MONITOR) ? ("V") : (".")));
1720 PDM_SNPF(out_len, used, output + used, out_len - used,
1721 "05. (( %s ))CCK_PD\n",
1722 ((comp & ODM_BB_CCK_PD) ? ("V") : (".")));
1723 PDM_SNPF(out_len, used, output + used, out_len - used,
1724 "06. (( %s ))ANT_DIV\n",
1725 ((comp & ODM_BB_ANT_DIV) ? ("V") : (".")));
1726 PDM_SNPF(out_len, used, output + used, out_len - used,
1727 "07. (( %s ))SMT_ANT\n",
1728 ((comp & ODM_BB_SMT_ANT) ? ("V") : (".")));
1729 PDM_SNPF(out_len, used, output + used, out_len - used,
1730 "08. (( %s ))PWR_TRAIN\n",
1731 ((comp & ODM_BB_PWR_TRAIN) ? ("V") : (".")));
1732 PDM_SNPF(out_len, used, output + used, out_len - used,
1733 "09. (( %s ))RA\n",
1734 ((comp & ODM_BB_RATE_ADAPTIVE) ? ("V") : (".")));
1735 PDM_SNPF(out_len, used, output + used, out_len - used,
1736 "10. (( %s ))PATH_DIV\n",
1737 ((comp & ODM_BB_PATH_DIV) ? ("V") : (".")));
1738 PDM_SNPF(out_len, used, output + used, out_len - used,
1739 "11. (( %s ))DFS\n",
1740 ((comp & ODM_BB_DFS) ? ("V") : (".")));
1741 PDM_SNPF(out_len, used, output + used, out_len - used,
1742 "12. (( %s ))DYN_ARFR\n",
1743 ((comp & ODM_BB_DYNAMIC_ARFR) ? ("V") : (".")));
1744 PDM_SNPF(out_len, used, output + used, out_len - used,
1745 "13. (( %s ))ADAPTIVITY\n",
1746 ((comp & ODM_BB_ADAPTIVITY) ? ("V") : (".")));
1747 PDM_SNPF(out_len, used, output + used, out_len - used,
1748 "14. (( %s ))CFO_TRACK\n",
1749 ((comp & ODM_BB_CFO_TRACKING) ? ("V") : (".")));
1750 PDM_SNPF(out_len, used, output + used, out_len - used,
1751 "15. (( %s ))ENV_MONITOR\n",
1752 ((comp & ODM_BB_ENV_MONITOR) ? ("V") : (".")));
1753 PDM_SNPF(out_len, used, output + used, out_len - used,
1754 "16. (( %s ))PRI_CCA\n",
1755 ((comp & ODM_BB_PRIMARY_CCA) ? ("V") : (".")));
1756 PDM_SNPF(out_len, used, output + used, out_len - used,
1757 "17. (( %s ))ADPTV_SOML\n",
1758 ((comp & ODM_BB_ADAPTIVE_SOML) ? ("V") : (".")));
1759 PDM_SNPF(out_len, used, output + used, out_len - used,
1760 "18. (( %s ))LNA_SAT_CHK\n",
1761 ((comp & ODM_BB_LNA_SAT_CHK) ? ("V") : (".")));
1762
1763 PDM_SNPF(out_len, used, output + used, out_len - used,
1764 "================================\n");
1765 PDM_SNPF(out_len, used, output + used, out_len - used,
1766 "[Supportability] PhyDM offload ability\n");
1767 PDM_SNPF(out_len, used, output + used, out_len - used,
1768 "================================\n");
1769
1770 PDM_SNPF(out_len, used, output + used, out_len - used,
1771 "00. (( %s ))PHY PARAM OFFLOAD\n",
1772 ((dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) ?
1773 ("V") : (".")));
1774 PDM_SNPF(out_len, used, output + used, out_len - used,
1775 "01. (( %s ))RF IQK OFFLOAD\n",
1776 ((dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ?
1777 ("V") : (".")));
1778 PDM_SNPF(out_len, used, output + used, out_len - used,
1779 "================================\n");
1780
1781 } else if (dm_value[0] == 101) {
1782 dm->support_ability = 0;
1783 PDM_SNPF(out_len, used, output + used, out_len - used,
1784 "Disable all support_ability components\n");
1785 } else {
1786 if (dm_value[1] == 1) { /* @enable */
1787 dm->support_ability |= (one << dm_value[0]);
1788 } else if (dm_value[1] == 2) {/* @disable */
1789 dm->support_ability &= ~(one << dm_value[0]);
1790 } else {
1791 PDM_SNPF(out_len, used, output + used, out_len - used,
1792 "[Warning!!!] 1:enable, 2:disable\n");
1793 }
1794 }
1795 PDM_SNPF(out_len, used, output + used, out_len - used,
1796 "pre-supportability = 0x%llx\n", pre_support_ability);
1797 PDM_SNPF(out_len, used, output + used, out_len - used,
1798 "Cur-supportability = 0x%llx\n", dm->support_ability);
1799 PDM_SNPF(out_len, used, output + used, out_len - used,
1800 "================================\n");
1801
1802 *_used = used;
1803 *_out_len = out_len;
1804 }
1805
phydm_watchdog_lps_32k(struct dm_struct * dm)1806 void phydm_watchdog_lps_32k(struct dm_struct *dm)
1807 {
1808 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
1809
1810 phydm_common_info_self_update(dm);
1811 phydm_rssi_monitor_check(dm);
1812 phydm_dig_lps_32k(dm);
1813 phydm_common_info_self_reset(dm);
1814 }
1815
phydm_watchdog_lps(struct dm_struct * dm)1816 void phydm_watchdog_lps(struct dm_struct *dm)
1817 {
1818 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
1819 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
1820
1821 phydm_common_info_self_update(dm);
1822 phydm_rssi_monitor_check(dm);
1823 phydm_basic_dbg_message(dm);
1824 phydm_receiver_blocking(dm);
1825 phydm_false_alarm_counter_statistics(dm);
1826 phydm_dig_by_rssi_lps(dm);
1827 #ifdef PHYDM_SUPPORT_CCKPD
1828 phydm_cck_pd_th(dm);
1829 #endif
1830 phydm_adaptivity(dm);
1831 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
1832 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1833 /*@enable AntDiv in PS mode, request from SD4 Jeff*/
1834 odm_antenna_diversity(dm);
1835 #endif
1836 #endif
1837 phydm_common_info_self_reset(dm);
1838 #endif
1839 }
1840
phydm_watchdog_mp(struct dm_struct * dm)1841 void phydm_watchdog_mp(struct dm_struct *dm)
1842 {
1843 }
1844
phydm_pause_dm_watchdog(void * dm_void,enum phydm_pause_type pause_type)1845 void phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type)
1846 {
1847 struct dm_struct *dm = (struct dm_struct *)dm_void;
1848
1849 if (pause_type == PHYDM_PAUSE) {
1850 dm->disable_phydm_watchdog = 1;
1851 PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Stop\n");
1852 } else {
1853 dm->disable_phydm_watchdog = 0;
1854 PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Start\n");
1855 }
1856 }
1857
phydm_pause_func(void * dm_void,enum phydm_func_idx pause_func,enum phydm_pause_type pause_type,enum phydm_pause_level pause_lv,u8 val_lehgth,u32 * val_buf)1858 u8 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func,
1859 enum phydm_pause_type pause_type,
1860 enum phydm_pause_level pause_lv, u8 val_lehgth,
1861 u32 *val_buf)
1862 {
1863 struct dm_struct *dm = (struct dm_struct *)dm_void;
1864 struct phydm_func_poiner *func_t = &dm->phydm_func_handler;
1865 s8 *pause_lv_pre = &dm->s8_dummy;
1866 u32 *bkp_val = &dm->u32_dummy;
1867 u32 ori_val[5] = {0};
1868 u64 pause_func_bitmap = (u64)BIT(pause_func);
1869 u8 i = 0;
1870 u8 en_2rcca = 0;
1871 u8 en_bw40m = 0;
1872 u8 pause_result = PAUSE_FAIL;
1873
1874 PHYDM_DBG(dm, ODM_COMP_API, "\n");
1875 PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] LV=%d, Len=%d\n", __func__,
1876 ((pause_type == PHYDM_PAUSE) ? "Pause" :
1877 ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
1878 pause_lv, val_lehgth);
1879
1880 if (pause_lv >= PHYDM_PAUSE_MAX_NUM) {
1881 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING]Wrong LV=%d\n", pause_lv);
1882 return PAUSE_FAIL;
1883 }
1884
1885 if (pause_func == F00_DIG) {
1886 PHYDM_DBG(dm, ODM_COMP_API, "[DIG]\n");
1887
1888 if (val_lehgth != 1) {
1889 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
1890 return PAUSE_FAIL;
1891 }
1892
1893 ori_val[0] = (u32)(dm->dm_dig_table.cur_ig_value);
1894 pause_lv_pre = &dm->pause_lv_table.lv_dig;
1895 bkp_val = (u32 *)(&dm->dm_dig_table.rvrt_val);
1896 /*@function pointer hook*/
1897 func_t->pause_phydm_handler = phydm_set_dig_val;
1898
1899 #ifdef PHYDM_SUPPORT_CCKPD
1900 } else if (pause_func == F05_CCK_PD) {
1901 PHYDM_DBG(dm, ODM_COMP_API, "[CCK_PD]\n");
1902
1903 if (val_lehgth != 1) {
1904 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
1905 return PAUSE_FAIL;
1906 }
1907
1908 ori_val[0] = (u32)dm->dm_cckpd_table.cck_pd_lv;
1909 pause_lv_pre = &dm->pause_lv_table.lv_cckpd;
1910 bkp_val = (u32 *)(&dm->dm_cckpd_table.rvrt_val);
1911 /*@function pointer hook*/
1912 func_t->pause_phydm_handler = phydm_set_cckpd_val;
1913 #endif
1914
1915 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1916 } else if (pause_func == F06_ANT_DIV) {
1917 PHYDM_DBG(dm, ODM_COMP_API, "[AntDiv]\n");
1918
1919 if (val_lehgth != 1) {
1920 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
1921 return PAUSE_FAIL;
1922 }
1923 /*@default antenna*/
1924 ori_val[0] = (u32)(dm->dm_fat_table.rx_idle_ant);
1925 pause_lv_pre = &dm->pause_lv_table.lv_antdiv;
1926 bkp_val = (u32 *)(&dm->dm_fat_table.rvrt_val);
1927 /*@function pointer hook*/
1928 func_t->pause_phydm_handler = phydm_set_antdiv_val;
1929
1930 #endif
1931 #ifdef PHYDM_SUPPORT_ADAPTIVITY
1932 } else if (pause_func == F13_ADPTVTY) {
1933 PHYDM_DBG(dm, ODM_COMP_API, "[Adaptivity]\n");
1934
1935 if (val_lehgth != 2) {
1936 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 2\n");
1937 return PAUSE_FAIL;
1938 }
1939
1940 ori_val[0] = (u32)(dm->adaptivity.th_l2h); /*th_l2h*/
1941 ori_val[1] = (u32)(dm->adaptivity.th_h2l); /*th_h2l*/
1942 pause_lv_pre = &dm->pause_lv_table.lv_adapt;
1943 bkp_val = (u32 *)(&dm->adaptivity.rvrt_val);
1944 /*@function pointer hook*/
1945 func_t->pause_phydm_handler = phydm_set_edcca_val;
1946
1947 #endif
1948 #ifdef CONFIG_ADAPTIVE_SOML
1949 } else if (pause_func == F17_ADPTV_SOML) {
1950 PHYDM_DBG(dm, ODM_COMP_API, "[AD-SOML]\n");
1951
1952 if (val_lehgth != 1) {
1953 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
1954 return PAUSE_FAIL;
1955 }
1956 /*SOML_ON/OFF*/
1957 ori_val[0] = (u32)(dm->dm_soml_table.soml_on_off);
1958
1959 pause_lv_pre = &dm->pause_lv_table.lv_adsl;
1960 bkp_val = (u32 *)(&dm->dm_soml_table.rvrt_val);
1961 /*@function pointer hook*/
1962 func_t->pause_phydm_handler = phydm_set_adsl_val;
1963
1964 #endif
1965 } else {
1966 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error func idx\n");
1967 return PAUSE_FAIL;
1968 }
1969
1970 PHYDM_DBG(dm, ODM_COMP_API, "Pause_LV{new , pre} = {%d ,%d}\n",
1971 pause_lv, *pause_lv_pre);
1972
1973 if (pause_type == PHYDM_PAUSE || pause_type == PHYDM_PAUSE_NO_SET) {
1974 if (pause_lv <= *pause_lv_pre) {
1975 PHYDM_DBG(dm, ODM_COMP_API,
1976 "[PAUSE FAIL] Pre_LV >= Curr_LV\n");
1977 return PAUSE_FAIL;
1978 }
1979
1980 if (!(dm->pause_ability & pause_func_bitmap)) {
1981 for (i = 0; i < val_lehgth; i++)
1982 bkp_val[i] = ori_val[i];
1983 }
1984
1985 dm->pause_ability |= pause_func_bitmap;
1986 PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
1987 dm->pause_ability);
1988
1989 if (pause_type == PHYDM_PAUSE) {
1990 for (i = 0; i < val_lehgth; i++)
1991 PHYDM_DBG(dm, ODM_COMP_API,
1992 "[PAUSE SUCCESS] val_idx[%d]{New, Ori}={0x%x, 0x%x}\n",
1993 i, val_buf[i], bkp_val[i]);
1994 func_t->pause_phydm_handler(dm, val_buf, val_lehgth);
1995 } else {
1996 for (i = 0; i < val_lehgth; i++)
1997 PHYDM_DBG(dm, ODM_COMP_API,
1998 "[PAUSE NO Set: SUCCESS] val_idx[%d]{Ori}={0x%x}\n",
1999 i, bkp_val[i]);
2000 }
2001
2002 *pause_lv_pre = pause_lv;
2003 pause_result = PAUSE_SUCCESS;
2004
2005 } else if (pause_type == PHYDM_RESUME) {
2006 if (pause_lv < *pause_lv_pre) {
2007 PHYDM_DBG(dm, ODM_COMP_API,
2008 "[Resume FAIL] Pre_LV >= Curr_LV\n");
2009 return PAUSE_FAIL;
2010 }
2011
2012 if ((dm->pause_ability & pause_func_bitmap) == 0) {
2013 PHYDM_DBG(dm, ODM_COMP_API,
2014 "[RESUME] No Need to Revert\n");
2015 return PAUSE_SUCCESS;
2016 }
2017
2018 dm->pause_ability &= ~pause_func_bitmap;
2019 PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
2020 dm->pause_ability);
2021
2022 *pause_lv_pre = PHYDM_PAUSE_RELEASE;
2023
2024 for (i = 0; i < val_lehgth; i++) {
2025 PHYDM_DBG(dm, ODM_COMP_API,
2026 "[RESUME] val_idx[%d]={0x%x}\n", i,
2027 bkp_val[i]);
2028 }
2029
2030 func_t->pause_phydm_handler(dm, bkp_val, val_lehgth);
2031
2032 pause_result = PAUSE_SUCCESS;
2033 } else {
2034 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error pause_type\n");
2035 pause_result = PAUSE_FAIL;
2036 }
2037 return pause_result;
2038 }
2039
phydm_pause_func_console(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)2040 void phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used,
2041 char *output, u32 *_out_len)
2042 {
2043 struct dm_struct *dm = (struct dm_struct *)dm_void;
2044 char help[] = "-h";
2045 u32 var1[10] = {0};
2046 u32 used = *_used;
2047 u32 out_len = *_out_len;
2048 u32 i;
2049 u8 length = 0;
2050 u32 buf[5] = {0};
2051 u8 set_result = 0;
2052 enum phydm_func_idx func = 0;
2053 enum phydm_pause_type type = 0;
2054 enum phydm_pause_level lv = 0;
2055
2056 if ((strcmp(input[1], help) == 0)) {
2057 PDM_SNPF(out_len, used, output + used, out_len - used,
2058 "{Func} {1:pause,2:pause no set 3:Resume} {lv:0~3} Val[5:0]\n");
2059
2060 goto out;
2061 }
2062
2063 for (i = 0; i < 10; i++) {
2064 if (input[i + 1])
2065 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
2066 }
2067
2068 func = (enum phydm_func_idx)var1[0];
2069 type = (enum phydm_pause_type)var1[1];
2070 lv = (enum phydm_pause_level)var1[2];
2071
2072 for (i = 0; i < 5; i++)
2073 buf[i] = var1[3 + i];
2074
2075 if (func == F00_DIG) {
2076 PDM_SNPF(out_len, used, output + used, out_len - used,
2077 "[DIG]\n");
2078 length = 1;
2079
2080 } else if (func == F05_CCK_PD) {
2081 PDM_SNPF(out_len, used, output + used, out_len - used,
2082 "[CCK_PD]\n");
2083 length = 1;
2084 } else if (func == F06_ANT_DIV) {
2085 PDM_SNPF(out_len, used, output + used, out_len - used,
2086 "[Ant_Div]\n");
2087 length = 1;
2088 } else if (func == F13_ADPTVTY) {
2089 PDM_SNPF(out_len, used, output + used, out_len - used,
2090 "[Adaptivity]\n");
2091 length = 2;
2092 } else if (func == F17_ADPTV_SOML) {
2093 PDM_SNPF(out_len, used, output + used, out_len - used,
2094 "[ADSL]\n");
2095 length = 1;
2096 } else {
2097 PDM_SNPF(out_len, used, output + used, out_len - used,
2098 "[Set Function Error]\n");
2099 length = 0;
2100 }
2101
2102 if (length != 0) {
2103 PDM_SNPF(out_len, used, output + used, out_len - used,
2104 "{%s, lv=%d} val = %d, %d}\n",
2105 ((type == PHYDM_PAUSE) ? "Pause" :
2106 ((type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
2107 lv, var1[3], var1[4]);
2108
2109 set_result = phydm_pause_func(dm, func, type, lv, length, buf);
2110 }
2111
2112 PDM_SNPF(out_len, used, output + used, out_len - used,
2113 "set_result = %d\n", set_result);
2114
2115 out:
2116 *_used = used;
2117 *_out_len = out_len;
2118 }
2119
phydm_pause_dm_by_asso_pkt(struct dm_struct * dm,enum phydm_pause_type pause_type,u8 rssi)2120 void phydm_pause_dm_by_asso_pkt(struct dm_struct *dm,
2121 enum phydm_pause_type pause_type, u8 rssi)
2122 {
2123 u32 igi_val = rssi + 10;
2124 u32 th_buf[2];
2125
2126 PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] rssi=%d\n", __func__,
2127 ((pause_type == PHYDM_PAUSE) ? "Pause" :
2128 ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
2129 rssi);
2130
2131 if (pause_type == PHYDM_RESUME) {
2132 phydm_pause_func(dm, F00_DIG, PHYDM_RESUME,
2133 PHYDM_PAUSE_LEVEL_1, 1, &igi_val);
2134
2135 phydm_pause_func(dm, F13_ADPTVTY, PHYDM_RESUME,
2136 PHYDM_PAUSE_LEVEL_1, 2, th_buf);
2137 } else {
2138 odm_write_dig(dm, (u8)igi_val);
2139 phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE,
2140 PHYDM_PAUSE_LEVEL_1, 1, &igi_val);
2141
2142 th_buf[0] = 0xff;
2143 th_buf[1] = 0xff;
2144
2145 phydm_pause_func(dm, F13_ADPTVTY, PHYDM_PAUSE,
2146 PHYDM_PAUSE_LEVEL_1, 2, th_buf);
2147 }
2148 }
2149
phydm_stop_dm_watchdog_check(void * dm_void)2150 u8 phydm_stop_dm_watchdog_check(void *dm_void)
2151 {
2152 struct dm_struct *dm = (struct dm_struct *)dm_void;
2153
2154 if (dm->disable_phydm_watchdog == 1) {
2155 PHYDM_DBG(dm, DBG_COMMON_FLOW, "Disable phydm\n");
2156 return true;
2157 } else {
2158 return false;
2159 }
2160 }
2161
phydm_watchdog(struct dm_struct * dm)2162 void phydm_watchdog(struct dm_struct *dm)
2163 {
2164 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
2165
2166 phydm_common_info_self_update(dm);
2167 phydm_phy_info_update(dm);
2168 phydm_rssi_monitor_check(dm);
2169 phydm_basic_dbg_message(dm);
2170 phydm_dm_summary(dm, FIRST_MACID);
2171 #ifdef PHYDM_AUTO_DEGBUG
2172 phydm_auto_dbg_engine(dm);
2173 #endif
2174 phydm_receiver_blocking(dm);
2175
2176 if (phydm_stop_dm_watchdog_check(dm) == true)
2177 return;
2178
2179 phydm_hw_setting(dm);
2180
2181 #ifdef PHYDM_TDMA_DIG_SUPPORT
2182 if (dm->original_dig_restore == 0)
2183 phydm_tdma_dig_timer_check(dm);
2184 else
2185 #endif
2186 {
2187 phydm_false_alarm_counter_statistics(dm);
2188 phydm_noisy_detection(dm);
2189 phydm_dig(dm);
2190 #ifdef PHYDM_SUPPORT_CCKPD
2191 phydm_cck_pd_th(dm);
2192 #endif
2193 }
2194
2195 #ifdef PHYDM_POWER_TRAINING_SUPPORT
2196 phydm_update_power_training_state(dm);
2197 #endif
2198 phydm_adaptivity(dm);
2199 phydm_ra_info_watchdog(dm);
2200 #ifdef CONFIG_PATH_DIVERSITY
2201 phydm_tx_path_diversity(dm);
2202 #endif
2203 phydm_cfo_tracking(dm);
2204 #ifdef CONFIG_DYNAMIC_TX_TWR
2205 phydm_dynamic_tx_power(dm);
2206 #endif
2207 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2208 odm_antenna_diversity(dm);
2209 #endif
2210 #ifdef CONFIG_ADAPTIVE_SOML
2211 phydm_adaptive_soml(dm);
2212 #endif
2213
2214 #ifdef PHYDM_BEAMFORMING_VERSION1
2215 phydm_beamforming_watchdog(dm);
2216 #endif
2217
2218 halrf_watchdog(dm);
2219 #ifdef PHYDM_PRIMARY_CCA
2220 phydm_primary_cca(dm);
2221 #endif
2222 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2223 odm_dtc(dm);
2224 #endif
2225
2226 phydm_env_mntr_watchdog(dm);
2227
2228 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
2229 phydm_lna_sat_chk_watchdog(dm);
2230 #endif
2231
2232 #ifdef CONFIG_MCC_DM
2233 phydm_mcc_switch(dm);
2234 #endif
2235
2236 #ifdef CONFIG_MU_RSOML
2237 phydm_mu_rsoml_decision(dm);
2238 #endif
2239
2240 phydm_common_info_self_reset(dm);
2241 }
2242
2243 /*@
2244 * Init /.. Fixed HW value. Only init time.
2245 */
odm_cmn_info_init(struct dm_struct * dm,enum odm_cmninfo cmn_info,u64 value)2246 void odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info,
2247 u64 value)
2248 {
2249 /* This section is used for init value */
2250 switch (cmn_info) {
2251 /* @Fixed ODM value. */
2252 case ODM_CMNINFO_ABILITY:
2253 dm->support_ability = (u64)value;
2254 break;
2255
2256 case ODM_CMNINFO_RF_TYPE:
2257 dm->rf_type = (u8)value;
2258 break;
2259
2260 case ODM_CMNINFO_PLATFORM:
2261 dm->support_platform = (u8)value;
2262 break;
2263
2264 case ODM_CMNINFO_INTERFACE:
2265 dm->support_interface = (u8)value;
2266 break;
2267
2268 case ODM_CMNINFO_MP_TEST_CHIP:
2269 dm->is_mp_chip = (u8)value;
2270 break;
2271
2272 case ODM_CMNINFO_IC_TYPE:
2273 dm->support_ic_type = (u32)value;
2274 break;
2275
2276 case ODM_CMNINFO_CUT_VER:
2277 dm->cut_version = (u8)value;
2278 break;
2279
2280 case ODM_CMNINFO_FAB_VER:
2281 dm->fab_version = (u8)value;
2282 break;
2283 case ODM_CMNINFO_FW_VER:
2284 dm->fw_version = (u8)value;
2285 break;
2286 case ODM_CMNINFO_FW_SUB_VER:
2287 dm->fw_sub_version = (u8)value;
2288 break;
2289 case ODM_CMNINFO_RFE_TYPE:
2290 #if (RTL8821C_SUPPORT)
2291 if (dm->support_ic_type & ODM_RTL8821C)
2292 dm->rfe_type_expand = (u8)value;
2293 else
2294 #endif
2295 dm->rfe_type = (u8)value;
2296
2297 #ifdef CONFIG_RFE_BY_HW_INFO
2298 phydm_init_hw_info_by_rfe(dm);
2299 #endif
2300 break;
2301
2302 case ODM_CMNINFO_RF_ANTENNA_TYPE:
2303 dm->ant_div_type = (u8)value;
2304 break;
2305
2306 case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH:
2307 dm->with_extenal_ant_switch = (u8)value;
2308 break;
2309
2310 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2311 case ODM_CMNINFO_BE_FIX_TX_ANT:
2312 dm->dm_fat_table.b_fix_tx_ant = (u8)value;
2313 break;
2314 #endif
2315
2316 case ODM_CMNINFO_BOARD_TYPE:
2317 if (!dm->is_init_hw_info_by_rfe)
2318 dm->board_type = (u8)value;
2319 break;
2320
2321 case ODM_CMNINFO_PACKAGE_TYPE:
2322 if (!dm->is_init_hw_info_by_rfe)
2323 dm->package_type = (u8)value;
2324 break;
2325
2326 case ODM_CMNINFO_EXT_LNA:
2327 if (!dm->is_init_hw_info_by_rfe)
2328 dm->ext_lna = (u8)value;
2329 break;
2330
2331 case ODM_CMNINFO_5G_EXT_LNA:
2332 if (!dm->is_init_hw_info_by_rfe)
2333 dm->ext_lna_5g = (u8)value;
2334 break;
2335
2336 case ODM_CMNINFO_EXT_PA:
2337 if (!dm->is_init_hw_info_by_rfe)
2338 dm->ext_pa = (u8)value;
2339 break;
2340
2341 case ODM_CMNINFO_5G_EXT_PA:
2342 if (!dm->is_init_hw_info_by_rfe)
2343 dm->ext_pa_5g = (u8)value;
2344 break;
2345
2346 case ODM_CMNINFO_GPA:
2347 if (!dm->is_init_hw_info_by_rfe)
2348 dm->type_gpa = (u16)value;
2349 break;
2350
2351 case ODM_CMNINFO_APA:
2352 if (!dm->is_init_hw_info_by_rfe)
2353 dm->type_apa = (u16)value;
2354 break;
2355
2356 case ODM_CMNINFO_GLNA:
2357 if (!dm->is_init_hw_info_by_rfe)
2358 dm->type_glna = (u16)value;
2359 break;
2360
2361 case ODM_CMNINFO_ALNA:
2362 if (!dm->is_init_hw_info_by_rfe)
2363 dm->type_alna = (u16)value;
2364 break;
2365
2366 case ODM_CMNINFO_EXT_TRSW:
2367 if (!dm->is_init_hw_info_by_rfe)
2368 dm->ext_trsw = (u8)value;
2369 break;
2370 case ODM_CMNINFO_EXT_LNA_GAIN:
2371 dm->ext_lna_gain = (u8)value;
2372 break;
2373 case ODM_CMNINFO_PATCH_ID:
2374 dm->iot_table.win_patch_id = (u8)value;
2375 break;
2376 case ODM_CMNINFO_BINHCT_TEST:
2377 dm->is_in_hct_test = (boolean)value;
2378 break;
2379 case ODM_CMNINFO_BWIFI_TEST:
2380 dm->wifi_test = (u8)value;
2381 break;
2382 case ODM_CMNINFO_SMART_CONCURRENT:
2383 dm->is_dual_mac_smart_concurrent = (boolean)value;
2384 break;
2385 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2386 case ODM_CMNINFO_CONFIG_BB_RF:
2387 dm->config_bbrf = (boolean)value;
2388 break;
2389 #endif
2390 case ODM_CMNINFO_IQKPAOFF:
2391 dm->rf_calibrate_info.is_iqk_pa_off = (boolean)value;
2392 break;
2393 case ODM_CMNINFO_REGRFKFREEENABLE:
2394 dm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value;
2395 break;
2396 case ODM_CMNINFO_RFKFREEENABLE:
2397 dm->rf_calibrate_info.rf_kfree_enable = (u8)value;
2398 break;
2399 case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE:
2400 dm->normal_rx_path = (u8)value;
2401 break;
2402 case ODM_CMNINFO_VALID_PATH_SET:
2403 dm->valid_path_set = (u8)value;
2404 break;
2405 case ODM_CMNINFO_EFUSE0X3D8:
2406 dm->efuse0x3d8 = (u8)value;
2407 break;
2408 case ODM_CMNINFO_EFUSE0X3D7:
2409 dm->efuse0x3d7 = (u8)value;
2410 break;
2411 case ODM_CMNINFO_ADVANCE_OTA:
2412 dm->p_advance_ota = (u8)value;
2413 break;
2414
2415 #ifdef CONFIG_PHYDM_DFS_MASTER
2416 case ODM_CMNINFO_DFS_REGION_DOMAIN:
2417 dm->dfs_region_domain = (u8)value;
2418 break;
2419 #endif
2420 case ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING:
2421 dm->soft_ap_special_setting = (u32)value;
2422 break;
2423
2424 case ODM_CMNINFO_X_CAP_SETTING:
2425 dm->dm_cfo_track.crystal_cap_default = (u8)value;
2426 break;
2427
2428 case ODM_CMNINFO_DPK_EN:
2429 /*@dm->dpk_en = (u1Byte)value;*/
2430 halrf_cmn_info_set(dm, HALRF_CMNINFO_DPK_EN, (u64)value);
2431 break;
2432
2433 case ODM_CMNINFO_HP_HWID:
2434 dm->hp_hw_id = (boolean)value;
2435 break;
2436 case ODM_CMNINFO_TSSI_ENABLE:
2437 dm->en_tssi_mode = (u8)value;
2438 break;
2439 case ODM_CMNINFO_DIS_DPD:
2440 dm->en_dis_dpd = (boolean)value;
2441 break;
2442 #if (RTL8721D_SUPPORT)
2443 case ODM_CMNINFO_POWER_VOLTAGE:
2444 dm->power_voltage = (u8)value;
2445 break;
2446 #endif
2447 default:
2448 break;
2449 }
2450 }
2451
odm_cmn_info_hook(struct dm_struct * dm,enum odm_cmninfo cmn_info,void * value)2452 void odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info,
2453 void *value)
2454 {
2455 /* @Hook call by reference pointer. */
2456 switch (cmn_info) {
2457 /* @Dynamic call by reference pointer. */
2458 case ODM_CMNINFO_TX_UNI:
2459 dm->num_tx_bytes_unicast = (u64 *)value;
2460 break;
2461
2462 case ODM_CMNINFO_RX_UNI:
2463 dm->num_rx_bytes_unicast = (u64 *)value;
2464 break;
2465
2466 case ODM_CMNINFO_BAND:
2467 dm->band_type = (u8 *)value;
2468 break;
2469
2470 case ODM_CMNINFO_SEC_CHNL_OFFSET:
2471 dm->sec_ch_offset = (u8 *)value;
2472 break;
2473
2474 case ODM_CMNINFO_SEC_MODE:
2475 dm->security = (u8 *)value;
2476 break;
2477
2478 case ODM_CMNINFO_BW:
2479 dm->band_width = (u8 *)value;
2480 break;
2481
2482 case ODM_CMNINFO_CHNL:
2483 dm->channel = (u8 *)value;
2484 break;
2485
2486 case ODM_CMNINFO_SCAN:
2487 dm->is_scan_in_process = (boolean *)value;
2488 break;
2489
2490 case ODM_CMNINFO_POWER_SAVING:
2491 dm->is_power_saving = (boolean *)value;
2492 break;
2493
2494 case ODM_CMNINFO_TDMA:
2495 dm->is_tdma = (boolean *)value;
2496 break;
2497
2498 case ODM_CMNINFO_ONE_PATH_CCA:
2499 dm->one_path_cca = (u8 *)value;
2500 break;
2501
2502 case ODM_CMNINFO_DRV_STOP:
2503 dm->is_driver_stopped = (boolean *)value;
2504 break;
2505 case ODM_CMNINFO_INIT_ON:
2506 dm->pinit_adpt_in_progress = (boolean *)value;
2507 break;
2508
2509 case ODM_CMNINFO_ANT_TEST:
2510 dm->antenna_test = (u8 *)value;
2511 break;
2512
2513 case ODM_CMNINFO_NET_CLOSED:
2514 dm->is_net_closed = (boolean *)value;
2515 break;
2516
2517 case ODM_CMNINFO_FORCED_RATE:
2518 dm->forced_data_rate = (u16 *)value;
2519 break;
2520 case ODM_CMNINFO_ANT_DIV:
2521 dm->enable_antdiv = (u8 *)value;
2522 break;
2523 case ODM_CMNINFO_PATH_DIV:
2524 dm->enable_pathdiv = (u8 *)value;
2525 break;
2526 case ODM_CMNINFO_ADAPTIVE_SOML:
2527 dm->en_adap_soml = (u8 *)value;
2528 break;
2529 case ODM_CMNINFO_ADAPTIVITY:
2530 dm->edcca_mode = (u8 *)value;
2531 break;
2532
2533 case ODM_CMNINFO_P2P_LINK:
2534 dm->dm_dig_table.is_p2p_in_process = (u8 *)value;
2535 break;
2536
2537 case ODM_CMNINFO_IS1ANTENNA:
2538 dm->is_1_antenna = (boolean *)value;
2539 break;
2540
2541 case ODM_CMNINFO_RFDEFAULTPATH:
2542 dm->rf_default_path = (u8 *)value;
2543 break;
2544
2545 case ODM_CMNINFO_FCS_MODE: /* @fast channel switch (= MCC mode)*/
2546 dm->is_fcs_mode_enable = (boolean *)value;
2547 break;
2548
2549 case ODM_CMNINFO_HUBUSBMODE:
2550 dm->hub_usb_mode = (u8 *)value;
2551 break;
2552 case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS:
2553 dm->is_fw_dw_rsvd_page_in_progress = (boolean *)value;
2554 break;
2555 case ODM_CMNINFO_TX_TP:
2556 dm->current_tx_tp = (u32 *)value;
2557 break;
2558 case ODM_CMNINFO_RX_TP:
2559 dm->current_rx_tp = (u32 *)value;
2560 break;
2561 case ODM_CMNINFO_SOUNDING_SEQ:
2562 dm->sounding_seq = (u8 *)value;
2563 break;
2564 #ifdef CONFIG_PHYDM_DFS_MASTER
2565 case ODM_CMNINFO_DFS_MASTER_ENABLE:
2566 dm->dfs_master_enabled = (u8 *)value;
2567 break;
2568 #endif
2569
2570 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2571 case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC:
2572 dm->dm_fat_table.p_force_tx_by_desc = (u8 *)value;
2573 break;
2574 case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA:
2575 dm->dm_fat_table.p_default_s0_s1 = (u8 *)value;
2576 break;
2577 case ODM_CMNINFO_BF_ANTDIV_DECISION:
2578 dm->dm_fat_table.is_no_csi_feedback = (boolean *)value;
2579 break;
2580 #endif
2581
2582 case ODM_CMNINFO_SOFT_AP_MODE:
2583 dm->soft_ap_mode = (u32 *)value;
2584 break;
2585 case ODM_CMNINFO_MP_MODE:
2586 dm->mp_mode = (u8 *)value;
2587 break;
2588 case ODM_CMNINFO_INTERRUPT_MASK:
2589 dm->interrupt_mask = (u32 *)value;
2590 break;
2591 case ODM_CMNINFO_BB_OPERATION_MODE:
2592 dm->bb_op_mode = (u8 *)value;
2593 break;
2594 case ODM_CMNINFO_MANUAL_SUPPORTABILITY:
2595 dm->manual_supportability = (u32 *)value;
2596 break;
2597 default:
2598 /*do nothing*/
2599 break;
2600 }
2601 }
2602
2603 /*@
2604 * Update band/CHannel/.. The values are dynamic but non-per-packet.
2605 */
odm_cmn_info_update(struct dm_struct * dm,u32 cmn_info,u64 value)2606 void odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value)
2607 {
2608 /* This init variable may be changed in run time. */
2609 switch (cmn_info) {
2610 case ODM_CMNINFO_LINK_IN_PROGRESS:
2611 dm->is_link_in_process = (boolean)value;
2612 break;
2613
2614 case ODM_CMNINFO_ABILITY:
2615 dm->support_ability = (u64)value;
2616 break;
2617
2618 case ODM_CMNINFO_RF_TYPE:
2619 dm->rf_type = (u8)value;
2620 break;
2621
2622 case ODM_CMNINFO_WIFI_DIRECT:
2623 dm->is_wifi_direct = (boolean)value;
2624 break;
2625
2626 case ODM_CMNINFO_WIFI_DISPLAY:
2627 dm->is_wifi_display = (boolean)value;
2628 break;
2629
2630 case ODM_CMNINFO_LINK:
2631 dm->is_linked = (boolean)value;
2632 break;
2633
2634 case ODM_CMNINFO_CMW500LINK:
2635 dm->iot_table.is_linked_cmw500 = (boolean)value;
2636 break;
2637
2638 case ODM_CMNINFO_STATION_STATE:
2639 dm->bsta_state = (boolean)value;
2640 break;
2641
2642 case ODM_CMNINFO_RSSI_MIN:
2643 dm->rssi_min = (u8)value;
2644 break;
2645
2646 case ODM_CMNINFO_RSSI_MIN_BY_PATH:
2647 dm->rssi_min_by_path = (u8)value;
2648 break;
2649
2650 case ODM_CMNINFO_DBG_COMP:
2651 dm->debug_components = (u64)value;
2652 break;
2653
2654 #ifdef ODM_CONFIG_BT_COEXIST
2655 /* The following is for BT HS mode and BT coexist mechanism. */
2656 case ODM_CMNINFO_BT_ENABLED:
2657 dm->bt_info_table.is_bt_enabled = (boolean)value;
2658 break;
2659
2660 case ODM_CMNINFO_BT_HS_CONNECT_PROCESS:
2661 dm->bt_info_table.is_bt_connect_process = (boolean)value;
2662 break;
2663
2664 case ODM_CMNINFO_BT_HS_RSSI:
2665 dm->bt_info_table.bt_hs_rssi = (u8)value;
2666 break;
2667
2668 case ODM_CMNINFO_BT_OPERATION:
2669 dm->bt_info_table.is_bt_hs_operation = (boolean)value;
2670 break;
2671
2672 case ODM_CMNINFO_BT_LIMITED_DIG:
2673 dm->bt_info_table.is_bt_limited_dig = (boolean)value;
2674 break;
2675 #endif
2676
2677 case ODM_CMNINFO_AP_TOTAL_NUM:
2678 dm->ap_total_num = (u8)value;
2679 break;
2680
2681 #ifdef CONFIG_PHYDM_DFS_MASTER
2682 case ODM_CMNINFO_DFS_REGION_DOMAIN:
2683 dm->dfs_region_domain = (u8)value;
2684 break;
2685 #endif
2686
2687 case ODM_CMNINFO_BT_CONTINUOUS_TURN:
2688 dm->is_bt_continuous_turn = (boolean)value;
2689 break;
2690 case ODM_CMNINFO_IS_DOWNLOAD_FW:
2691 dm->is_download_fw = (boolean)value;
2692 break;
2693 case ODM_CMNINFO_PHYDM_PATCH_ID:
2694 dm->iot_table.phydm_patch_id = (u32)value;
2695 break;
2696 case ODM_CMNINFO_RRSR_VAL:
2697 dm->dm_ra_table.rrsr_val_init = (u32)value;
2698 break;
2699 case ODM_CMNINFO_LINKED_BF_SUPPORT:
2700 dm->linked_bf_support = (u8)value;
2701 break;
2702 default:
2703 break;
2704 }
2705 }
2706
phydm_cmn_info_query(struct dm_struct * dm,enum phydm_info_query info_type)2707 u32 phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type)
2708 {
2709 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
2710 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2711 struct ccx_info *ccx_info = &dm->dm_ccx_info;
2712
2713 switch (info_type) {
2714 /*@=== [FA Relative] ===========================================*/
2715 case PHYDM_INFO_FA_OFDM:
2716 return fa_t->cnt_ofdm_fail;
2717
2718 case PHYDM_INFO_FA_CCK:
2719 return fa_t->cnt_cck_fail;
2720
2721 case PHYDM_INFO_FA_TOTAL:
2722 return fa_t->cnt_all;
2723
2724 case PHYDM_INFO_CCA_OFDM:
2725 return fa_t->cnt_ofdm_cca;
2726
2727 case PHYDM_INFO_CCA_CCK:
2728 return fa_t->cnt_cck_cca;
2729
2730 case PHYDM_INFO_CCA_ALL:
2731 return fa_t->cnt_cca_all;
2732
2733 case PHYDM_INFO_CRC32_OK_VHT:
2734 return fa_t->cnt_vht_crc32_ok;
2735
2736 case PHYDM_INFO_CRC32_OK_HT:
2737 return fa_t->cnt_ht_crc32_ok;
2738
2739 case PHYDM_INFO_CRC32_OK_LEGACY:
2740 return fa_t->cnt_ofdm_crc32_ok;
2741
2742 case PHYDM_INFO_CRC32_OK_CCK:
2743 return fa_t->cnt_cck_crc32_ok;
2744
2745 case PHYDM_INFO_CRC32_ERROR_VHT:
2746 return fa_t->cnt_vht_crc32_error;
2747
2748 case PHYDM_INFO_CRC32_ERROR_HT:
2749 return fa_t->cnt_ht_crc32_error;
2750
2751 case PHYDM_INFO_CRC32_ERROR_LEGACY:
2752 return fa_t->cnt_ofdm_crc32_error;
2753
2754 case PHYDM_INFO_CRC32_ERROR_CCK:
2755 return fa_t->cnt_cck_crc32_error;
2756
2757 case PHYDM_INFO_EDCCA_FLAG:
2758 return fa_t->edcca_flag;
2759
2760 case PHYDM_INFO_OFDM_ENABLE:
2761 return fa_t->ofdm_block_enable;
2762
2763 case PHYDM_INFO_CCK_ENABLE:
2764 return fa_t->cck_block_enable;
2765
2766 case PHYDM_INFO_DBG_PORT_0:
2767 return fa_t->dbg_port0;
2768
2769 case PHYDM_INFO_CRC32_OK_HT_AGG:
2770 return fa_t->cnt_ht_crc32_ok_agg;
2771
2772 case PHYDM_INFO_CRC32_ERROR_HT_AGG:
2773 return fa_t->cnt_ht_crc32_error_agg;
2774
2775 /*@=== [DIG] ================================================*/
2776
2777 case PHYDM_INFO_CURR_IGI:
2778 return dig_t->cur_ig_value;
2779
2780 /*@=== [RSSI] ===============================================*/
2781 case PHYDM_INFO_RSSI_MIN:
2782 return (u32)dm->rssi_min;
2783
2784 case PHYDM_INFO_RSSI_MAX:
2785 return (u32)dm->rssi_max;
2786
2787 case PHYDM_INFO_CLM_RATIO:
2788 return (u32)ccx_info->clm_ratio;
2789 case PHYDM_INFO_NHM_RATIO:
2790 return (u32)ccx_info->nhm_ratio;
2791 case PHYDM_INFO_NHM_NOISE_PWR:
2792 return (u32)ccx_info->nhm_noise_pwr;
2793 default:
2794 return 0xffffffff;
2795 }
2796 }
2797
2798 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
odm_init_all_work_items(struct dm_struct * dm)2799 void odm_init_all_work_items(struct dm_struct *dm)
2800 {
2801 void *adapter = dm->adapter;
2802 #if USE_WORKITEM
2803
2804 #ifdef CONFIG_ADAPTIVE_SOML
2805 odm_initialize_work_item(dm,
2806 &dm->dm_soml_table.phydm_adaptive_soml_workitem,
2807 (RT_WORKITEM_CALL_BACK)phydm_adaptive_soml_workitem_callback,
2808 (void *)adapter,
2809 "AdaptiveSOMLWorkitem");
2810 #endif
2811
2812 #ifdef ODM_EVM_ENHANCE_ANTDIV
2813 odm_initialize_work_item(dm,
2814 &dm->phydm_evm_antdiv_workitem,
2815 (RT_WORKITEM_CALL_BACK)phydm_evm_antdiv_workitem_callback,
2816 (void *)adapter,
2817 "EvmAntdivWorkitem");
2818 #endif
2819
2820 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
2821 odm_initialize_work_item(dm,
2822 &dm->dm_swat_table.phydm_sw_antenna_switch_workitem,
2823 (RT_WORKITEM_CALL_BACK)odm_sw_antdiv_workitem_callback,
2824 (void *)adapter,
2825 "AntennaSwitchWorkitem");
2826 #endif
2827 #if (defined(CONFIG_HL_SMART_ANTENNA))
2828 odm_initialize_work_item(dm,
2829 &dm->dm_sat_table.hl_smart_antenna_workitem,
2830 (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback,
2831 (void *)adapter,
2832 "hl_smart_ant_workitem");
2833
2834 odm_initialize_work_item(dm,
2835 &dm->dm_sat_table.hl_smart_antenna_decision_workitem,
2836 (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback,
2837 (void *)adapter,
2838 "hl_smart_ant_decision_workitem");
2839 #endif
2840
2841 odm_initialize_work_item(
2842 dm,
2843 &dm->ra_rpt_workitem,
2844 (RT_WORKITEM_CALL_BACK)halrf_update_init_rate_work_item_callback,
2845 (void *)adapter,
2846 "ra_rpt_workitem");
2847
2848 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
2849 odm_initialize_work_item(
2850 dm,
2851 &dm->fast_ant_training_workitem,
2852 (RT_WORKITEM_CALL_BACK)odm_fast_ant_training_work_item_callback,
2853 (void *)adapter,
2854 "fast_ant_training_workitem");
2855 #endif
2856
2857 #endif /*#if USE_WORKITEM*/
2858
2859 #ifdef PHYDM_BEAMFORMING_SUPPORT
2860 odm_initialize_work_item(
2861 dm,
2862 &dm->beamforming_info.txbf_info.txbf_enter_work_item,
2863 (RT_WORKITEM_CALL_BACK)hal_com_txbf_enter_work_item_callback,
2864 (void *)adapter,
2865 "txbf_enter_work_item");
2866
2867 odm_initialize_work_item(
2868 dm,
2869 &dm->beamforming_info.txbf_info.txbf_leave_work_item,
2870 (RT_WORKITEM_CALL_BACK)hal_com_txbf_leave_work_item_callback,
2871 (void *)adapter,
2872 "txbf_leave_work_item");
2873
2874 odm_initialize_work_item(
2875 dm,
2876 &dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item,
2877 (RT_WORKITEM_CALL_BACK)hal_com_txbf_fw_ndpa_work_item_callback,
2878 (void *)adapter,
2879 "txbf_fw_ndpa_work_item");
2880
2881 odm_initialize_work_item(
2882 dm,
2883 &dm->beamforming_info.txbf_info.txbf_clk_work_item,
2884 (RT_WORKITEM_CALL_BACK)hal_com_txbf_clk_work_item_callback,
2885 (void *)adapter,
2886 "txbf_clk_work_item");
2887
2888 odm_initialize_work_item(
2889 dm,
2890 &dm->beamforming_info.txbf_info.txbf_rate_work_item,
2891 (RT_WORKITEM_CALL_BACK)hal_com_txbf_rate_work_item_callback,
2892 (void *)adapter,
2893 "txbf_rate_work_item");
2894
2895 odm_initialize_work_item(
2896 dm,
2897 &dm->beamforming_info.txbf_info.txbf_status_work_item,
2898 (RT_WORKITEM_CALL_BACK)hal_com_txbf_status_work_item_callback,
2899 (void *)adapter,
2900 "txbf_status_work_item");
2901
2902 odm_initialize_work_item(
2903 dm,
2904 &dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item,
2905 (RT_WORKITEM_CALL_BACK)hal_com_txbf_reset_tx_path_work_item_callback,
2906 (void *)adapter,
2907 "txbf_reset_tx_path_work_item");
2908
2909 odm_initialize_work_item(
2910 dm,
2911 &dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item,
2912 (RT_WORKITEM_CALL_BACK)hal_com_txbf_get_tx_rate_work_item_callback,
2913 (void *)adapter,
2914 "txbf_get_tx_rate_work_item");
2915 #endif
2916
2917 #if (PHYDM_LA_MODE_SUPPORT == 1)
2918 odm_initialize_work_item(
2919 dm,
2920 &dm->adcsmp.adc_smp_work_item,
2921 (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
2922 (void *)adapter,
2923 "adc_smp_work_item");
2924
2925 odm_initialize_work_item(
2926 dm,
2927 &dm->adcsmp.adc_smp_work_item_1,
2928 (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
2929 (void *)adapter,
2930 "adc_smp_work_item_1");
2931 #endif
2932 }
2933
odm_free_all_work_items(struct dm_struct * dm)2934 void odm_free_all_work_items(struct dm_struct *dm)
2935 {
2936 #if USE_WORKITEM
2937
2938 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
2939 odm_free_work_item(&dm->dm_swat_table.phydm_sw_antenna_switch_workitem);
2940 #endif
2941
2942 #ifdef CONFIG_ADAPTIVE_SOML
2943 odm_free_work_item(&dm->dm_soml_table.phydm_adaptive_soml_workitem);
2944 #endif
2945
2946 #ifdef ODM_EVM_ENHANCE_ANTDIV
2947 odm_free_work_item(&dm->phydm_evm_antdiv_workitem);
2948 #endif
2949
2950 #if (defined(CONFIG_HL_SMART_ANTENNA))
2951 odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_workitem);
2952 odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_decision_workitem);
2953 #endif
2954
2955 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
2956 odm_free_work_item(&dm->fast_ant_training_workitem);
2957 #endif
2958 odm_free_work_item(&dm->ra_rpt_workitem);
2959 /*odm_free_work_item((&dm->sbdcnt_workitem));*/
2960 #endif
2961
2962 #ifdef PHYDM_BEAMFORMING_SUPPORT
2963 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_enter_work_item));
2964 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_leave_work_item));
2965 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item));
2966 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_clk_work_item));
2967 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_rate_work_item));
2968 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_status_work_item));
2969 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item));
2970 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item));
2971 #endif
2972
2973 #if (PHYDM_LA_MODE_SUPPORT == 1)
2974 odm_free_work_item((&dm->adcsmp.adc_smp_work_item));
2975 odm_free_work_item((&dm->adcsmp.adc_smp_work_item_1));
2976 #endif
2977 }
2978 #endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
2979
odm_init_all_timers(struct dm_struct * dm)2980 void odm_init_all_timers(struct dm_struct *dm)
2981 {
2982 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
2983 odm_ant_div_timers(dm, INIT_ANTDIV_TIMMER);
2984 #endif
2985 #if (defined(PHYDM_TDMA_DIG_SUPPORT))
2986 #ifdef IS_USE_NEW_TDMA
2987 phydm_tdma_dig_timers(dm, INIT_TDMA_DIG_TIMMER);
2988 #endif
2989 #endif
2990 #ifdef CONFIG_ADAPTIVE_SOML
2991 phydm_adaptive_soml_timers(dm, INIT_SOML_TIMMER);
2992 #endif
2993 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
2994 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
2995 phydm_lna_sat_chk_timers(dm, INIT_LNA_SAT_CHK_TIMMER);
2996 #endif
2997 #endif
2998
2999 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3000 odm_initialize_timer(dm, &dm->sbdcnt_timer,
3001 (void *)phydm_sbd_callback, NULL, "SbdTimer");
3002 #ifdef PHYDM_BEAMFORMING_SUPPORT
3003 odm_initialize_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer,
3004 (void *)hal_com_txbf_fw_ndpa_timer_callback, NULL,
3005 "txbf_fw_ndpa_timer");
3006 #endif
3007 #endif
3008
3009 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3010 #ifdef PHYDM_BEAMFORMING_SUPPORT
3011 odm_initialize_timer(dm, &dm->beamforming_info.beamforming_timer,
3012 (void *)beamforming_sw_timer_callback, NULL,
3013 "beamforming_timer");
3014 #endif
3015 #endif
3016 }
3017
odm_cancel_all_timers(struct dm_struct * dm)3018 void odm_cancel_all_timers(struct dm_struct *dm)
3019 {
3020 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3021 /* @2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in win7*/
3022 if (dm->adapter == NULL)
3023 return;
3024 #endif
3025
3026 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
3027 odm_ant_div_timers(dm, CANCEL_ANTDIV_TIMMER);
3028 #endif
3029 #ifdef PHYDM_TDMA_DIG_SUPPORT
3030 #ifdef IS_USE_NEW_TDMA
3031 phydm_tdma_dig_timers(dm, CANCEL_TDMA_DIG_TIMMER);
3032 #endif
3033 #endif
3034 #ifdef CONFIG_ADAPTIVE_SOML
3035 phydm_adaptive_soml_timers(dm, CANCEL_SOML_TIMMER);
3036 #endif
3037 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
3038 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
3039 phydm_lna_sat_chk_timers(dm, CANCEL_LNA_SAT_CHK_TIMMER);
3040 #endif
3041 #endif
3042
3043 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3044 odm_cancel_timer(dm, &dm->sbdcnt_timer);
3045 #ifdef PHYDM_BEAMFORMING_SUPPORT
3046 odm_cancel_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
3047 #endif
3048 #endif
3049
3050 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3051 #ifdef PHYDM_BEAMFORMING_SUPPORT
3052 odm_cancel_timer(dm, &dm->beamforming_info.beamforming_timer);
3053 #endif
3054 #endif
3055 }
3056
odm_release_all_timers(struct dm_struct * dm)3057 void odm_release_all_timers(struct dm_struct *dm)
3058 {
3059 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
3060 odm_ant_div_timers(dm, RELEASE_ANTDIV_TIMMER);
3061 #endif
3062 #ifdef PHYDM_TDMA_DIG_SUPPORT
3063 #ifdef IS_USE_NEW_TDMA
3064 phydm_tdma_dig_timers(dm, RELEASE_TDMA_DIG_TIMMER);
3065 #endif
3066 #endif
3067 #ifdef CONFIG_ADAPTIVE_SOML
3068 phydm_adaptive_soml_timers(dm, RELEASE_SOML_TIMMER);
3069 #endif
3070 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
3071 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
3072 phydm_lna_sat_chk_timers(dm, RELEASE_LNA_SAT_CHK_TIMMER);
3073 #endif
3074 #endif
3075
3076 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3077 odm_release_timer(dm, &dm->sbdcnt_timer);
3078 #ifdef PHYDM_BEAMFORMING_SUPPORT
3079 odm_release_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
3080 #endif
3081 #endif
3082
3083 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3084 #ifdef PHYDM_BEAMFORMING_SUPPORT
3085 odm_release_timer(dm, &dm->beamforming_info.beamforming_timer);
3086 #endif
3087 #endif
3088 }
3089
3090 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
odm_init_all_threads(struct dm_struct * dm)3091 void odm_init_all_threads(
3092 struct dm_struct *dm)
3093 {
3094 #ifdef TPT_THREAD
3095 k_tpt_task_init(dm->priv);
3096 #endif
3097 }
3098
odm_stop_all_threads(struct dm_struct * dm)3099 void odm_stop_all_threads(
3100 struct dm_struct *dm)
3101 {
3102 #ifdef TPT_THREAD
3103 k_tpt_task_stop(dm->priv);
3104 #endif
3105 }
3106 #endif
3107
3108 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3109 /* @Justin: According to the current RRSI to adjust Response Frame TX power,
3110 * 2012/11/05
3111 */
odm_dtc(struct dm_struct * dm)3112 void odm_dtc(struct dm_struct *dm)
3113 {
3114 #ifdef CONFIG_DM_RESP_TXAGC
3115 /* RSSI higher than this value, start to decade TX power */
3116 #define DTC_BASE 35
3117
3118 /* RSSI lower than this value, start to increase TX power */
3119 #define DTC_DWN_BASE (DTC_BASE - 5)
3120
3121 /* RSSI vs TX power step mapping: decade TX power */
3122 static const u8 dtc_table_down[] = {
3123 DTC_BASE,
3124 (DTC_BASE + 5),
3125 (DTC_BASE + 10),
3126 (DTC_BASE + 15),
3127 (DTC_BASE + 20),
3128 (DTC_BASE + 25)};
3129
3130 /* RSSI vs TX power step mapping: increase TX power */
3131 static const u8 dtc_table_up[] = {
3132 DTC_DWN_BASE,
3133 (DTC_DWN_BASE - 5),
3134 (DTC_DWN_BASE - 10),
3135 (DTC_DWN_BASE - 15),
3136 (DTC_DWN_BASE - 15),
3137 (DTC_DWN_BASE - 20),
3138 (DTC_DWN_BASE - 20),
3139 (DTC_DWN_BASE - 25),
3140 (DTC_DWN_BASE - 25),
3141 (DTC_DWN_BASE - 30),
3142 (DTC_DWN_BASE - 35)};
3143
3144 u8 i;
3145 u8 dtc_steps = 0;
3146 u8 sign;
3147 u8 resp_txagc = 0;
3148
3149 #if 0
3150 /* @As DIG is disabled, DTC is also disable */
3151 if (!(dm->support_ability & ODM_XXXXXX))
3152 return;
3153 #endif
3154
3155 if (dm->rssi_min > DTC_BASE) {
3156 /* need to decade the CTS TX power */
3157 sign = 1;
3158 for (i = 0; i < ARRAY_SIZE(dtc_table_down); i++) {
3159 if (dtc_table_down[i] >= dm->rssi_min || dtc_steps >= 6)
3160 break;
3161 else
3162 dtc_steps++;
3163 }
3164 }
3165 #if 0
3166 else if (dm->rssi_min > DTC_DWN_BASE) {
3167 /* needs to increase the CTS TX power */
3168 sign = 0;
3169 dtc_steps = 1;
3170 for (i = 0; i < ARRAY_SIZE(dtc_table_up); i++) {
3171 if (dtc_table_up[i] <= dm->rssi_min || dtc_steps >= 10)
3172 break;
3173 else
3174 dtc_steps++;
3175 }
3176 }
3177 #endif
3178 else {
3179 sign = 0;
3180 dtc_steps = 0;
3181 }
3182
3183 resp_txagc = dtc_steps | (sign << 4);
3184 resp_txagc = resp_txagc | (resp_txagc << 5);
3185 odm_write_1byte(dm, 0x06d9, resp_txagc);
3186
3187 PHYDM_DBG(dm, ODM_COMP_PWR_TRAIN,
3188 "%s rssi_min:%u, set RESP_TXAGC to %s %u\n", __func__,
3189 dm->rssi_min, sign ? "minus" : "plus", dtc_steps);
3190 #endif /* @CONFIG_RESP_TXAGC_ADJUST */
3191 }
3192
3193 #endif /* @#if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
3194
3195 /*@<20170126, BB-Kevin>8188F D-CUT DC cancellation and 8821C*/
phydm_dc_cancellation(struct dm_struct * dm)3196 void phydm_dc_cancellation(struct dm_struct *dm)
3197 {
3198 #ifdef PHYDM_DC_CANCELLATION
3199 u32 offset_i_hex[PHYDM_MAX_RF_PATH] = {0};
3200 u32 offset_q_hex[PHYDM_MAX_RF_PATH] = {0};
3201 u32 reg_value32[PHYDM_MAX_RF_PATH] = {0};
3202 u8 path = RF_PATH_A;
3203 u8 set_result;
3204
3205 if (!(dm->support_ic_type & ODM_DC_CANCELLATION_SUPPORT))
3206 return;
3207 if ((dm->support_ic_type & ODM_RTL8188F) &&
3208 dm->cut_version < ODM_CUT_D)
3209 return;
3210 if ((dm->support_ic_type & ODM_RTL8192F) &&
3211 dm->cut_version == ODM_CUT_A)
3212 return;
3213 if (*dm->band_width == CHANNEL_WIDTH_5)
3214 return;
3215 if (*dm->band_width == CHANNEL_WIDTH_10)
3216 return;
3217
3218 PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
3219
3220 /*@DC_Estimation (only for 2x2 ic now) */
3221
3222 for (path = RF_PATH_A; path < PHYDM_MAX_RF_PATH; path++) {
3223 if (path > RF_PATH_A &&
3224 dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8188F |
3225 ODM_RTL8710B | ODM_RTL8721D |
3226 ODM_RTL8710C))
3227 break;
3228 else if (path > RF_PATH_B &&
3229 dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8192F))
3230 break;
3231 if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
3232 PHYDM_DBG(dm, ODM_COMP_API, "STOP_TRX_FAIL\n");
3233 return;
3234 }
3235 odm_write_dig(dm, 0x7e);
3236 /*@Disable LNA*/
3237 if (dm->support_ic_type & ODM_RTL8821C)
3238 halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE);
3239 /*Turn off 3-wire*/
3240 phydm_stop_3_wire(dm, PHYDM_SET);
3241 if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) {
3242 /*set debug port to 0x235*/
3243 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
3244 PHYDM_DBG(dm, ODM_COMP_API,
3245 "Set Debug port Fail\n");
3246 return;
3247 }
3248 } else if (dm->support_ic_type & (ODM_RTL8721D |
3249 ODM_RTL8710C)) {
3250 /*set debug port to 0x200*/
3251 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x200)) {
3252 PHYDM_DBG(dm, ODM_COMP_API,
3253 "Set Debug port Fail\n");
3254 return;
3255 }
3256 } else if (dm->support_ic_type & ODM_RTL8821C) {
3257 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
3258 /*set debug port to 0x200*/
3259 PHYDM_DBG(dm, ODM_COMP_API,
3260 "Set Debug port Fail\n");
3261 return;
3262 }
3263 phydm_bb_dbg_port_header_sel(dm, 0x0);
3264 } else if (dm->support_ic_type & ODM_RTL8822B) {
3265 if (path == RF_PATH_A &&
3266 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
3267 /*set debug port to 0x200*/
3268 PHYDM_DBG(dm, ODM_COMP_API,
3269 "Set Debug port Fail\n");
3270 return;
3271 }
3272 if (path == RF_PATH_B &&
3273 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x202)) {
3274 /*set debug port to 0x200*/
3275 PHYDM_DBG(dm, ODM_COMP_API,
3276 "Set Debug port Fail\n");
3277 return;
3278 }
3279 phydm_bb_dbg_port_header_sel(dm, 0x0);
3280 } else if (dm->support_ic_type & ODM_RTL8192F) {
3281 if (path == RF_PATH_A &&
3282 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
3283 /*set debug port to 0x235*/
3284 PHYDM_DBG(dm, ODM_COMP_API,
3285 "Set Debug port Fail\n");
3286 return;
3287 }
3288 if (path == RF_PATH_B &&
3289 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x23d)) {
3290 /*set debug port to 0x23d*/
3291 PHYDM_DBG(dm, ODM_COMP_API,
3292 "Set Debug port Fail\n");
3293 return;
3294 }
3295 }
3296
3297 /*@disable CCK DCNF*/
3298 odm_set_bb_reg(dm, R_0xa78, MASKBYTE1, 0x0);
3299
3300 PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation Begin!!!\n");
3301
3302 phydm_stop_ck320(dm, true); /*stop ck320*/
3303
3304 /* the same debug port both for path-a and path-b*/
3305 reg_value32[path] = phydm_get_bb_dbg_port_val(dm);
3306
3307 phydm_stop_ck320(dm, false); /*start ck320*/
3308
3309 phydm_release_bb_dbg_port(dm);
3310 /* @Turn on 3-wire*/
3311 phydm_stop_3_wire(dm, PHYDM_REVERT);
3312 /* @Enable LNA*/
3313 if (dm->support_ic_type & ODM_RTL8821C)
3314 halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE);
3315
3316 odm_write_dig(dm, 0x20);
3317
3318 set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT);
3319
3320 PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation OK!!!\n");
3321 }
3322
3323 /*@DC_Cancellation*/
3324 /*@DC compensation to CCK data path*/
3325 odm_set_bb_reg(dm, R_0xa9c, BIT(20), 0x1);
3326 if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) {
3327 offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
3328 offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
3329
3330 /*@Before filling into registers,
3331 *offset should be multiplexed (-1)
3332 */
3333 offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
3334 (0x400 - offset_i_hex[0]) :
3335 (0x1ff - offset_i_hex[0]);
3336 offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
3337 (0x400 - offset_q_hex[0]) :
3338 (0x1ff - offset_q_hex[0]);
3339
3340 odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
3341 odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
3342 } else if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) {
3343 /* Path-a */
3344 offset_i_hex[0] = (reg_value32[0] & 0xffc00) >> 10;
3345 offset_q_hex[0] = reg_value32[0] & 0x3ff;
3346
3347 /*@Before filling into registers,
3348 *offset should be multiplexed (-1)
3349 */
3350 offset_i_hex[0] = 0x400 - offset_i_hex[0];
3351 offset_q_hex[0] = 0x400 - offset_q_hex[0];
3352
3353 odm_set_bb_reg(dm, R_0xc10, 0x3c000000,
3354 (0x3c0 & offset_i_hex[0]) >> 6);
3355 odm_set_bb_reg(dm, R_0xc10, 0xfc00, 0x3f & offset_i_hex[0]);
3356 odm_set_bb_reg(dm, R_0xc14, 0x3c000000,
3357 (0x3c0 & offset_q_hex[0]) >> 6);
3358 odm_set_bb_reg(dm, R_0xc14, 0xfc00, 0x3f & offset_q_hex[0]);
3359
3360 /* Path-b */
3361 if (dm->rf_type > RF_1T1R) {
3362 offset_i_hex[1] = (reg_value32[1] & 0xffc00) >> 10;
3363 offset_q_hex[1] = reg_value32[1] & 0x3ff;
3364
3365 /*@Before filling into registers,
3366 *offset should be multiplexed (-1)
3367 */
3368 offset_i_hex[1] = 0x400 - offset_i_hex[1];
3369 offset_q_hex[1] = 0x400 - offset_q_hex[1];
3370
3371 odm_set_bb_reg(dm, R_0xe10, 0x3c000000,
3372 (0x3c0 & offset_i_hex[1]) >> 6);
3373 odm_set_bb_reg(dm, R_0xe10, 0xfc00,
3374 0x3f & offset_i_hex[1]);
3375 odm_set_bb_reg(dm, R_0xe14, 0x3c000000,
3376 (0x3c0 & offset_q_hex[1]) >> 6);
3377 odm_set_bb_reg(dm, R_0xe14, 0xfc00,
3378 0x3f & offset_q_hex[1]);
3379 }
3380 } else if (dm->support_ic_type & (ODM_RTL8192F)) {
3381 /* Path-a I:df4[27:18],Q:df4[17:8]*/
3382 offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
3383 offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
3384
3385 /*@Before filling into registers,
3386 *offset should be multiplexed (-1)
3387 */
3388 offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
3389 (0x400 - offset_i_hex[0]) :
3390 (0xff - offset_i_hex[0]);
3391 offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
3392 (0x400 - offset_q_hex[0]) :
3393 (0xff - offset_q_hex[0]);
3394 /*Path-a I:c10[7:0],Q:c10[15:8]*/
3395 odm_set_bb_reg(dm, R_0xc10, 0xff, offset_i_hex[0]);
3396 odm_set_bb_reg(dm, R_0xc10, 0xff00, offset_q_hex[0]);
3397
3398 /* Path-b */
3399 if (dm->rf_type > RF_1T1R) {
3400 /* @I:df4[27:18],Q:df4[17:8]*/
3401 offset_i_hex[1] = (reg_value32[1] & 0xffc0000) >> 18;
3402 offset_q_hex[1] = (reg_value32[1] & 0x3ff00) >> 8;
3403
3404 /*@Before filling into registers,
3405 *offset should be multiplexed (-1)
3406 */
3407 offset_i_hex[1] = (offset_i_hex[1] >= 0x200) ?
3408 (0x400 - offset_i_hex[1]) :
3409 (0xff - offset_i_hex[1]);
3410 offset_q_hex[1] = (offset_q_hex[1] >= 0x200) ?
3411 (0x400 - offset_q_hex[1]) :
3412 (0xff - offset_q_hex[1]);
3413 /*Path-b I:c18[7:0],Q:c18[15:8]*/
3414 odm_set_bb_reg(dm, R_0xc18, 0xff, offset_i_hex[1]);
3415 odm_set_bb_reg(dm, R_0xc18, 0xff00, offset_q_hex[1]);
3416 }
3417 } else if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C)) {
3418 /*judy modified 20180517*/
3419 offset_i_hex[0] = (reg_value32[0] & 0xff80000) >> 19;
3420 offset_q_hex[0] = (reg_value32[0] & 0x3fe00) >> 9;
3421
3422 /*@Before filling into registers,
3423 *offset should be multiplexed (-1)
3424 */
3425 offset_i_hex[0] = 0x200 - offset_i_hex[0];
3426 offset_q_hex[0] = 0x200 - offset_q_hex[0];
3427
3428 odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
3429 odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
3430 }
3431 #endif
3432 }
3433
phydm_receiver_blocking(void * dm_void)3434 void phydm_receiver_blocking(void *dm_void)
3435 {
3436 #ifdef CONFIG_RECEIVER_BLOCKING
3437 struct dm_struct *dm = (struct dm_struct *)dm_void;
3438 u32 chnl = *dm->channel;
3439 u8 bw = *dm->band_width;
3440 u32 bb_regf0 = odm_get_bb_reg(dm, R_0xf0, 0xf000);
3441
3442 if (!(dm->support_ic_type & ODM_RECEIVER_BLOCKING_SUPPORT) ||
3443 *dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
3444 return;
3445
3446 if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 < 8) ||
3447 dm->support_ic_type & ODM_RTL8192E) {
3448 /*@8188E_T version*/
3449 if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
3450 goto end;
3451
3452 if (bw == CHANNEL_WIDTH_20 && chnl == 1) {
3453 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2410,
3454 PHYDM_DONT_CARE);
3455 dm->is_rx_blocking_en = true;
3456 } else if ((bw == CHANNEL_WIDTH_20) && (chnl == 13)) {
3457 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
3458 PHYDM_DONT_CARE);
3459 dm->is_rx_blocking_en = true;
3460 } else if (dm->is_rx_blocking_en && chnl != 1 && chnl != 13) {
3461 phydm_nbi_enable(dm, FUNC_DISABLE);
3462 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3463 dm->is_rx_blocking_en = false;
3464 }
3465 return;
3466 } else if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 >= 8)) {
3467 /*@8188E_S version*/
3468 if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
3469 goto end;
3470
3471 if (bw == CHANNEL_WIDTH_20 && chnl == 13) {
3472 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
3473 PHYDM_DONT_CARE);
3474 dm->is_rx_blocking_en = true;
3475 } else if (dm->is_rx_blocking_en && chnl != 13) {
3476 phydm_nbi_enable(dm, FUNC_DISABLE);
3477 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3478 dm->is_rx_blocking_en = false;
3479 }
3480 return;
3481 }
3482
3483 end:
3484 if (dm->is_rx_blocking_en) {
3485 phydm_nbi_enable(dm, FUNC_DISABLE);
3486 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3487 dm->is_rx_blocking_en = false;
3488 }
3489 #endif
3490 }
3491