1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _HAL_MP_C_
16
17 #include <drv_types.h>
18
19 #ifdef CONFIG_MP_INCLUDED
20
21 #ifdef RTW_HALMAC
22 #include <hal_data.h> /* struct HAL_DATA_TYPE, RF register definition and etc. */
23 #else /* !RTW_HALMAC */
24 #ifdef CONFIG_RTL8188E
25 #include <rtl8188e_hal.h>
26 #endif
27 #ifdef CONFIG_RTL8723B
28 #include <rtl8723b_hal.h>
29 #endif
30 #ifdef CONFIG_RTL8192E
31 #include <rtl8192e_hal.h>
32 #endif
33 #ifdef CONFIG_RTL8814A
34 #include <rtl8814a_hal.h>
35 #endif
36 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
37 #include <rtl8812a_hal.h>
38 #endif
39 #ifdef CONFIG_RTL8703B
40 #include <rtl8703b_hal.h>
41 #endif
42 #ifdef CONFIG_RTL8723D
43 #include <rtl8723d_hal.h>
44 #endif
45 #ifdef CONFIG_RTL8710B
46 #include <rtl8710b_hal.h>
47 #endif
48 #ifdef CONFIG_RTL8188F
49 #include <rtl8188f_hal.h>
50 #endif
51 #ifdef CONFIG_RTL8188GTV
52 #include <rtl8188gtv_hal.h>
53 #endif
54 #ifdef CONFIG_RTL8192F
55 #include <rtl8192f_hal.h>
56 #endif
57 #endif /* !RTW_HALMAC */
58
59
MgntQuery_NssTxRate(u16 Rate)60 u8 MgntQuery_NssTxRate(u16 Rate)
61 {
62 u8 NssNum = RF_TX_NUM_NONIMPLEMENT;
63
64 if ((Rate >= MGN_MCS8 && Rate <= MGN_MCS15) ||
65 (Rate >= MGN_VHT2SS_MCS0 && Rate <= MGN_VHT2SS_MCS9))
66 NssNum = RF_2TX;
67 else if ((Rate >= MGN_MCS16 && Rate <= MGN_MCS23) ||
68 (Rate >= MGN_VHT3SS_MCS0 && Rate <= MGN_VHT3SS_MCS9))
69 NssNum = RF_3TX;
70 else if ((Rate >= MGN_MCS24 && Rate <= MGN_MCS31) ||
71 (Rate >= MGN_VHT4SS_MCS0 && Rate <= MGN_VHT4SS_MCS9))
72 NssNum = RF_4TX;
73 else
74 NssNum = RF_1TX;
75
76 return NssNum;
77 }
78
hal_mpt_SwitchRfSetting(PADAPTER pAdapter)79 void hal_mpt_SwitchRfSetting(PADAPTER pAdapter)
80 {
81 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
82 u8 ChannelToSw = pMptCtx->MptChannelToSw;
83 u32 ulRateIdx = pMptCtx->mpt_rate_index;
84 u32 ulbandwidth = pMptCtx->MptBandWidth;
85
86 /* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/
87 if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) &&
88 (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) {
89 pMptCtx->backup0x52_RF_A = (u8)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
90 pMptCtx->backup0x52_RF_B = (u8)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
91
92 if ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) {
93 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB);
94 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB);
95 } else {
96 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD);
97 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xD);
98 }
99 } else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/
100 if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) {
101 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
102 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
103 } else {
104 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
105 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
106 }
107 } else if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
108 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A);
109 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B);
110 }
111 }
112
hal_mpt_SetPowerTracking(PADAPTER padapter,u8 enable)113 s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable)
114 {
115 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
116 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
117
118
119 if (!netif_running(padapter->pnetdev)) {
120 return _FAIL;
121 }
122
123 if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
124 return _FAIL;
125 }
126 if (enable)
127 pDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE;
128 else
129 pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
130
131 return _SUCCESS;
132 }
133
hal_mpt_GetPowerTracking(PADAPTER padapter,u8 * enable)134 void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable)
135 {
136 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
137 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
138
139
140 *enable = pDM_Odm->rf_calibrate_info.txpowertrack_control;
141 }
142
143
hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter,BOOLEAN bInCH14)144 void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
145 {
146 u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0;
147 u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12;
148 u8 i;
149 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
150 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
151 u8 u1Channel = pHalData->current_channel;
152 u32 ulRateIdx = pMptCtx->mpt_rate_index;
153 u8 DataRate = 0xFF;
154
155 /* Do not modify CCK TX filter parameters for 8822B*/
156 if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) ||
157 IS_HARDWARE_TYPE_8723D(Adapter) || IS_HARDWARE_TYPE_8192F(Adapter) || IS_HARDWARE_TYPE_8822C(Adapter))
158 return;
159
160 DataRate = mpt_to_mgnt_rate(ulRateIdx);
161
162 if (u1Channel == 14 && IS_CCK_RATE(DataRate))
163 pHalData->bCCKinCH14 = TRUE;
164 else
165 pHalData->bCCKinCH14 = FALSE;
166
167 if (IS_HARDWARE_TYPE_8703B(Adapter)) {
168 if ((u1Channel == 14) && IS_CCK_RATE(DataRate)) {
169 /* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */
170 phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0);
171 phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskLWord, 0);
172
173 } else {
174 /* Normal setting for 8703B, just recover to the default setting. */
175 /* This hardcore values reference from the parameter which BB team gave. */
176 for (i = 0 ; i < 2 ; ++i)
177 phy_set_bb_reg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);
178
179 }
180 } else if (IS_HARDWARE_TYPE_8723D(Adapter)) {
181 /* 2.4G CCK TX DFIR */
182 /* 2016.01.20 Suggest from RS BB mingzhi*/
183 if ((u1Channel == 14)) {
184 phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C);
185 phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000000);
186 phy_set_bb_reg(Adapter, 0xAAC, bMaskDWord, 0x00003667);
187 } else {
188 for (i = 0 ; i < 3 ; ++i) {
189 phy_set_bb_reg(Adapter,
190 pHalData->RegForRecover[i].offset,
191 bMaskDWord,
192 pHalData->RegForRecover[i].value);
193 }
194 }
195 } else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) {
196 /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
197 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
198 CCKSwingIndex = 20; /* default index */
199
200 if (!pHalData->bCCKinCH14) {
201 /* Readback the current bb cck swing value and compare with the table to */
202 /* get the current swing index */
203 for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
204 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13_88f[i][0]) &&
205 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13_88f[i][1])) {
206 CCKSwingIndex = i;
207 break;
208 }
209 }
210 write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][0]);
211 write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][1]);
212 write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][2]);
213 write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][3]);
214 write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][4]);
215 write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][5]);
216 write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][6]);
217 write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][7]);
218 write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][8]);
219 write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][9]);
220 write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][10]);
221 write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][11]);
222 write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][12]);
223 write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][13]);
224 write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][14]);
225 write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][15]);
226 RTW_INFO("%s , cck_swing_table_ch1_ch13_88f[%d]\n", __func__, CCKSwingIndex);
227 } else {
228 for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
229 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14_88f[i][0]) &&
230 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14_88f[i][1])) {
231 CCKSwingIndex = i;
232 break;
233 }
234 }
235 write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][0]);
236 write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][1]);
237 write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][2]);
238 write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][3]);
239 write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][4]);
240 write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][5]);
241 write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][6]);
242 write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][7]);
243 write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][8]);
244 write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][9]);
245 write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][10]);
246 write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][11]);
247 write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][12]);
248 write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][13]);
249 write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][14]);
250 write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][15]);
251 RTW_INFO("%s , cck_swing_table_ch14_88f[%d]\n", __func__, CCKSwingIndex);
252 }
253 } else {
254
255 /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
256 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
257
258 if (!pHalData->bCCKinCH14) {
259 /* Readback the current bb cck swing value and compare with the table to */
260 /* get the current swing index */
261 for (i = 0; i < CCK_TABLE_SIZE; i++) {
262 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13[i][0]) &&
263 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13[i][1])) {
264 CCKSwingIndex = i;
265 break;
266 }
267 }
268
269 /*Write 0xa22 0xa23*/
270 TempVal = cck_swing_table_ch1_ch13[CCKSwingIndex][0] +
271 (cck_swing_table_ch1_ch13[CCKSwingIndex][1] << 8);
272
273
274 /*Write 0xa24 ~ 0xa27*/
275 TempVal2 = 0;
276 TempVal2 = cck_swing_table_ch1_ch13[CCKSwingIndex][2] +
277 (cck_swing_table_ch1_ch13[CCKSwingIndex][3] << 8) +
278 (cck_swing_table_ch1_ch13[CCKSwingIndex][4] << 16) +
279 (cck_swing_table_ch1_ch13[CCKSwingIndex][5] << 24);
280
281 /*Write 0xa28 0xa29*/
282 TempVal3 = 0;
283 TempVal3 = cck_swing_table_ch1_ch13[CCKSwingIndex][6] +
284 (cck_swing_table_ch1_ch13[CCKSwingIndex][7] << 8);
285 } else {
286 for (i = 0; i < CCK_TABLE_SIZE; i++) {
287 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14[i][0]) &&
288 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14[i][1])) {
289 CCKSwingIndex = i;
290 break;
291 }
292 }
293
294 /*Write 0xa22 0xa23*/
295 TempVal = cck_swing_table_ch14[CCKSwingIndex][0] +
296 (cck_swing_table_ch14[CCKSwingIndex][1] << 8);
297
298 /*Write 0xa24 ~ 0xa27*/
299 TempVal2 = 0;
300 TempVal2 = cck_swing_table_ch14[CCKSwingIndex][2] +
301 (cck_swing_table_ch14[CCKSwingIndex][3] << 8) +
302 (cck_swing_table_ch14[CCKSwingIndex][4] << 16) +
303 (cck_swing_table_ch14[CCKSwingIndex][5] << 24);
304
305 /*Write 0xa28 0xa29*/
306 TempVal3 = 0;
307 TempVal3 = cck_swing_table_ch14[CCKSwingIndex][6] +
308 (cck_swing_table_ch14[CCKSwingIndex][7] << 8);
309 }
310
311 write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
312 write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
313 write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
314 }
315
316 }
317
hal_mpt_SetChannel(PADAPTER pAdapter)318 void hal_mpt_SetChannel(PADAPTER pAdapter)
319 {
320 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
321 struct mp_priv *pmp = &pAdapter->mppriv;
322 u8 channel = pmp->channel;
323 u8 bandwidth = pmp->bandwidth;
324
325 hal_mpt_SwitchRfSetting(pAdapter);
326
327 pHalData->bSwChnl = _TRUE;
328 pHalData->bSetChnlBW = _TRUE;
329
330 if (bandwidth == 2) {
331 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
332 } else if (bandwidth == 1) {
333 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
334 } else
335 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
336
337 hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
338 rtw_btcoex_wifionly_scan_notify(pAdapter);
339
340 }
341
342 /*
343 * Notice
344 * Switch bandwitdth may change center frequency(channel)
345 */
hal_mpt_SetBandwidth(PADAPTER pAdapter)346 void hal_mpt_SetBandwidth(PADAPTER pAdapter)
347 {
348 struct mp_priv *pmp = &pAdapter->mppriv;
349 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
350
351 u8 channel = pmp->channel;
352 u8 bandwidth = pmp->bandwidth;
353
354 pHalData->bSwChnl = _TRUE;
355 pHalData->bSetChnlBW = _TRUE;
356
357 if (bandwidth == 2) {
358 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
359 } else if (bandwidth == 1) {
360 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
361 } else
362 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
363
364 hal_mpt_SwitchRfSetting(pAdapter);
365 rtw_btcoex_wifionly_scan_notify(pAdapter);
366
367 }
368
mpt_SetTxPower_Old(PADAPTER pAdapter,MPT_TXPWR_DEF Rate,u8 * pTxPower)369 void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)
370 {
371 switch (Rate) {
372 case MPT_CCK: {
373 u32 TxAGC = 0, pwr = 0;
374
375 pwr = pTxPower[RF_PATH_A];
376 if (pwr < 0x3f) {
377 TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
378 phy_set_bb_reg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[RF_PATH_A]);
379 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC);
380 }
381 pwr = pTxPower[RF_PATH_B];
382 if (pwr < 0x3f) {
383 TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
384 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[RF_PATH_B]);
385 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC);
386 }
387 }
388 break;
389
390 case MPT_OFDM_AND_HT: {
391 u32 TxAGC = 0;
392 u8 pwr = 0;
393
394 pwr = pTxPower[0];
395 if (pwr < 0x3f) {
396 TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
397 RTW_INFO("HT Tx-rf(A) Power = 0x%x\n", TxAGC);
398 phy_set_bb_reg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
399 phy_set_bb_reg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
400 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
401 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
402 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
403 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
404 }
405 TxAGC = 0;
406 pwr = pTxPower[1];
407 if (pwr < 0x3f) {
408 TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
409 RTW_INFO("HT Tx-rf(B) Power = 0x%x\n", TxAGC);
410 phy_set_bb_reg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
411 phy_set_bb_reg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
412 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
413 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
414 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
415 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
416 }
417 }
418 break;
419
420 default:
421 break;
422 }
423 RTW_INFO("<===mpt_SetTxPower_Old()\n");
424 }
425
426 void
mpt_SetTxPower(PADAPTER pAdapter,MPT_TXPWR_DEF Rate,u8 * pTxPower)427 mpt_SetTxPower(
428 PADAPTER pAdapter,
429 MPT_TXPWR_DEF Rate,
430 u8 *pTxPower
431 )
432 {
433 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
434
435 u8 path = 0 , i = 0, MaxRate = MGN_6M;
436 u8 StartPath = RF_PATH_A, EndPath = RF_PATH_B;
437
438 if (IS_HARDWARE_TYPE_8814A(pAdapter) || IS_HARDWARE_TYPE_8814B(pAdapter))
439 EndPath = RF_PATH_D;
440 else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)
441 || IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter))
442 EndPath = RF_PATH_A;
443
444 switch (Rate) {
445 case MPT_CCK: {
446 u8 rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
447
448 for (path = StartPath; path <= EndPath; path++)
449 for (i = 0; i < sizeof(rate); ++i)
450 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
451 }
452 break;
453 case MPT_OFDM: {
454 u8 rate[] = {
455 MGN_6M, MGN_9M, MGN_12M, MGN_18M,
456 MGN_24M, MGN_36M, MGN_48M, MGN_54M,
457 };
458
459 for (path = StartPath; path <= EndPath; path++)
460 for (i = 0; i < sizeof(rate); ++i)
461 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
462 }
463 break;
464 case MPT_HT: {
465 u8 rate[] = {
466 MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4,
467 MGN_MCS5, MGN_MCS6, MGN_MCS7, MGN_MCS8, MGN_MCS9,
468 MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14,
469 MGN_MCS15, MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19,
470 MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23, MGN_MCS24,
471 MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29,
472 MGN_MCS30, MGN_MCS31,
473 };
474 if (pHalData->rf_type == RF_3T3R)
475 MaxRate = MGN_MCS23;
476 else if (pHalData->rf_type == RF_2T2R)
477 MaxRate = MGN_MCS15;
478 else
479 MaxRate = MGN_MCS7;
480 for (path = StartPath; path <= EndPath; path++) {
481 for (i = 0; i < sizeof(rate); ++i) {
482 if (rate[i] > MaxRate)
483 break;
484 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
485 }
486 }
487 }
488 break;
489 case MPT_VHT: {
490 u8 rate[] = {
491 MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
492 MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9,
493 MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
494 MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9,
495 MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
496 MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9,
497 MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4,
498 MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9,
499 };
500 if (pHalData->rf_type == RF_3T3R)
501 MaxRate = MGN_VHT3SS_MCS9;
502 else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
503 MaxRate = MGN_VHT2SS_MCS9;
504 else
505 MaxRate = MGN_VHT1SS_MCS9;
506
507 for (path = StartPath; path <= EndPath; path++) {
508 for (i = 0; i < sizeof(rate); ++i) {
509 if (rate[i] > MaxRate)
510 break;
511 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
512 }
513 }
514 }
515 break;
516 default:
517 RTW_INFO("<===mpt_SetTxPower: Illegal channel!!\n");
518 break;
519 }
520 }
521
hal_mpt_SetTxPower(PADAPTER pAdapter)522 void hal_mpt_SetTxPower(PADAPTER pAdapter)
523 {
524 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
525 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
526 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
527
528 if (pHalData->rf_chip < RF_CHIP_MAX) {
529 if (IS_HARDWARE_TYPE_8188E(pAdapter) ||
530 IS_HARDWARE_TYPE_8723B(pAdapter) ||
531 IS_HARDWARE_TYPE_8192E(pAdapter) ||
532 IS_HARDWARE_TYPE_8703B(pAdapter) ||
533 IS_HARDWARE_TYPE_8188F(pAdapter) ||
534 IS_HARDWARE_TYPE_8188GTV(pAdapter)
535 ) {
536
537 RTW_INFO("===> MPT_ProSetTxPower: Old\n");
538
539 mpt_SetTxPower_Old(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
540 mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel);
541
542 } else {
543
544 mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
545 mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);
546 mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel);
547 if(IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
548 RTW_INFO("===> MPT_ProSetTxPower: Jaguar/Jaguar2\n");
549 mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel);
550 }
551 }
552
553 rtw_hal_set_txpwr_done(pAdapter);
554 } else
555 RTW_INFO("RFChipID < RF_CHIP_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);
556
557 odm_clear_txpowertracking_state(pDM_Odm);
558 }
559
hal_mpt_SetDataRate(PADAPTER pAdapter)560 void hal_mpt_SetDataRate(PADAPTER pAdapter)
561 {
562 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
563 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
564 u32 DataRate;
565
566 DataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
567
568 hal_mpt_SwitchRfSetting(pAdapter);
569
570 hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
571 #ifdef CONFIG_RTL8723B
572 if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
573 if (IS_CCK_RATE(DataRate)) {
574 if (pMptCtx->mpt_rf_path == RF_PATH_A)
575 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0x6);
576 else
577 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0x6);
578 } else {
579 if (pMptCtx->mpt_rf_path == RF_PATH_A)
580 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
581 else
582 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
583 }
584 }
585
586 if ((IS_HARDWARE_TYPE_8723BS(pAdapter) &&
587 ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) {
588 if (pMptCtx->mpt_rf_path == RF_PATH_A)
589 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
590 else
591 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
592 }
593 #endif
594 }
595
596 #define RF_PATH_AB 22
597
598 #ifdef CONFIG_RTL8814A
mpt_ToggleIG_8814A(PADAPTER pAdapter)599 void mpt_ToggleIG_8814A(PADAPTER pAdapter)
600 {
601 u8 Path;
602 u32 IGReg = rA_IGI_Jaguar, IGvalue = 0;
603
604 for (Path = 0; Path <= RF_PATH_D; Path++) {
605 switch (Path) {
606 case RF_PATH_B:
607 IGReg = rB_IGI_Jaguar;
608 break;
609 case RF_PATH_C:
610 IGReg = rC_IGI_Jaguar2;
611 break;
612 case RF_PATH_D:
613 IGReg = rD_IGI_Jaguar2;
614 break;
615 default:
616 IGReg = rA_IGI_Jaguar;
617 break;
618 }
619
620 IGvalue = phy_query_bb_reg(pAdapter, IGReg, bMaskByte0);
621 phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue + 2);
622 phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue);
623 }
624 }
625
mpt_SetRFPath_8814A(PADAPTER pAdapter)626 void mpt_SetRFPath_8814A(PADAPTER pAdapter)
627 {
628
629 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
630 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
631 R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
632 R_ANTENNA_SELECT_CCK *p_cck_txrx;
633 u8 ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
634 /*/PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo);*/
635 /*/PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pMgntInfo);*/
636
637 u32 ulAntennaTx = pHalData->antenna_tx_path;
638 u32 ulAntennaRx = pHalData->AntennaRxPath;
639 u8 NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
640
641 if (NssforRate == RF_3TX) {
642 RTW_INFO("===> SetAntenna 3T Rate ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
643
644 switch (ulAntennaTx) {
645 case ANTENNA_BCD:
646 pMptCtx->mpt_rf_path = RF_PATH_BCD;
647 /*pHalData->ValidTxPath = 0x0e;*/
648 phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e); /*/ 0x940[27:16]=12'b0010_0100_0111*/
649 break;
650
651 case ANTENNA_ABC:
652 default:
653 pMptCtx->mpt_rf_path = RF_PATH_ABC;
654 /*pHalData->ValidTxPath = 0x0d;*/
655 phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247); /*/ 0x940[27:16]=12'b0010_0100_0111*/
656 break;
657 }
658
659 } else { /*/if(NssforRate == RF_1TX)*/
660 RTW_INFO("===> SetAntenna for 1T/2T Rate, ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
661 switch (ulAntennaTx) {
662 case ANTENNA_BCD:
663 pMptCtx->mpt_rf_path = RF_PATH_BCD;
664 /*pHalData->ValidTxPath = 0x0e;*/
665 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x7);
666 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0xe);
667 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0xe);
668 break;
669
670 case ANTENNA_BC:
671 pMptCtx->mpt_rf_path = RF_PATH_BC;
672 /*pHalData->ValidTxPath = 0x06;*/
673 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x6);
674 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0x6);
675 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x6);
676 break;
677 case ANTENNA_B:
678 pMptCtx->mpt_rf_path = RF_PATH_B;
679 /*pHalData->ValidTxPath = 0x02;*/
680 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4); /*/ 0xa07[7:4] = 4'b0100*/
681 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002); /*/ 0x93C[31:20]=12'b0000_0000_0010*/
682 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2); /* 0x80C[7:4] = 4'b0010*/
683 break;
684
685 case ANTENNA_C:
686 pMptCtx->mpt_rf_path = RF_PATH_C;
687 /*pHalData->ValidTxPath = 0x04;*/
688 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2); /*/ 0xa07[7:4] = 4'b0010*/
689 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004); /*/ 0x93C[31:20]=12'b0000_0000_0100*/
690 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4); /*/ 0x80C[7:4] = 4'b0100*/
691 break;
692
693 case ANTENNA_D:
694 pMptCtx->mpt_rf_path = RF_PATH_D;
695 /*pHalData->ValidTxPath = 0x08;*/
696 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1); /*/ 0xa07[7:4] = 4'b0001*/
697 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008); /*/ 0x93C[31:20]=12'b0000_0000_1000*/
698 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8); /*/ 0x80C[7:4] = 4'b1000*/
699 break;
700
701 case ANTENNA_A:
702 default:
703 pMptCtx->mpt_rf_path = RF_PATH_A;
704 /*pHalData->ValidTxPath = 0x01;*/
705 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8); /*/ 0xa07[7:4] = 4'b1000*/
706 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001); /*/ 0x93C[31:20]=12'b0000_0000_0001*/
707 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1); /*/ 0x80C[7:4] = 4'b0001*/
708 break;
709 }
710 }
711
712 switch (ulAntennaRx) {
713 case ANTENNA_A:
714 /*pHalData->ValidRxPath = 0x01;*/
715 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
716 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
717 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
718 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
719 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
720 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0);
721 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
722 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
723 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
724 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
725 /*/ CCA related PD_delay_th*/
726 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
727 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
728 break;
729
730 case ANTENNA_B:
731 /*pHalData->ValidRxPath = 0x02;*/
732 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
733 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
734 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
735 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
736 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
737 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1);
738 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
739 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
740 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
741 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
742 /*/ CCA related PD_delay_th*/
743 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
744 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
745 break;
746
747 case ANTENNA_C:
748 /*pHalData->ValidRxPath = 0x04;*/
749 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
750 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
751 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44);
752 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
753 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
754 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2);
755 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
756 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
757 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
758 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
759 /*/ CCA related PD_delay_th*/
760 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
761 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
762 break;
763
764 case ANTENNA_D:
765 /*pHalData->ValidRxPath = 0x08;*/
766 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
767 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
768 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88);
769 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
770 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
771 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3);
772 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
773 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
774 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
775 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
776 /*/ CCA related PD_delay_th*/
777 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
778 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
779 break;
780
781 case ANTENNA_BC:
782 /*pHalData->ValidRxPath = 0x06;*/
783 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
784 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
785 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66);
786 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
787 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
788 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
789 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
790 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
791 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
792 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
793 /*/ CCA related PD_delay_th*/
794 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
795 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
796 break;
797
798 case ANTENNA_CD:
799 /*pHalData->ValidRxPath = 0x0C;*/
800 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
801 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
802 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc);
803 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
804 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
805 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB);
806 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
807 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
808 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
809 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
810 /*/ CCA related PD_delay_th*/
811 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
812 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
813 break;
814
815 case ANTENNA_BCD:
816 /*pHalData->ValidRxPath = 0x0e;*/
817 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
818 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
819 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee);
820 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
821 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
822 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
823 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
824 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
825 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
826 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/
827 /*/ CCA related PD_delay_th*/
828 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
829 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
830 break;
831
832 case ANTENNA_ABCD:
833 /*pHalData->ValidRxPath = 0x0f;*/
834 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
835 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
836 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff);
837 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
838 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
839 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1);
840 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
841 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
842 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
843 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
844 /*/ CCA related PD_delay_th*/
845 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
846 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
847 break;
848
849 default:
850 break;
851 }
852
853 PHY_Set_SecCCATH_by_RXANT_8814A(pAdapter, ulAntennaRx);
854
855 mpt_ToggleIG_8814A(pAdapter);
856 }
857
858 #endif /* CONFIG_RTL8814A */
859 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
860 void
mpt_SetSingleTone_8814A(PADAPTER pAdapter,BOOLEAN bSingleTone,BOOLEAN bEnPMacTx)861 mpt_SetSingleTone_8814A(
862 PADAPTER pAdapter,
863 BOOLEAN bSingleTone,
864 BOOLEAN bEnPMacTx)
865 {
866
867 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
868 u8 StartPath = RF_PATH_A, EndPath = RF_PATH_A, path;
869 static u32 regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0;
870
871 if (bSingleTone) {
872 regIG0 = phy_query_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord); /*/ 0xC1C[31:21]*/
873 regIG1 = phy_query_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord); /*/ 0xE1C[31:21]*/
874 regIG2 = phy_query_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord); /*/ 0x181C[31:21]*/
875 regIG3 = phy_query_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord); /*/ 0x1A1C[31:21]*/
876
877 switch (pMptCtx->mpt_rf_path) {
878 case RF_PATH_A:
879 case RF_PATH_B:
880 case RF_PATH_C:
881 case RF_PATH_D:
882 StartPath = pMptCtx->mpt_rf_path;
883 EndPath = pMptCtx->mpt_rf_path;
884 break;
885 case RF_PATH_AB:
886 EndPath = RF_PATH_B;
887 break;
888 case RF_PATH_BC:
889 StartPath = RF_PATH_B;
890 EndPath = RF_PATH_C;
891 break;
892 case RF_PATH_ABC:
893 EndPath = RF_PATH_C;
894 break;
895 case RF_PATH_BCD:
896 StartPath = RF_PATH_B;
897 EndPath = RF_PATH_D;
898 break;
899 case RF_PATH_ABCD:
900 EndPath = RF_PATH_D;
901 break;
902 }
903
904 if (bEnPMacTx == FALSE) {
905 hal_mpt_SetContinuousTx(pAdapter, _TRUE);
906 issue_nulldata(pAdapter, NULL, 1, 3, 500);
907 }
908
909 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/
910
911 for (path = StartPath; path <= EndPath; path++) {
912 phy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
913 phy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
914
915 phy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
916 }
917
918 phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/
919 phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/
920 phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/
921 phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/
922 } else {
923 switch (pMptCtx->mpt_rf_path) {
924 case RF_PATH_A:
925 case RF_PATH_B:
926 case RF_PATH_C:
927 case RF_PATH_D:
928 StartPath = pMptCtx->mpt_rf_path;
929 EndPath = pMptCtx->mpt_rf_path;
930 break;
931 case RF_PATH_AB:
932 EndPath = RF_PATH_B;
933 break;
934 case RF_PATH_BC:
935 StartPath = RF_PATH_B;
936 EndPath = RF_PATH_C;
937 break;
938 case RF_PATH_ABC:
939 EndPath = RF_PATH_C;
940 break;
941 case RF_PATH_BCD:
942 StartPath = RF_PATH_B;
943 EndPath = RF_PATH_D;
944 break;
945 case RF_PATH_ABCD:
946 EndPath = RF_PATH_D;
947 break;
948 }
949 for (path = StartPath; path <= EndPath; path++)
950 phy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x0); /* RF LO disabled */
951
952 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/
953
954 if (bEnPMacTx == FALSE) {
955 if(IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
956 #ifdef PHYDM_MP_SUPPORT
957 phydm_stop_ofdm_cont_tx(pAdapter);
958 pMptCtx->bCckContTx = FALSE;
959 pMptCtx->bOfdmContTx = FALSE;
960 #endif
961 } else
962 hal_mpt_SetContinuousTx(pAdapter, _FALSE);
963 }
964
965 phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/
966 phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/
967 phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/
968 phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/
969 }
970 }
971
972 #endif
973
974 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
mpt_SetRFPath_8812A(PADAPTER pAdapter)975 void mpt_SetRFPath_8812A(PADAPTER pAdapter)
976 {
977 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
978 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
979 struct mp_priv *pmp = &pAdapter->mppriv;
980 u8 channel = pmp->channel;
981 u8 bandwidth = pmp->bandwidth;
982 u8 eLNA_2g = pHalData->ExternalLNA_2G;
983 u32 ulAntennaTx, ulAntennaRx;
984 u32 reg0xC50 = 0;
985
986 ulAntennaTx = pHalData->antenna_tx_path;
987 ulAntennaRx = pHalData->AntennaRxPath;
988
989 switch (ulAntennaTx) {
990 case ANTENNA_A:
991 pMptCtx->mpt_rf_path = RF_PATH_A;
992 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
993 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
994 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
995 break;
996 case ANTENNA_B:
997 pMptCtx->mpt_rf_path = RF_PATH_B;
998 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222);
999 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
1000 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1);
1001 break;
1002 case ANTENNA_AB:
1003 pMptCtx->mpt_rf_path = RF_PATH_AB;
1004 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333);
1005 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
1006 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
1007 break;
1008 default:
1009 pMptCtx->mpt_rf_path = RF_PATH_AB;
1010 RTW_INFO("Unknown Tx antenna.\n");
1011 break;
1012 }
1013
1014 switch (ulAntennaRx) {
1015 case ANTENNA_A:
1016 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
1017 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
1018 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
1019 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
1020
1021 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
1022 reg0xC50 = phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
1023 phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
1024 phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50);
1025
1026 /* set PWED_TH for BB Yn user guide R29 */
1027 if (IS_HARDWARE_TYPE_8812(pAdapter)) {
1028 if (channel <= 14) { /* 2.4G */
1029 if (bandwidth == CHANNEL_WIDTH_20
1030 && eLNA_2g == 0) {
1031 /* 0x830[3:1]=3'b010 */
1032 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
1033 } else
1034 /* 0x830[3:1]=3'b100 */
1035 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1036 } else
1037 /* 0x830[3:1]=3'b100 for 5G */
1038 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1039 }
1040 break;
1041 case ANTENNA_B:
1042 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
1043 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */
1044 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1);
1045 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
1046
1047 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
1048 reg0xC50 = phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
1049 phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
1050 phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50);
1051
1052 /* set PWED_TH for BB Yn user guide R29 */
1053 if (IS_HARDWARE_TYPE_8812(pAdapter)) {
1054 if (channel <= 14) {
1055 if (bandwidth == CHANNEL_WIDTH_20
1056 && eLNA_2g == 0) {
1057 /* 0x830[3:1]=3'b010 */
1058 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
1059 } else
1060 /* 0x830[3:1]=3'b100 */
1061 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1062 } else
1063 /* 0x830[3:1]=3'b100 for 5G */
1064 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1065 }
1066 break;
1067 case ANTENNA_AB:
1068 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33);
1069 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/
1070 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
1071 /* set PWED_TH for BB Yn user guide R29 */
1072 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1073 break;
1074 default:
1075 RTW_INFO("Unknown Rx antenna.\n");
1076 break;
1077 }
1078
1079 if (pHalData->rfe_type == 5 || pHalData->rfe_type == 1) {
1080 if (ulAntennaTx == ANTENNA_A || ulAntennaTx == ANTENNA_AB) {
1081 /* WiFi */
1082 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x2);
1083 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
1084 } else {
1085 /* BT */
1086 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x1);
1087 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
1088 }
1089 }
1090 }
1091 #endif
1092
1093 #ifdef CONFIG_RTL8723B
mpt_SetRFPath_8723B(PADAPTER pAdapter)1094 void mpt_SetRFPath_8723B(PADAPTER pAdapter)
1095 {
1096 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1097 u32 ulAntennaTx, ulAntennaRx;
1098 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1099 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1100 struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1101 u8 i;
1102
1103 ulAntennaTx = pHalData->antenna_tx_path;
1104 ulAntennaRx = pHalData->AntennaRxPath;
1105
1106 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1107 RTW_INFO("This RF chip ID is not supported\n");
1108 return;
1109 }
1110
1111 switch (pAdapter->mppriv.antenna_tx) {
1112 case ANTENNA_A: { /*/ Actually path S1 (Wi-Fi)*/
1113 pMptCtx->mpt_rf_path = RF_PATH_A;
1114 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1115 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1116
1117 for (i = 0; i < 3; ++i) {
1118 u32 offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
1119 u32 data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][1];
1120
1121 if (offset != 0) {
1122 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1123 RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1124 }
1125 }
1126 for (i = 0; i < 2; ++i) {
1127 u32 offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
1128 u32 data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][1];
1129
1130 if (offset != 0) {
1131 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1132 RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1133 }
1134 }
1135 }
1136 break;
1137 case ANTENNA_B: { /*/ Actually path S0 (BT)*/
1138 u32 offset;
1139 u32 data;
1140
1141 pMptCtx->mpt_rf_path = RF_PATH_B;
1142 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1143 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/
1144
1145 for (i = 0; i < 3; ++i) {
1146 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1147 offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
1148 data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][1];
1149 if (pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][0] != 0) {
1150 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1151 RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1152 }
1153 }
1154 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1155 for (i = 0; i < 2; ++i) {
1156 offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
1157 data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][1];
1158 if (pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][0] != 0) {
1159 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1160 RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1161 }
1162 }
1163 }
1164 break;
1165 default:
1166 pMptCtx->mpt_rf_path = RF_PATH_AB;
1167 break;
1168 }
1169 }
1170 #endif
1171
1172 #ifdef CONFIG_RTL8703B
mpt_SetRFPath_8703B(PADAPTER pAdapter)1173 void mpt_SetRFPath_8703B(PADAPTER pAdapter)
1174 {
1175 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1176 u32 ulAntennaTx, ulAntennaRx;
1177 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1178 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1179 struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1180 u8 i;
1181
1182 ulAntennaTx = pHalData->antenna_tx_path;
1183 ulAntennaRx = pHalData->AntennaRxPath;
1184
1185 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1186 RTW_INFO("This RF chip ID is not supported\n");
1187 return;
1188 }
1189
1190 switch (pAdapter->mppriv.antenna_tx) {
1191 case ANTENNA_A: { /* Actually path S1 (Wi-Fi) */
1192 pMptCtx->mpt_rf_path = RF_PATH_A;
1193 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1194 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1195
1196 for (i = 0; i < 3; ++i) {
1197 u32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
1198 u32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
1199
1200 if (offset != 0) {
1201 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1202 RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1203 }
1204
1205 }
1206 for (i = 0; i < 2; ++i) {
1207 u32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
1208 u32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
1209
1210 if (offset != 0) {
1211 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1212 RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1213 }
1214 }
1215 }
1216 break;
1217 case ANTENNA_B: { /* Actually path S0 (BT)*/
1218 pMptCtx->mpt_rf_path = RF_PATH_B;
1219 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1220 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */
1221
1222 for (i = 0; i < 3; ++i) {
1223 u32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
1224 u32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
1225
1226 if (pRFCalibrateInfo->tx_iqc_8703b[i][0] != 0) {
1227 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1228 RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1229 }
1230 }
1231 for (i = 0; i < 2; ++i) {
1232 u32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
1233 u32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
1234
1235 if (pRFCalibrateInfo->rx_iqc_8703b[i][0] != 0) {
1236 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1237 RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1238 }
1239 }
1240 }
1241 break;
1242 default:
1243 pMptCtx->mpt_rf_path = RF_PATH_AB;
1244 break;
1245 }
1246
1247 }
1248 #endif
1249
1250 #ifdef CONFIG_RTL8723D
mpt_SetRFPath_8723D(PADAPTER pAdapter)1251 void mpt_SetRFPath_8723D(PADAPTER pAdapter)
1252 {
1253 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1254 u8 p = 0, i = 0;
1255 u32 ulAntennaTx, ulAntennaRx, offset = 0, data = 0, val32 = 0;
1256 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1257 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1258 struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1259
1260 ulAntennaTx = pHalData->antenna_tx_path;
1261 ulAntennaRx = pHalData->AntennaRxPath;
1262
1263 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1264 RTW_INFO("This RF chip ID is not supported\n");
1265 return;
1266 }
1267
1268 switch (pAdapter->mppriv.antenna_tx) {
1269 /* Actually path S1 (Wi-Fi) */
1270 case ANTENNA_A: {
1271 pMptCtx->mpt_rf_path = RF_PATH_A;
1272 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0);
1273 }
1274 break;
1275 /* Actually path S0 (BT) */
1276 case ANTENNA_B: {
1277 pMptCtx->mpt_rf_path = RF_PATH_B;
1278 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0xA);
1279
1280 }
1281 break;
1282 default:
1283 pMptCtx->mpt_rf_path = RF_PATH_AB;
1284 break;
1285 }
1286 }
1287 #endif
1288
mpt_SetRFPath_819X(PADAPTER pAdapter)1289 void mpt_SetRFPath_819X(PADAPTER pAdapter)
1290 {
1291 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1292 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1293 u32 ulAntennaTx, ulAntennaRx;
1294 R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
1295 R_ANTENNA_SELECT_CCK *p_cck_txrx;
1296 u8 r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
1297 u8 chgTx = 0, chgRx = 0;
1298 u32 r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
1299
1300 ulAntennaTx = pHalData->antenna_tx_path;
1301 ulAntennaRx = pHalData->AntennaRxPath;
1302
1303 p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;
1304 p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;
1305
1306 p_ofdm_tx->r_ant_ht1 = 0x1;
1307 p_ofdm_tx->r_ant_ht2 = 0x2;/*Second TX RF path is A*/
1308 p_ofdm_tx->r_ant_non_ht = 0x3;/*/ 0x1+0x2=0x3 */
1309
1310 switch (ulAntennaTx) {
1311 case ANTENNA_A:
1312 p_ofdm_tx->r_tx_antenna = 0x1;
1313 r_ofdm_tx_en_val = 0x1;
1314 p_ofdm_tx->r_ant_l = 0x1;
1315 p_ofdm_tx->r_ant_ht_s1 = 0x1;
1316 p_ofdm_tx->r_ant_non_ht_s1 = 0x1;
1317 p_cck_txrx->r_ccktx_enable = 0x8;
1318 chgTx = 1;
1319 /*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
1320 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1321 {
1322 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1323 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
1324 r_ofdm_tx_en_val = 0x3;
1325 /*/ Power save*/
1326 /*/cosa r_ant_select_ofdm_val = 0x11111111;*/
1327 /*/ We need to close RFB by SW control*/
1328 if (pHalData->rf_type == RF_2T2R) {
1329 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1330 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
1331 phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
1332 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1333 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
1334 }
1335 }
1336 pMptCtx->mpt_rf_path = RF_PATH_A;
1337 break;
1338 case ANTENNA_B:
1339 p_ofdm_tx->r_tx_antenna = 0x2;
1340 r_ofdm_tx_en_val = 0x2;
1341 p_ofdm_tx->r_ant_l = 0x2;
1342 p_ofdm_tx->r_ant_ht_s1 = 0x2;
1343 p_ofdm_tx->r_ant_non_ht_s1 = 0x2;
1344 p_cck_txrx->r_ccktx_enable = 0x4;
1345 chgTx = 1;
1346 /*/ From SD3 Willis suggestion !!! Set RF A as standby*/
1347 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1348 {
1349 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
1350 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1351
1352 /*/ 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.*/
1353 /*/ 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control*/
1354 if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
1355 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
1356 phy_set_bb_reg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
1357 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1358 /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1359 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
1360 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1361 }
1362 }
1363 pMptCtx->mpt_rf_path = RF_PATH_B;
1364 break;
1365 case ANTENNA_AB:/*/ For 8192S*/
1366 p_ofdm_tx->r_tx_antenna = 0x3;
1367 r_ofdm_tx_en_val = 0x3;
1368 p_ofdm_tx->r_ant_l = 0x3;
1369 p_ofdm_tx->r_ant_ht_s1 = 0x3;
1370 p_ofdm_tx->r_ant_non_ht_s1 = 0x3;
1371 p_cck_txrx->r_ccktx_enable = 0xC;
1372 chgTx = 1;
1373 /*/ From SD3Willis suggestion !!! Set RF B as standby*/
1374 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1375 {
1376 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1377 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1378 /* Disable Power save*/
1379 /*cosa r_ant_select_ofdm_val = 0x3321333;*/
1380 /* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control*/
1381 if (pHalData->rf_type == RF_2T2R) {
1382 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1383
1384 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1385 /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1386 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1387 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1388 }
1389 }
1390 pMptCtx->mpt_rf_path = RF_PATH_AB;
1391 break;
1392 default:
1393 break;
1394 }
1395 #if 0
1396 /* r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */
1397 /* r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */
1398 /* r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D */
1399 #endif
1400 switch (ulAntennaRx) {
1401 case ANTENNA_A:
1402 r_rx_antenna_ofdm = 0x1; /* A*/
1403 p_cck_txrx->r_cckrx_enable = 0x0; /* default: A*/
1404 p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A*/
1405 chgRx = 1;
1406 break;
1407 case ANTENNA_B:
1408 r_rx_antenna_ofdm = 0x2; /*/ B*/
1409 p_cck_txrx->r_cckrx_enable = 0x1; /*/ default: B*/
1410 p_cck_txrx->r_cckrx_enable_2 = 0x1; /*/ option: B*/
1411 chgRx = 1;
1412 break;
1413 case ANTENNA_AB:/*/ For 8192S and 8192E/U...*/
1414 r_rx_antenna_ofdm = 0x3;/*/ AB*/
1415 p_cck_txrx->r_cckrx_enable = 0x0;/*/ default:A*/
1416 p_cck_txrx->r_cckrx_enable_2 = 0x1;/*/ option:B*/
1417 chgRx = 1;
1418 break;
1419 default:
1420 break;
1421 }
1422
1423
1424 if (chgTx && chgRx) {
1425 switch (pHalData->rf_chip) {
1426 case RF_8225:
1427 case RF_8256:
1428 case RF_6052:
1429 /*/r_ant_sel_cck_val = r_ant_select_cck_val;*/
1430 phy_set_bb_reg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); /*/OFDM Tx*/
1431 phy_set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); /*/OFDM Tx*/
1432 phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
1433 phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
1434 if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1435 phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
1436 phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
1437 }
1438 phy_set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/
1439 break;
1440
1441 default:
1442 RTW_INFO("Unsupported RFChipID for switching antenna.\n");
1443 break;
1444 }
1445 }
1446 } /* MPT_ProSetRFPath */
1447
1448 #ifdef CONFIG_RTL8192F
1449
mpt_set_rfpath_8192f(PADAPTER pAdapter)1450 void mpt_set_rfpath_8192f(PADAPTER pAdapter)
1451 {
1452 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1453 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1454
1455 u16 ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
1456 u8 NssforRate, odmNssforRate;
1457 u32 ulAntennaTx, ulAntennaRx;
1458 enum bb_path RxAntToPhyDm;
1459 enum bb_path TxAntToPhyDm;
1460
1461 ulAntennaTx = pHalData->antenna_tx_path;
1462 ulAntennaRx = pHalData->AntennaRxPath;
1463 NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
1464
1465 if (pHalData->rf_chip >= RF_TYPE_MAX)
1466 RTW_INFO("This RF chip ID is not supported\n");
1467
1468 switch (ulAntennaTx) {
1469 case ANTENNA_A:
1470 pMptCtx->mpt_rf_path = RF_PATH_A;
1471 TxAntToPhyDm = BB_PATH_A;
1472 break;
1473 case ANTENNA_B:
1474 pMptCtx->mpt_rf_path = RF_PATH_B;
1475 TxAntToPhyDm = BB_PATH_B;
1476 break;
1477 case ANTENNA_AB:
1478 pMptCtx->mpt_rf_path = RF_PATH_AB;
1479 TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1480 break;
1481 default:
1482 pMptCtx->mpt_rf_path = RF_PATH_AB;
1483 TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1484 break;
1485 }
1486
1487 switch (ulAntennaRx) {
1488 case ANTENNA_A:
1489 RxAntToPhyDm = BB_PATH_A;
1490 break;
1491 case ANTENNA_B:
1492 RxAntToPhyDm = BB_PATH_B;
1493 break;
1494 case ANTENNA_AB:
1495 RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1496 break;
1497 default:
1498 RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1499 break;
1500 }
1501
1502 phydm_api_trx_mode(GET_PDM_ODM(pAdapter), TxAntToPhyDm, RxAntToPhyDm, TxAntToPhyDm);
1503
1504 }
1505
1506 #endif
1507
hal_mpt_SetAntenna(PADAPTER pAdapter)1508 void hal_mpt_SetAntenna(PADAPTER pAdapter)
1509
1510 {
1511 RTW_INFO("Do %s\n", __func__);
1512 #ifdef CONFIG_RTL8822C
1513 if (IS_HARDWARE_TYPE_8822C(pAdapter)) {
1514 rtl8822c_mp_config_rfpath(pAdapter);
1515 return;
1516 }
1517 #endif
1518 #ifdef CONFIG_RTL8814A
1519 if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
1520 mpt_SetRFPath_8814A(pAdapter);
1521 return;
1522 }
1523 #endif
1524 #ifdef CONFIG_RTL8822B
1525 if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
1526 rtl8822b_mp_config_rfpath(pAdapter);
1527 return;
1528 }
1529 #endif
1530 #ifdef CONFIG_RTL8821C
1531 if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
1532 rtl8821c_mp_config_rfpath(pAdapter);
1533 return;
1534 }
1535 #endif
1536 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1537 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {
1538 mpt_SetRFPath_8812A(pAdapter);
1539 return;
1540 }
1541 #endif
1542 #ifdef CONFIG_RTL8723B
1543 if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1544 mpt_SetRFPath_8723B(pAdapter);
1545 return;
1546 }
1547 #endif
1548
1549 #ifdef CONFIG_RTL8703B
1550 if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1551 mpt_SetRFPath_8703B(pAdapter);
1552 return;
1553 }
1554 #endif
1555
1556 #ifdef CONFIG_RTL8723D
1557 if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1558 mpt_SetRFPath_8723D(pAdapter);
1559 return;
1560 }
1561 #endif
1562
1563 #ifdef CONFIG_RTL8192F
1564 if (IS_HARDWARE_TYPE_8192F(pAdapter)) {
1565 mpt_set_rfpath_8192f(pAdapter);
1566 return;
1567 }
1568 #endif
1569
1570 #ifdef CONFIG_RTL8814B
1571 if (IS_HARDWARE_TYPE_8814B(pAdapter)) {
1572 rtl8814b_mp_config_rfpath(pAdapter);
1573 return;
1574 }
1575 #endif
1576
1577 /* else if (IS_HARDWARE_TYPE_8821B(pAdapter))
1578 mpt_SetRFPath_8821B(pAdapter);
1579 Prepare for 8822B
1580 else if (IS_HARDWARE_TYPE_8822B(Context))
1581 mpt_SetRFPath_8822B(Context);
1582 */
1583 mpt_SetRFPath_819X(pAdapter);
1584 RTW_INFO("mpt_SetRFPath_819X Do %s\n", __func__);
1585 }
1586
hal_mpt_SetThermalMeter(PADAPTER pAdapter,u8 target_ther)1587 s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
1588 {
1589 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1590
1591 if (!netif_running(pAdapter->pnetdev)) {
1592 return _FAIL;
1593 }
1594
1595
1596 if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
1597 return _FAIL;
1598 }
1599
1600 target_ther &= 0xff;
1601
1602 pHalData->eeprom_thermal_meter = target_ther;
1603
1604 return _SUCCESS;
1605 }
1606
1607
hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)1608 void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)
1609 {
1610 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
1611 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);
1612 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x0);
1613 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);
1614 } else
1615 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT17 | BIT16, 0x03);
1616
1617 }
1618
1619
hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter,u8 rf_path)1620 u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter, u8 rf_path)
1621
1622 {
1623 struct dm_struct *p_dm_odm = adapter_to_phydm(pAdapter);
1624
1625 u32 ThermalValue = 0;
1626 s32 thermal_value_temp = 0;
1627 s8 thermal_offset = 0;
1628 u32 thermal_reg_mask = 0;
1629
1630 if (IS_8822C_SERIES(GET_HAL_DATA(pAdapter)->version_id))
1631 thermal_reg_mask = 0x007e; /*0x42: RF Reg[6:1], 35332(themal K & bias k & power trim) & 35325(tssi )*/
1632 else
1633 thermal_reg_mask = 0xfc00; /*0x42: RF Reg[15:10]*/
1634
1635 ThermalValue = (u8)phy_query_rf_reg(pAdapter, rf_path, 0x42, thermal_reg_mask);
1636
1637 thermal_offset = phydm_get_thermal_offset(p_dm_odm);
1638
1639 thermal_value_temp = ThermalValue + thermal_offset;
1640
1641 if (thermal_value_temp > 63)
1642 ThermalValue = 63;
1643 else if (thermal_value_temp < 0)
1644 ThermalValue = 0;
1645 else
1646 ThermalValue = thermal_value_temp;
1647
1648 return (u8)ThermalValue;
1649 }
1650
1651
hal_mpt_GetThermalMeter(PADAPTER pAdapter,u8 rfpath,u8 * value)1652 void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 rfpath, u8 *value)
1653 {
1654 #if 0
1655 fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
1656 rtw_msleep_os(1000);
1657 fw_cmd_data(pAdapter, value, 1);
1658 *value &= 0xFF;
1659 #else
1660 hal_mpt_TriggerRFThermalMeter(pAdapter);
1661 rtw_msleep_os(1000);
1662 *value = hal_mpt_ReadRFThermalMeter(pAdapter, rfpath);
1663 #endif
1664
1665 }
1666
1667
hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter,u8 bStart)1668 void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
1669 {
1670 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1671
1672 pAdapter->mppriv.mpt_ctx.bSingleCarrier = bStart;
1673
1674 if (bStart) {/*/ Start Single Carrier.*/
1675 /*/ Start Single Carrier.*/
1676 /*/ 1. if OFDM block on?*/
1677 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
1678 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/
1679
1680 /*/ 2. set CCK test mode off, set to CCK normal mode*/
1681 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
1682
1683 /*/ 3. turn on scramble setting*/
1684 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
1685
1686 /*/ 4. Turn On Continue Tx and turn off the other test modes.*/
1687 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1688 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
1689 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_SingleCarrier);
1690 else
1691 #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1692 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleCarrier);
1693
1694 } else {
1695 /*/ Stop Single Carrier.*/
1696 /*/ Stop Single Carrier.*/
1697 /*/ Turn off all test modes.*/
1698 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1699 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
1700 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1701 else
1702 #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1703 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1704
1705 rtw_msleep_os(10);
1706 /*/BB Reset*/
1707 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1708 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1709 }
1710 }
1711
1712
hal_mpt_SetSingleToneTx(PADAPTER pAdapter,u8 bStart)1713 void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
1714 {
1715 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1716 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1717 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1718 u32 ulAntennaTx = pHalData->antenna_tx_path;
1719 static u32 regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0;
1720 u8 rfPath;
1721
1722 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
1723 #ifdef PHYDM_MP_SUPPORT
1724 #ifdef CONFIG_RTL8814B
1725 if(pHalData->current_channel_bw == CHANNEL_WIDTH_80_80)
1726 {
1727 /* @Tx mode: RF0x00[19:16]=4'b0010 */
1728 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x0, 0xF0000, 0x2);
1729 /* @Lowest RF gain index: RF_0x0[4:0] = 0*/
1730 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x0, 0x1F, 0x0);
1731 /* @RF LO enabled */
1732 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x58, BIT(1), 0x1);
1733 /* @SYN1 */
1734 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x0, 0xF0000, 0x2);
1735 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x0, 0x1F, 0x0);
1736 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x58, BIT(1), 0x1);
1737 }
1738 #endif
1739 phydm_mp_set_single_tone(pDM_Odm, bStart, pMptCtx->mpt_rf_path);
1740 #endif
1741 return;
1742 }
1743
1744 switch (ulAntennaTx) {
1745 case ANTENNA_B:
1746 rfPath = RF_PATH_B;
1747 break;
1748 case ANTENNA_C:
1749 rfPath = RF_PATH_C;
1750 break;
1751 case ANTENNA_D:
1752 rfPath = RF_PATH_D;
1753 break;
1754 case ANTENNA_A:
1755 default:
1756 rfPath = RF_PATH_A;
1757 break;
1758 }
1759
1760 pAdapter->mppriv.mpt_ctx.is_single_tone = bStart;
1761 if (bStart) {
1762 /*/ Start Single Tone.*/
1763 /*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/
1764 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1765 regRF = phy_query_rf_reg(pAdapter, rfPath, lna_low_gain_3, bRFRegOffsetMask);
1766 phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1767 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
1768 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
1769 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
1770 /*/Set MAC REG 88C: Prevent SingleTone Fail*/
1771 phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0xF);
1772 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO disabled*/
1773 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1774 } else if (IS_HARDWARE_TYPE_8192F(pAdapter)) { /* USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
1775 #ifdef CONFIG_RTL8192F
1776 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x1);
1777 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x1);
1778 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x1);
1779 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x1);
1780 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x1);
1781 phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x1);
1782 phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0xF);
1783 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x1); /* RF LO disabled*/
1784 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /* Tx mode*/
1785 #endif
1786 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1787 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1788 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1789 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/
1790 } else {
1791 /*/ S0/S1 both use PATH A to configure*/
1792 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1793 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/
1794 }
1795 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1796 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1797 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */
1798 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */
1799 }
1800 } else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
1801 /*Set BB REG 88C: Prevent SingleTone Fail*/
1802 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF);
1803 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1);
1804 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2);
1805
1806 } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1807 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1808 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1809 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
1810 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x1);
1811 } else {/* S0/S1 both use PATH A to configure */
1812 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1813 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
1814 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x1);
1815 }
1816 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
1817 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1818 u8 p = RF_PATH_A;
1819
1820 regRF = phy_query_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);
1821 regBB0 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);
1822 regBB1 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);
1823 regBB2 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1824 regBB3 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1825
1826 phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x0); /*/ Disable CCK and OFDM*/
1827
1828 if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
1829 for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
1830 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1831 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1832 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1833 }
1834 } else {
1835 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1836 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1837 #ifdef CONFIG_RTL8821C
1838 if (IS_HARDWARE_TYPE_8821C(pAdapter) && pDM_Odm->current_rf_set_8821c == SWITCH_TO_BTG)
1839 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x75, BIT16, 0x1); /* RF LO (for BTG) enabled */
1840 else
1841 #endif
1842 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1843 }
1844 if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
1845 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777); /* 0xCB0=0x77777777*/
1846 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777); /* 0xEB0=0x77777777*/
1847 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777); /* 0xCB4[15:0] = 0x7777*/
1848 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777); /* 0xEB4[15:0] = 0x7777*/
1849 phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xFFF, 0xb); /* 0xCBC[23:16] = 0x12*/
1850 phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xFFF, 0x830); /* 0xEBC[23:16] = 0x12*/
1851 } else if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
1852 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xF0F0, 0x707); /* 0xCB0[[15:12, 7:4] = 0x707*/
1853
1854 if (pHalData->external_pa_5g)
1855 {
1856 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
1857 }
1858 else if (pHalData->ExternalPA_2G)
1859 {
1860 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
1861 }
1862 } else {
1863 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1864 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1865
1866 if (pHalData->external_pa_5g) {
1867 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/
1868 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/
1869 } else if (pHalData->ExternalPA_2G) {
1870 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/
1871 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/
1872 }
1873 }
1874 #endif
1875 }
1876 #if defined(CONFIG_RTL8814A)
1877 else if (IS_HARDWARE_TYPE_8814A(pAdapter))
1878 mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE);
1879 #endif
1880 else /*/ Turn On SingleTone and turn off the other test modes.*/
1881 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone);
1882
1883 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1884 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1885
1886 } else {/*/ Stop Single Ton e.*/
1887
1888 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1889 phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, bRFRegOffsetMask, regRF);
1890 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
1891 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
1892 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1893 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/
1894 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0);/*/ RF LO disabled */
1895 /*/ RESTORE MAC REG 88C: Enable RF Functions*/
1896 phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0x0);
1897 } else if (IS_HARDWARE_TYPE_8192F(pAdapter)){
1898 #ifdef CONFIG_RTL8192F
1899 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x0);
1900 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x0);
1901 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x0);
1902 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x0);
1903 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x0);
1904 phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x0);
1905 phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0x0);
1906 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x0); /* RF LO disabled*/
1907 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /* Rx mode*/
1908 #endif
1909 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1910 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1911 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1912 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/
1913 } else {
1914 /*/ S0/S1 both use PATH A to configure*/
1915 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1916 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/
1917 }
1918 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1919 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1920 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */
1921 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */
1922 }
1923 } else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
1924 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /*Tx mode*/
1925 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0); /*RF LO disabled*/
1926 /*Set BB REG 88C: Prevent SingleTone Fail*/
1927 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc);
1928 } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1929 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1930 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
1931 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
1932 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x0);
1933 } else { /* S0/S1 both use PATH A to configure */
1934 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
1935 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
1936 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x0);
1937 }
1938 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
1939 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1940 u8 p = RF_PATH_A;
1941
1942 phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x3); /*/ Disable CCK and OFDM*/
1943
1944 if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
1945 for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
1946 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
1947 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
1948 }
1949 } else {
1950 p = pMptCtx->mpt_rf_path;
1951 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
1952
1953 if (IS_HARDWARE_TYPE_8821C(pAdapter))
1954 phy_set_rf_reg(pAdapter, p, 0x75, BIT16, 0x0); /* RF LO (for BTG) disabled */
1955
1956 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
1957 }
1958
1959 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0);
1960 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1);
1961 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB2);
1962 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB3);
1963
1964 if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
1965 RTW_INFO("Restore RFE control Pin cbc\n");
1966 phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xfff, 0x0);
1967 phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xfff, 0x0);
1968 }
1969 #endif
1970 }
1971 #if defined(CONFIG_RTL8814A)
1972 else if (IS_HARDWARE_TYPE_8814A(pAdapter))
1973 mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE);
1974
1975 else/*/ Turn off all test modes.*/
1976 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1977 #endif
1978 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1979 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1980
1981 }
1982 }
1983
hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter,u8 bStart)1984 void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
1985 {
1986 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1987 struct dm_struct *pdm_odm = &pHalData->odmpriv;
1988 u8 Rate;
1989
1990 pAdapter->mppriv.mpt_ctx.is_carrier_suppression = bStart;
1991
1992 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
1993 #ifdef PHYDM_MP_SUPPORT
1994 phydm_mp_set_carrier_supp(pdm_odm, bStart, pAdapter->mppriv.rateidx);
1995 #endif
1996 return;
1997 }
1998
1999 Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
2000 if (bStart) {/* Start Carrier Suppression.*/
2001 if (Rate <= MPT_RATE_11M) {
2002 /*/ 1. if CCK block on?*/
2003 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
2004 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
2005
2006 /*/Turn Off All Test Mode*/
2007 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
2008 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /* rSingleTone_ContTx_Jaguar*/
2009 else
2010 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2011
2012 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/
2013 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); /*/turn off scramble setting*/
2014
2015 /*/Set CCK Tx Test Rate*/
2016 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); /*/Set FTxRate to 1Mbps*/
2017 }
2018
2019 /*Set for dynamic set Power index*/
2020 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2021 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2022
2023 } else {/* Stop Carrier Suppression.*/
2024
2025 if (Rate <= MPT_RATE_11M) {
2026 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
2027 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
2028
2029 /*BB Reset*/
2030 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2031 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2032 }
2033 /*Stop for dynamic set Power index*/
2034 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2035 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2036 }
2037 RTW_INFO("\n MPT_ProSetCarrierSupp() is finished.\n");
2038 }
2039
hal_mpt_query_phytxok(PADAPTER pAdapter)2040 u32 hal_mpt_query_phytxok(PADAPTER pAdapter)
2041 {
2042 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2043 RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
2044 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2045 u16 count = 0;
2046
2047 #ifdef PHYDM_MP_SUPPORT
2048 struct dm_struct *dm = (struct dm_struct *)&pHalData->odmpriv;
2049 struct phydm_mp *mp = &dm->dm_mp_table;
2050
2051 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
2052 phydm_mp_get_tx_ok(&pHalData->odmpriv, pAdapter->mppriv.rateidx);
2053 count = mp->tx_phy_ok_cnt;
2054
2055 } else
2056 #endif
2057 {
2058
2059 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2060 count = phy_query_bb_reg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/
2061 else
2062 count = phy_query_bb_reg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/
2063 }
2064
2065 if (count > 50000) {
2066 rtw_reset_phy_trx_ok_counters(pAdapter);
2067 pAdapter->mppriv.tx.sended += count;
2068 count = 0;
2069 }
2070
2071 return pAdapter->mppriv.tx.sended + count;
2072
2073 }
2074
mpt_StopCckContTx(PADAPTER pAdapter)2075 static void mpt_StopCckContTx(
2076 PADAPTER pAdapter
2077 )
2078 {
2079 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2080 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2081 u8 u1bReg;
2082
2083 pMptCtx->bCckContTx = FALSE;
2084 pMptCtx->bOfdmContTx = FALSE;
2085
2086 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
2087 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
2088
2089 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2090 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 2b00*/
2091 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
2092
2093 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
2094 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 0);
2095 phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 0);
2096 }
2097
2098 /*BB Reset*/
2099 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2100 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2101
2102 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2103 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2104 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2105 }
2106
2107 if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) ||
2108 IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) ||
2109 IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) ||
2110 IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
2111 phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);/* patch Count CCK adjust Rate*/
2112 }
2113
2114 } /* mpt_StopCckContTx */
2115
2116
mpt_StopOfdmContTx(PADAPTER pAdapter)2117 static void mpt_StopOfdmContTx(
2118 PADAPTER pAdapter
2119 )
2120 {
2121 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2122 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2123 u8 u1bReg;
2124 u32 data;
2125
2126 pMptCtx->bCckContTx = FALSE;
2127 pMptCtx->bOfdmContTx = FALSE;
2128
2129 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
2130 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
2131 else
2132 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2133
2134 rtw_mdelay_os(10);
2135
2136 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)){
2137 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 0*/
2138 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
2139 }
2140
2141 /*BB Reset*/
2142 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2143 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2144
2145 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2146 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2147 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2148 }
2149 } /* mpt_StopOfdmContTx */
2150
2151
mpt_StartCckContTx(PADAPTER pAdapter)2152 static void mpt_StartCckContTx(
2153 PADAPTER pAdapter
2154 )
2155 {
2156 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2157 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2158 u32 cckrate;
2159
2160 /* 1. if CCK block on */
2161 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn))
2162 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/
2163
2164 /*Turn Off All Test Mode*/
2165 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
2166 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
2167 else
2168 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2169
2170 cckrate = pAdapter->mppriv.rateidx;
2171
2172 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
2173
2174 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*transmit mode*/
2175 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
2176
2177 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2178 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 11 force cck rxiq = 0*/
2179 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
2180 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
2181 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 1);
2182 phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 1);
2183 }
2184
2185 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2186 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2187 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2188 }
2189
2190 if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) ||
2191 IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) ||
2192 IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) ||
2193 IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
2194 if (pAdapter->mppriv.rateidx == MPT_RATE_1M) /* patch Count CCK adjust Rate*/
2195 phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);
2196 else
2197 phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bEnable);
2198 }
2199
2200 pMptCtx->bCckContTx = TRUE;
2201 pMptCtx->bOfdmContTx = FALSE;
2202
2203 } /* mpt_StartCckContTx */
2204
2205
mpt_StartOfdmContTx(PADAPTER pAdapter)2206 static void mpt_StartOfdmContTx(
2207 PADAPTER pAdapter
2208 )
2209 {
2210 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2211 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2212
2213 /* 1. if OFDM block on?*/
2214 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
2215 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/
2216
2217 /* 2. set CCK test mode off, set to CCK normal mode*/
2218 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
2219
2220 /* 3. turn on scramble setting*/
2221 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
2222
2223 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2224 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 2b'11*/
2225 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/
2226 }
2227
2228 /* 4. Turn On Continue Tx and turn off the other test modes.*/
2229 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
2230 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx);
2231 else
2232 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx);
2233
2234 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2235 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2236 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2237 }
2238
2239 pMptCtx->bCckContTx = FALSE;
2240 pMptCtx->bOfdmContTx = TRUE;
2241 } /* mpt_StartOfdmContTx */
2242
2243 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
2244 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
mpt_convert_phydm_txinfo_for_jaguar3(RT_PMAC_TX_INFO pMacTxInfo,struct phydm_pmac_info * phydmtxinfo)2245 static void mpt_convert_phydm_txinfo_for_jaguar3(
2246 RT_PMAC_TX_INFO pMacTxInfo, struct phydm_pmac_info *phydmtxinfo)
2247 {
2248 phydmtxinfo->en_pmac_tx = pMacTxInfo.bEnPMacTx;
2249 phydmtxinfo->mode = pMacTxInfo.Mode;
2250 phydmtxinfo->tx_rate = MRateToHwRate(mpt_to_mgnt_rate(pMacTxInfo.TX_RATE));
2251 phydmtxinfo->tx_sc = pMacTxInfo.TX_SC;
2252 phydmtxinfo->is_short_preamble = pMacTxInfo.bSPreamble;
2253 phydmtxinfo->ndp_sound = pMacTxInfo.NDP_sound;
2254 phydmtxinfo->bw = pMacTxInfo.BandWidth;
2255 phydmtxinfo->m_stbc = pMacTxInfo.m_STBC;
2256 phydmtxinfo->packet_period = pMacTxInfo.PacketPeriod;
2257 phydmtxinfo->packet_count = pMacTxInfo.PacketCount;
2258 phydmtxinfo->packet_pattern = pMacTxInfo.PacketPattern;
2259 phydmtxinfo->sfd = pMacTxInfo.SFD;
2260 phydmtxinfo->signal_field = pMacTxInfo.SignalField;
2261 phydmtxinfo->service_field = pMacTxInfo.ServiceField;
2262 phydmtxinfo->length = pMacTxInfo.LENGTH;
2263 _rtw_memcpy(&phydmtxinfo->crc16,pMacTxInfo.CRC16, 2);
2264 _rtw_memcpy(&phydmtxinfo->lsig , pMacTxInfo.LSIG,3);
2265 _rtw_memcpy(&phydmtxinfo->ht_sig , pMacTxInfo.HT_SIG,6);
2266 _rtw_memcpy(&phydmtxinfo->vht_sig_a , pMacTxInfo.VHT_SIG_A,6);
2267 _rtw_memcpy(&phydmtxinfo->vht_sig_b , pMacTxInfo.VHT_SIG_B,4);
2268 phydmtxinfo->vht_sig_b_crc = pMacTxInfo.VHT_SIG_B_CRC;
2269 _rtw_memcpy(&phydmtxinfo->vht_delimiter,pMacTxInfo.VHT_Delimiter,4);
2270 }
2271 #endif
2272
2273 /* for HW TX mode */
mpt_ProSetPMacTx(PADAPTER Adapter)2274 void mpt_ProSetPMacTx(PADAPTER Adapter)
2275 {
2276 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2277 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
2278 struct mp_priv *pmppriv = &Adapter->mppriv;
2279 RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
2280 u32 u4bTmp;
2281 struct dm_struct *p_dm_odm;
2282
2283 p_dm_odm = &pHalData->odmpriv;
2284
2285 #if 0
2286 PRINT_DATA("LSIG ", PMacTxInfo.LSIG, 3);
2287 PRINT_DATA("HT_SIG", PMacTxInfo.HT_SIG, 6);
2288 PRINT_DATA("VHT_SIG_A", PMacTxInfo.VHT_SIG_A, 6);
2289 PRINT_DATA("VHT_SIG_B", PMacTxInfo.VHT_SIG_B, 4);
2290 dbg_print("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC);
2291 PRINT_DATA("VHT_Delimiter", PMacTxInfo.VHT_Delimiter, 4);
2292
2293 PRINT_DATA("Src Address", Adapter->mac_addr, ETH_ALEN);
2294 PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, ETH_ALEN);
2295 #endif
2296 if (pmppriv->pktInterval != 0)
2297 PMacTxInfo.PacketPeriod = pmppriv->pktInterval;
2298
2299 if (pmppriv->tx.count != 0)
2300 PMacTxInfo.PacketCount = pmppriv->tx.count;
2301
2302 RTW_INFO("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound);
2303 RTW_INFO("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount,
2304 PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern);
2305
2306 if (IS_HARDWARE_TYPE_JAGUAR3(Adapter)) {
2307 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
2308 struct phydm_pmac_info phydm_mactxinfo;
2309
2310 mpt_convert_phydm_txinfo_for_jaguar3(PMacTxInfo, &phydm_mactxinfo);
2311 phydm_set_pmac_tx(p_dm_odm, &phydm_mactxinfo, pMptCtx->mpt_rf_path);
2312 #endif
2313 return;
2314 }
2315
2316 if (PMacTxInfo.bEnPMacTx == FALSE) {
2317 if (pMptCtx->HWTxmode == CONTINUOUS_TX) {
2318 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
2319 if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
2320 mpt_StopCckContTx(Adapter);
2321 else
2322 mpt_StopOfdmContTx(Adapter);
2323 } else if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index)) {
2324 u4bTmp = phy_query_bb_reg(Adapter, 0xf50, bMaskLWord);
2325 phy_set_bb_reg(Adapter, 0xb1c, bMaskLWord, u4bTmp + 50);
2326 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /*TX Stop*/
2327 } else
2328 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
2329
2330 if (pMptCtx->HWTxmode == OFDM_Single_Tone_TX) {
2331 /* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/
2332 if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
2333 mpt_StopCckContTx(Adapter);
2334 else
2335 mpt_StopOfdmContTx(Adapter);
2336
2337 mpt_SetSingleTone_8814A(Adapter, FALSE, TRUE);
2338 }
2339 pMptCtx->HWTxmode = TEST_NONE;
2340 return;
2341 }
2342
2343 pMptCtx->mpt_rate_index = PMacTxInfo.TX_RATE;
2344
2345 if (PMacTxInfo.Mode == CONTINUOUS_TX) {
2346 pMptCtx->HWTxmode = CONTINUOUS_TX;
2347 PMacTxInfo.PacketCount = 1;
2348
2349 hal_mpt_SetTxPower(Adapter);
2350
2351 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2352 mpt_StartCckContTx(Adapter);
2353 else
2354 mpt_StartOfdmContTx(Adapter);
2355 } else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
2356 /* Continuous TX -> HW TX -> RF Setting */
2357 pMptCtx->HWTxmode = OFDM_Single_Tone_TX;
2358 PMacTxInfo.PacketCount = 1;
2359
2360 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2361 mpt_StartCckContTx(Adapter);
2362 else
2363 mpt_StartOfdmContTx(Adapter);
2364 } else if (PMacTxInfo.Mode == PACKETS_TX) {
2365 pMptCtx->HWTxmode = PACKETS_TX;
2366 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0)
2367 PMacTxInfo.PacketCount = 0xffff;
2368 }
2369
2370 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2371 /* 0xb1c[0:15] TX packet count 0xb1C[31:16] SFD*/
2372 u4bTmp = PMacTxInfo.PacketCount | (PMacTxInfo.SFD << 16);
2373 phy_set_bb_reg(Adapter, 0xb1c, bMaskDWord, u4bTmp);
2374 /* 0xb40 7:0 SIGNAL 15:8 SERVICE 31:16 LENGTH*/
2375 u4bTmp = PMacTxInfo.SignalField | (PMacTxInfo.ServiceField << 8) | (PMacTxInfo.LENGTH << 16);
2376 phy_set_bb_reg(Adapter, 0xb40, bMaskDWord, u4bTmp);
2377 u4bTmp = PMacTxInfo.CRC16[0] | (PMacTxInfo.CRC16[1] << 8);
2378 phy_set_bb_reg(Adapter, 0xb44, bMaskLWord, u4bTmp);
2379
2380 if (PMacTxInfo.bSPreamble)
2381 phy_set_bb_reg(Adapter, 0xb0c, BIT27, 0);
2382 else
2383 phy_set_bb_reg(Adapter, 0xb0c, BIT27, 1);
2384 } else {
2385 phy_set_bb_reg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount);
2386
2387 u4bTmp = PMacTxInfo.LSIG[0] | ((PMacTxInfo.LSIG[1]) << 8) | ((PMacTxInfo.LSIG[2]) << 16) | ((PMacTxInfo.PacketPattern) << 24);
2388 phy_set_bb_reg(Adapter, 0xb08, bMaskDWord, u4bTmp); /* Set 0xb08[23:0] = LSIG, 0xb08[31:24] = Data init octet*/
2389
2390 if (PMacTxInfo.PacketPattern == 0x12)
2391 u4bTmp = 0x3000000;
2392 else
2393 u4bTmp = 0;
2394 }
2395
2396 if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) {
2397 u4bTmp |= PMacTxInfo.HT_SIG[0] | ((PMacTxInfo.HT_SIG[1]) << 8) | ((PMacTxInfo.HT_SIG[2]) << 16);
2398 phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2399 u4bTmp = PMacTxInfo.HT_SIG[3] | ((PMacTxInfo.HT_SIG[4]) << 8) | ((PMacTxInfo.HT_SIG[5]) << 16);
2400 phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
2401 } else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2402 u4bTmp |= PMacTxInfo.VHT_SIG_A[0] | ((PMacTxInfo.VHT_SIG_A[1]) << 8) | ((PMacTxInfo.VHT_SIG_A[2]) << 16);
2403 phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2404 u4bTmp = PMacTxInfo.VHT_SIG_A[3] | ((PMacTxInfo.VHT_SIG_A[4]) << 8) | ((PMacTxInfo.VHT_SIG_A[5]) << 16);
2405 phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
2406
2407 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_SIG_B, 4);
2408 phy_set_bb_reg(Adapter, 0xb14, bMaskDWord, u4bTmp);
2409 }
2410
2411 if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2412 u4bTmp = (PMacTxInfo.VHT_SIG_B_CRC << 24) | PMacTxInfo.PacketPeriod; /* for TX interval */
2413 phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, u4bTmp);
2414
2415 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_Delimiter, 4);
2416 phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, u4bTmp);
2417
2418 /* 0xb28 - 0xb34 24 byte Probe Request MAC Header*/
2419 /*& Duration & Frame control*/
2420 phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, 0x00000040);
2421
2422 /* Address1 [0:3]*/
2423 u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2424 phy_set_bb_reg(Adapter, 0xb2C, bMaskDWord, u4bTmp);
2425
2426 /* Address3 [3:0]*/
2427 phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2428
2429 /* Address2[0:1] & Address1 [5:4]*/
2430 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2431 phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2432
2433 /* Address2 [5:2]*/
2434 u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2435 phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2436
2437 /* Sequence Control & Address3 [5:4]*/
2438 /*u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8) ;*/
2439 /*phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/
2440 } else {
2441 phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod); /* for TX interval*/
2442 /* & Duration & Frame control */
2443 phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, 0x00000040);
2444
2445 /* 0xb24 - 0xb38 24 byte Probe Request MAC Header*/
2446 /* Address1 [0:3]*/
2447 u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2448 phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, u4bTmp);
2449
2450 /* Address3 [3:0]*/
2451 phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2452
2453 /* Address2[0:1] & Address1 [5:4]*/
2454 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2455 phy_set_bb_reg(Adapter, 0xb2c, bMaskDWord, u4bTmp);
2456
2457 /* Address2 [5:2] */
2458 u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2459 phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2460
2461 /* Sequence Control & Address3 [5:4]*/
2462 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8);
2463 phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2464 }
2465
2466 phy_set_bb_reg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX);
2467
2468 /* 0xb4c 3:0 TXSC 5:4 BW 7:6 m_STBC 8 NDP_Sound*/
2469 u4bTmp = (PMacTxInfo.TX_SC) | ((PMacTxInfo.BandWidth) << 4) | ((PMacTxInfo.m_STBC - 1) << 6) | ((PMacTxInfo.NDP_sound) << 8);
2470 phy_set_bb_reg(Adapter, 0xb4c, 0x1ff, u4bTmp);
2471
2472 if (IS_HARDWARE_TYPE_JAGUAR2(Adapter)) {
2473 u32 offset = 0xb44;
2474
2475 if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
2476 phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
2477 else if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
2478 phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
2479 else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
2480 phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
2481
2482 } else if(IS_HARDWARE_TYPE_JAGUAR(Adapter)) {
2483 u32 offset = 0xb4c;
2484
2485 if(IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
2486 phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
2487 else if(IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
2488 phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
2489 else if(IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
2490 phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
2491 }
2492
2493 phy_set_bb_reg(Adapter, 0xb00, BIT8, 1); /* Turn on PMAC*/
2494 /* phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); */ /* TX Stop */
2495 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2496 phy_set_bb_reg(Adapter, 0xb04, 0xf, 8); /*TX CCK ON*/
2497 phy_set_bb_reg(Adapter, 0xA84, BIT31, 0);
2498 } else
2499 phy_set_bb_reg(Adapter, 0xb04, 0xf, 4); /* TX Ofdm ON */
2500
2501 if (PMacTxInfo.Mode == OFDM_Single_Tone_TX)
2502 mpt_SetSingleTone_8814A(Adapter, TRUE, TRUE);
2503
2504 }
2505
2506 #endif
2507
hal_mpt_SetContinuousTx(PADAPTER pAdapter,u8 bStart)2508 void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
2509 {
2510 u8 Rate;
2511
2512 RTW_INFO("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx);
2513 Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
2514 pAdapter->mppriv.mpt_ctx.is_start_cont_tx = bStart;
2515
2516 if (Rate <= MPT_RATE_11M) {
2517 if (bStart)
2518 mpt_StartCckContTx(pAdapter);
2519 else
2520 mpt_StopCckContTx(pAdapter);
2521
2522 } else if (Rate >= MPT_RATE_6M) {
2523 if (bStart)
2524 mpt_StartOfdmContTx(pAdapter);
2525 else
2526 mpt_StopOfdmContTx(pAdapter);
2527 }
2528 }
2529
2530 #endif /* CONFIG_MP_INCLUDE*/
2531