1 /****************************************************************************** 2 * 3 * Copyright(c) 2016 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 #ifndef _RTL8821C_HAL_H_ 21 #define _RTL8821C_HAL_H_ 22 23 #include <osdep_service.h> /* BIT(x) */ 24 #include "../hal/halmac/halmac_api.h" /* MAC REG definition */ 25 #include "hal_data.h" 26 27 #if defined(CONFIG_USB_HCI) 28 29 #ifndef MAX_RECVBUF_SZ 30 #ifndef CONFIG_MINIMAL_MEMORY_USAGE 31 #ifdef CONFIG_PLATFORM_MSTAR 32 #define MAX_RECVBUF_SZ (8192) /* 8K */ 33 #else 34 /* 8821C - RX FIFO :16K ,for RX agg DMA mode = 16K, Rx agg USB mode could large than 16k*/ 35 #define MAX_RECVBUF_SZ HALMAC_RX_FIFO_SIZE_8821C 36 #endif 37 /*#define MAX_RECVBUF_SZ_8821C (24576)*/ /* 24k*/ 38 /*#define MAX_RECVBUF_SZ_8821C (20480)*/ /*20K*/ 39 /*#define MAX_RECVBUF_SZ_8821C (10240) */ /*10K*/ 40 /*#define MAX_RECVBUF_SZ_8821C (15360)*/ /*15k < 16k*/ 41 /*#define MAX_RECVBUF_SZ_8821C (8192+1024)*/ /* 8K+1k*/ 42 #else 43 #define MAX_RECVBUF_SZ (4096) /* about 4K */ 44 #endif 45 #endif/* !MAX_RECVBUF_SZ*/ 46 47 #elif defined(CONFIG_PCI_HCI) 48 /*#ifndef CONFIG_MINIMAL_MEMORY_USAGE 49 #define MAX_RECVBUF_SZ (9100) 50 #else*/ 51 #define MAX_RECVBUF_SZ (4096) /* about 4K */ 52 /*#endif*/ 53 54 #elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) 55 56 #define MAX_RECVBUF_SZ HALMAC_RX_FIFO_SIZE_8821C 57 58 #endif 59 60 #define EFUSE_MAP_SIZE HALMAC_EFUSE_SIZE_8821C 61 62 #define MACID_NUM_8821C 128 63 #define NSS_NUM_8821C 1 64 #define HW_PORT_NUM_8821C 5 65 66 /* 67 * MAC Register definition 68 */ 69 #define REG_AFE_XTAL_CTRL REG_AFE_CTRL1_8821C /* hal_com.c & phydm */ 70 #define REG_AFE_PLL_CTRL REG_AFE_CTRL2_8821C /* hal_com.c & phydm */ 71 #define REG_MAC_PHY_CTRL REG_AFE_CTRL3_8821C /* phydm only */ 72 #define REG_LEDCFG0 REG_LED_CFG_8821C /* rtw_mp.c */ 73 #define MSR (REG_CR_8821C + 2) /* rtw_mp.c */ 74 #define MSR1 REG_CR_EXT_8821C /* rtw_mp.c & hal_com.c */ 75 #define REG_C2HEVT_MSG_NORMAL 0x1A0 /* hal_com.c */ 76 #define REG_C2HEVT_CLEAR 0x1AF /* hal_com.c */ 77 #define REG_BCN_CTRL_1 REG_BCN_CTRL_CLINT0_8821C/* hal_com.c */ 78 #define REG_TSFTR1 REG_FREERUN_CNT_8821C /* hal_com.c */ 79 #define REG_RXFLTMAP2 REG_RXFLTMAP_8821C /* rtw_mp.c */ 80 81 /* RXERR_RPT, for rtw_mp.c */ 82 #define RXERR_TYPE_OFDM_PPDU 0 83 #define RXERR_TYPE_OFDM_FALSE_ALARM 2 84 #define RXERR_TYPE_OFDM_MPDU_OK 0 85 #define RXERR_TYPE_OFDM_MPDU_FAIL 1 86 #define RXERR_TYPE_CCK_PPDU 3 87 #define RXERR_TYPE_CCK_FALSE_ALARM 5 88 #define RXERR_TYPE_CCK_MPDU_OK 3 89 #define RXERR_TYPE_CCK_MPDU_FAIL 4 90 #define RXERR_TYPE_HT_PPDU 8 91 #define RXERR_TYPE_HT_FALSE_ALARM 9 92 #define RXERR_TYPE_HT_MPDU_TOTAL 6 93 #define RXERR_TYPE_HT_MPDU_OK 6 94 #define RXERR_TYPE_HT_MPDU_FAIL 7 95 #define RXERR_TYPE_RX_FULL_DROP 10 96 97 #define RXERR_COUNTER_MASK BIT_MASK_RPT_COUNTER_8821C 98 #define RXERR_RPT_RST BIT_RXERR_RPT_RST_8821C 99 #define _RXERR_RPT_SEL(type) (BIT_RXERR_RPT_SEL_V1_3_0_8821C(type) \ 100 | ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8821C : 0)) 101 102 /* 103 * BB Register definition 104 */ 105 #define rPMAC_Reset 0x100 /* hal_mp.c */ 106 107 #define rFPGA0_RFMOD 0x800 108 #define rFPGA0_TxInfo 0x804 109 #define rOFDMCCKEN_Jaguar 0x808 /* hal_mp.c */ 110 #define rFPGA0_TxGainStage 0x80C /* phydm only */ 111 #define rFPGA0_XA_HSSIParameter1 0x820 /* hal_mp.c */ 112 #define rFPGA0_XA_HSSIParameter2 0x824 /* hal_mp.c */ 113 #define rFPGA0_XB_HSSIParameter1 0x828 /* hal_mp.c */ 114 #define rFPGA0_XB_HSSIParameter2 0x82C /* hal_mp.c */ 115 #define rTxAGC_B_Rate18_06 0x830 116 #define rTxAGC_B_Rate54_24 0x834 117 #define rTxAGC_B_CCK1_55_Mcs32 0x838 118 #define rCCAonSec_Jaguar 0x838 /* hal_mp.c */ 119 #define rTxAGC_B_Mcs03_Mcs00 0x83C 120 #define rTxAGC_B_Mcs07_Mcs04 0x848 121 #define rTxAGC_B_Mcs11_Mcs08 0x84C 122 #define rFPGA0_XA_RFInterfaceOE 0x860 123 #define rFPGA0_XB_RFInterfaceOE 0x864 124 #define rTxAGC_B_Mcs15_Mcs12 0x868 125 #define rTxAGC_B_CCK11_A_CCK2_11 0x86C 126 #define rFPGA0_XAB_RFInterfaceSW 0x870 127 #define rFPGA0_XAB_RFParameter 0x878 128 #define rFPGA0_AnalogParameter4 0x88C /* hal_mp.c & phydm */ 129 #define rFPGA0_XB_LSSIReadBack 0x8A4 /* phydm */ 130 #define rHSSIRead_Jaguar 0x8B0 /* RF read addr (rtl8821c_phy.c) */ 131 132 #define rC_TxScale_Jaguar2 0x181C /* Pah_C TX scaling factor (hal_mp.c) */ 133 #define rC_IGI_Jaguar2 0x1850 /* Initial Gain for path-C (hal_mp.c) */ 134 135 #define rFPGA1_TxInfo 0x90C /* hal_mp.c */ 136 #define rSingleTone_ContTx_Jaguar 0x914 /* hal_mp.c */ 137 138 #define rCCK0_System 0xA00 139 #define rCCK0_AFESetting 0xA04 140 141 #define rCCK0_DSPParameter2 0xA1C 142 #define rCCK0_TxFilter1 0xA20 143 #define rCCK0_TxFilter2 0xA24 144 #define rCCK0_DebugPort 0xA28 145 #define rCCK0_FalseAlarmReport 0xA2C 146 147 #define rD_TxScale_Jaguar2 0x1A1C /* Path_D TX scaling factor (hal_mp.c) */ 148 #define rD_IGI_Jaguar2 0x1A50 /* Initial Gain for path-D (hal_mp.c) */ 149 150 #define rOFDM0_TRxPathEnable 0xC04 151 #define rOFDM0_TRMuxPar 0xC08 152 #define rA_TxScale_Jaguar 0xC1C /* Pah_A TX scaling factor (hal_mp.c) */ 153 #define rOFDM0_RxDetector1 0xC30 /* rtw_mp.c */ 154 #define rOFDM0_ECCAThreshold 0xC4C /* phydm only */ 155 #define rOFDM0_XAAGCCore1 0xC50 /* phydm only */ 156 #define rA_IGI_Jaguar 0xC50 /* Initial Gain for path-A (hal_mp.c) */ 157 #define rOFDM0_XBAGCCore1 0xC58 /* phydm only */ 158 #define rOFDM0_XATxIQImbalance 0xC80 /* phydm only */ 159 #define rA_LSSIWrite_Jaguar 0xC90 /* RF write addr, LSSI Parameter (rtl8821c_phy.c) */ 160 #define rA_RFE_Pinmux_Jaguar 0xCB0 /* hal_mp.c */ 161 162 #define rOFDM1_LSTF 0xD00 163 #define rOFDM1_TRxPathEnable 0xD04 /* hal_mp.c */ 164 #define rA_PIRead_Jaguar 0xD04 /* RF readback with PI (rtl8821c_phy.c) */ 165 #define rA_SIRead_Jaguar 0xD08 /* RF readback with SI (rtl8821c_phy.c) */ 166 #define rB_PIRead_Jaguar 0xD44 /* RF readback with PI (rtl8821c_phy.c) */ 167 #define rB_SIRead_Jaguar 0xD48 /* RF readback with SI (rtl8821c_phy.c) */ 168 169 #define rTxAGC_A_Rate18_06 0xE00 170 #define rTxAGC_A_Rate54_24 0xE04 171 #define rTxAGC_A_CCK1_Mcs32 0xE08 172 #define rTxAGC_A_Mcs03_Mcs00 0xE10 173 #define rTxAGC_A_Mcs07_Mcs04 0xE14 174 #define rTxAGC_A_Mcs11_Mcs08 0xE18 175 #define rTxAGC_A_Mcs15_Mcs12 0xE1C 176 #define rB_TxScale_Jaguar 0xE1C /* Path_B TX scaling factor (hal_mp.c) */ 177 #define rB_IGI_Jaguar 0xE50 /* Initial Gain for path-B (hal_mp.c) */ 178 #define rB_LSSIWrite_Jaguar 0xE90 /* RF write addr, LSSI Parameter (rtl8821c_phy.c) */ 179 #define rB_RFE_Pinmux_Jaguar 0xEB0 /* hal_mp.c */ 180 181 /* Page1(0x100) */ 182 #define bBBResetB 0x100 183 184 /* Page8(0x800) */ 185 #define bCCKEn 0x1000000 186 #define bOFDMEn 0x2000000 187 /* Reg 0x80C rFPGA0_TxGainStage */ 188 #define bXBTxAGC 0xF00 189 #define bXCTxAGC 0xF000 190 #define bXDTxAGC 0xF0000 191 192 /* PageA(0xA00) */ 193 #define bCCKBBMode 0x3 194 195 #define bCCKScramble 0x8 196 #define bCCKTxRate 0x3000 197 198 /* General */ 199 #define bMaskByte0 0xFF /* mp, rtw_odm.c & phydm */ 200 #define bMaskByte1 0xFF00 /* hal_mp.c & phydm */ 201 #define bMaskByte2 0xFF0000 /* hal_mp.c & phydm */ 202 #define bMaskByte3 0xFF000000 /* hal_mp.c & phydm */ 203 #define bMaskHWord 0xFFFF0000 /* hal_com.c, rtw_mp.c */ 204 #define bMaskLWord 0x0000FFFF /* mp, hal_com.c & phydm */ 205 #define bMaskDWord 0xFFFFFFFF /* mp, hal, rtw_odm.c & phydm */ 206 207 #define bEnable 0x1 /* hal_mp.c, rtw_mp.c */ 208 #define bDisable 0x0 /* rtw_mp.c */ 209 210 #define MAX_STALL_TIME 50 /* unit: us, hal_com_phycfg.c */ 211 212 #define Rx_Smooth_Factor 20 /* phydm only */ 213 214 /* 215 * RF Register definition 216 */ 217 #define RF_AC 0x00 218 #define RF_AC_Jaguar 0x00 /* hal_mp.c */ 219 #define RF_CHNLBW 0x18 /* rtl8821c_phy.c */ 220 #define RF_0x52 0x52 221 222 /* 223 * 8821C files path 224 */ 225 #define RTL8821C_FW_IMG "rtl8821c/FW_NIC.bin" 226 #define RTL8821C_FW_WW_IMG "rtl8821c/FW_WoWLAN.bin" 227 #define RTL8821C_PHY_REG "rtl8821c/PHY_REG.txt" 228 #define RTL8821C_PHY_RADIO_A "rtl8821c/RadioA.txt" 229 #define RTL8821C_PHY_RADIO_B "rtl8821c/RadioB.txt" 230 #define RTL8821C_TXPWR_TRACK "rtl8821c/TxPowerTrack.txt" 231 #define RTL8821C_AGC_TAB "rtl8821c/AGC_TAB.txt" 232 #define RTL8821C_PHY_MACREG "rtl8821c/MAC_REG.txt" 233 #define RTL8821C_PHY_REG_PG "rtl8821c/PHY_REG_PG.txt" 234 #define RTL8821C_PHY_REG_MP "rtl8821c/PHY_REG_MP.txt" 235 #define RTL8821C_TXPWR_LMT "rtl8821c/TXPWR_LMT.txt" 236 237 void init_hal_spec_rtl8821c(PADAPTER); 238 /* MP Functions */ 239 void rtl8821c_phy_init_haldm(PADAPTER); /* rtw_mp.c */ 240 void rtl8821c_prepare_mp_txdesc(PADAPTER, struct mp_priv *); /* rtw_mp.c */ 241 void rtl8821c_mp_config_rfpath(PADAPTER); /* hal_mp.c */ 242 243 #endif /* _RTL8821C_HAL_H_ */ 244