1 /****************************************************************************** 2 * 3 * Copyright(c) 2013 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 *******************************************************************************/ 19 #ifndef __RTL8821A_SPEC_H__ 20 #define __RTL8821A_SPEC_H__ 21 22 #include <drv_conf.h> 23 /* This file should based on "hal_com_reg.h" */ 24 #include <hal_com_reg.h> 25 /* Because 8812a and 8821a is the same serial, 26 * most of 8821a register definitions are the same as 8812a. */ 27 #include <rtl8812a_spec.h> 28 29 30 /* ************************************************************ 31 * 8821A Regsiter offset definition 32 * ************************************************************ */ 33 34 /* ************************************************************ 35 * MAC register 36 * ************************************************************ */ 37 38 /* ----------------------------------------------------- 39 * 0x0000h ~ 0x00FFh System Configuration 40 * ----------------------------------------------------- */ 41 42 /* ----------------------------------------------------- 43 * 0x0100h ~ 0x01FFh MACTOP General Configuration 44 * ----------------------------------------------------- */ 45 #define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN 46 47 /* ----------------------------------------------------- 48 * 0x0200h ~ 0x027Fh TXDMA Configuration 49 * ----------------------------------------------------- */ 50 51 /* ----------------------------------------------------- 52 * 0x0280h ~ 0x02FFh RXDMA Configuration 53 * ----------------------------------------------------- */ 54 55 /* ----------------------------------------------------- 56 * 0x0300h ~ 0x03FFh PCIe 57 * ----------------------------------------------------- */ 58 59 /* ----------------------------------------------------- 60 * 0x0400h ~ 0x047Fh Protocol Configuration 61 * ----------------------------------------------------- */ 62 63 /* ----------------------------------------------------- 64 * 0x0500h ~ 0x05FFh EDCA Configuration 65 * ----------------------------------------------------- */ 66 67 /* ----------------------------------------------------- 68 * 0x0600h ~ 0x07FFh WMAC Configuration 69 * ----------------------------------------------------- */ 70 71 72 /* ************************************************************ 73 * SDIO Bus Specification 74 * ************************************************************ */ 75 76 /* ----------------------------------------------------- 77 * SDIO CMD Address Mapping 78 * ----------------------------------------------------- */ 79 80 /* ----------------------------------------------------- 81 * I/O bus domain (Host) 82 * ----------------------------------------------------- */ 83 84 /* ----------------------------------------------------- 85 * SDIO register 86 * ----------------------------------------------------- */ 87 #undef SDIO_REG_HCPWM1 88 #define SDIO_REG_FREE_TXPG2 0x024 89 #define SDIO_REG_HCPWM1 0x025 90 91 92 /* ************************************************************ 93 * Regsiter Bit and Content definition 94 * ************************************************************ */ 95 96 /* ******************************************************** 97 * General definitions 98 * ******************************************************** */ 99 100 #define MACID_NUM_8821A 128 101 #define SEC_CAM_ENT_NUM_8821A 64 102 #define HW_PORT_NUM_8821A 2 103 #define NSS_NUM_8821A 1 104 #define BAND_CAP_8821A (BAND_CAP_2G | BAND_CAP_5G) 105 #define BW_CAP_8821A (BW_CAP_20M | BW_CAP_40M | BW_CAP_80M) 106 #define PROTO_CAP_8821A (PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N | PROTO_CAP_11AC) 107 108 #endif /* __RTL8821A_SPEC_H__ */ 109