1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 *******************************************************************************/ 19 #ifndef __RTL8723D_SPEC_H__ 20 #define __RTL8723D_SPEC_H__ 21 22 #include <drv_conf.h> 23 24 25 #define HAL_NAV_UPPER_UNIT_8723D 128 /* micro-second */ 26 27 /* ----------------------------------------------------- 28 * 29 * 0x0000h ~ 0x00FFh System Configuration 30 * 31 * ----------------------------------------------------- */ 32 #define REG_SYS_ISO_CTRL_8723D 0x0000 /* 2 Byte */ 33 #define REG_SYS_FUNC_EN_8723D 0x0002 /* 2 Byte */ 34 #define REG_APS_FSMCO_8723D 0x0004 /* 4 Byte */ 35 #define REG_SYS_CLKR_8723D 0x0008 /* 2 Byte */ 36 #define REG_9346CR_8723D 0x000A /* 2 Byte */ 37 #define REG_EE_VPD_8723D 0x000C /* 2 Byte */ 38 #define REG_AFE_MISC_8723D 0x0010 /* 1 Byte */ 39 #define REG_SPS0_CTRL_8723D 0x0011 /* 7 Byte */ 40 #define REG_SPS_OCP_CFG_8723D 0x0018 /* 4 Byte */ 41 #define REG_RSV_CTRL_8723D 0x001C /* 3 Byte */ 42 #define REG_RF_CTRL_8723D 0x001F /* 1 Byte */ 43 #define REG_LPLDO_CTRL_8723D 0x0023 /* 1 Byte */ 44 #define REG_AFE_XTAL_CTRL_8723D 0x0024 /* 4 Byte */ 45 #define REG_AFE_PLL_CTRL_8723D 0x0028 /* 4 Byte */ 46 #define REG_MAC_PLL_CTRL_EXT_8723D 0x002c /* 4 Byte */ 47 #define REG_EFUSE_CTRL_8723D 0x0030 48 #define REG_EFUSE_TEST_8723D 0x0034 49 #define REG_PWR_DATA_8723D 0x0038 50 #define REG_CAL_TIMER_8723D 0x003C 51 #define REG_ACLK_MON_8723D 0x003E 52 #define REG_GPIO_MUXCFG_8723D 0x0040 53 #define REG_GPIO_IO_SEL_8723D 0x0042 54 #define REG_MAC_PINMUX_CFG_8723D 0x0043 55 #define REG_GPIO_PIN_CTRL_8723D 0x0044 56 #define REG_GPIO_INTM_8723D 0x0048 57 #define REG_LEDCFG0_8723D 0x004C 58 #define REG_LEDCFG1_8723D 0x004D 59 #define REG_LEDCFG2_8723D 0x004E 60 #define REG_LEDCFG3_8723D 0x004F 61 #define REG_FSIMR_8723D 0x0050 62 #define REG_FSISR_8723D 0x0054 63 #define REG_HSIMR_8723D 0x0058 64 #define REG_HSISR_8723D 0x005c 65 #define REG_GPIO_EXT_CTRL 0x0060 66 #define REG_PAD_CTRL1_8723D 0x0064 67 #define REG_MULTI_FUNC_CTRL_8723D 0x0068 68 #define REG_GPIO_STATUS_8723D 0x006C 69 #define REG_SDIO_CTRL_8723D 0x0070 70 #define REG_OPT_CTRL_8723D 0x0074 71 #define REG_AFE_CTRL_4_8723D 0x0078 72 #define REG_MCUFWDL_8723D 0x0080 73 #define REG_8051FW_CTRL_8723D 0x0080 74 #define REG_HMEBOX_DBG_0_8723D 0x0088 75 #define REG_HMEBOX_DBG_1_8723D 0x008A 76 #define REG_HMEBOX_DBG_2_8723D 0x008C 77 #define REG_HMEBOX_DBG_3_8723D 0x008E 78 #define REG_WLLPS_CTRL 0x0090 79 #define REG_HIMR0_8723D 0x00B0 80 #define REG_HISR0_8723D 0x00B4 81 #define REG_HIMR1_8723D 0x00B8 82 #define REG_HISR1_8723D 0x00BC 83 #define REG_PMC_DBG_CTRL2_8723D 0x00CC 84 #define REG_EFUSE_BURN_GNT_8723D 0x00CF 85 #define REG_HPON_FSM_8723D 0x00EC 86 #define REG_SYS_CFG_8723D 0x00FC 87 #define REG_ROM_VERSION 0x00FD 88 89 /* ----------------------------------------------------- 90 * 91 * 0x0100h ~ 0x01FFh MACTOP General Configuration 92 * 93 * ----------------------------------------------------- */ 94 #define REG_C2HEVT_CMD_ID_8723D 0x01A0 95 #define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 96 #define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 97 #define REG_C2HEVT_CMD_LEN_8723D 0x01AE 98 #define REG_C2HEVT_CLEAR_8723D 0x01AF 99 #define REG_MCUTST_1_8723D 0x01C0 100 #define REG_WOWLAN_WAKE_REASON 0x01C7 101 #define REG_FMETHR_8723D 0x01C8 102 #define REG_HMETFR_8723D 0x01CC 103 #define REG_HMEBOX_0_8723D 0x01D0 104 #define REG_HMEBOX_1_8723D 0x01D4 105 #define REG_HMEBOX_2_8723D 0x01D8 106 #define REG_HMEBOX_3_8723D 0x01DC 107 #define REG_LLT_INIT_8723D 0x01E0 108 #define REG_HMEBOX_EXT0_8723D 0x01F0 109 #define REG_HMEBOX_EXT1_8723D 0x01F4 110 #define REG_HMEBOX_EXT2_8723D 0x01F8 111 #define REG_HMEBOX_EXT3_8723D 0x01FC 112 113 /* ----------------------------------------------------- 114 * 115 * 0x0200h ~ 0x027Fh TXDMA Configuration 116 * 117 * ----------------------------------------------------- */ 118 #define REG_RQPN_8723D 0x0200 119 #define REG_FIFOPAGE_8723D 0x0204 120 #define REG_DWBCN0_CTRL_8723D REG_TDECTRL 121 #define REG_TXDMA_OFFSET_CHK_8723D 0x020C 122 #define REG_TXDMA_STATUS_8723D 0x0210 123 #define REG_RQPN_NPQ_8723D 0x0214 124 #define REG_DWBCN1_CTRL_8723D 0x0228 125 126 127 /* ----------------------------------------------------- 128 * 129 * 0x0280h ~ 0x02FFh RXDMA Configuration 130 * 131 * ----------------------------------------------------- */ 132 #define REG_RXDMA_AGG_PG_TH_8723D 0x0280 133 #define REG_FW_UPD_RDPTR_8723D 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */ 134 #define REG_RXDMA_CONTROL_8723D 0x0286 /* Control the RX DMA. */ 135 #define REG_RXDMA_STATUS_8723D 0x0288 136 #define REG_RXDMA_MODE_CTRL_8723D 0x0290 137 #define REG_EARLY_MODE_CONTROL_8723D 0x02BC 138 #define REG_RSVD5_8723D 0x02F0 139 #define REG_RSVD6_8723D 0x02F4 140 141 /* ----------------------------------------------------- 142 * 143 * 0x0300h ~ 0x03FFh PCIe 144 * 145 * ----------------------------------------------------- */ 146 #define REG_PCIE_CTRL_REG_8723D 0x0300 147 #define REG_INT_MIG_8723D 0x0304 /* Interrupt Migration */ 148 #define REG_BCNQ_TXBD_DESA_8723D 0x0308 /* TX Beacon Descriptor Address */ 149 #define REG_MGQ_TXBD_DESA_8723D 0x0310 /* TX Manage Queue Descriptor Address */ 150 #define REG_VOQ_TXBD_DESA_8723D 0x0318 /* TX VO Queue Descriptor Address */ 151 #define REG_VIQ_TXBD_DESA_8723D 0x0320 /* TX VI Queue Descriptor Address */ 152 #define REG_BEQ_TXBD_DESA_8723D 0x0328 /* TX BE Queue Descriptor Address */ 153 #define REG_BKQ_TXBD_DESA_8723D 0x0330 /* TX BK Queue Descriptor Address */ 154 #define REG_RXQ_RXBD_DESA_8723D 0x0338 /* RX Queue Descriptor Address */ 155 #define REG_HI0Q_TXBD_DESA_8723D 0x0340 156 #define REG_HI1Q_TXBD_DESA_8723D 0x0348 157 #define REG_HI2Q_TXBD_DESA_8723D 0x0350 158 #define REG_HI3Q_TXBD_DESA_8723D 0x0358 159 #define REG_HI4Q_TXBD_DESA_8723D 0x0360 160 #define REG_HI5Q_TXBD_DESA_8723D 0x0368 161 #define REG_HI6Q_TXBD_DESA_8723D 0x0370 162 #define REG_HI7Q_TXBD_DESA_8723D 0x0378 163 #define REG_MGQ_TXBD_NUM_8723D 0x0380 164 #define REG_RX_RXBD_NUM_8723D 0x0382 165 #define REG_VOQ_TXBD_NUM_8723D 0x0384 166 #define REG_VIQ_TXBD_NUM_8723D 0x0386 167 #define REG_BEQ_TXBD_NUM_8723D 0x0388 168 #define REG_BKQ_TXBD_NUM_8723D 0x038A 169 #define REG_HI0Q_TXBD_NUM_8723D 0x038C 170 #define REG_HI1Q_TXBD_NUM_8723D 0x038E 171 #define REG_HI2Q_TXBD_NUM_8723D 0x0390 172 #define REG_HI3Q_TXBD_NUM_8723D 0x0392 173 #define REG_HI4Q_TXBD_NUM_8723D 0x0394 174 #define REG_HI5Q_TXBD_NUM_8723D 0x0396 175 #define REG_HI6Q_TXBD_NUM_8723D 0x0398 176 #define REG_HI7Q_TXBD_NUM_8723D 0x039A 177 #define REG_TSFTIMER_HCI_8723D 0x039C 178 #define REG_BD_RW_PTR_CLR_8723D 0x039C 179 180 /* Read Write Point */ 181 #define REG_VOQ_TXBD_IDX_8723D 0x03A0 182 #define REG_VIQ_TXBD_IDX_8723D 0x03A4 183 #define REG_BEQ_TXBD_IDX_8723D 0x03A8 184 #define REG_BKQ_TXBD_IDX_8723D 0x03AC 185 #define REG_MGQ_TXBD_IDX_8723D 0x03B0 186 #define REG_RXQ_TXBD_IDX_8723D 0x03B4 187 #define REG_HI0Q_TXBD_IDX_8723D 0x03B8 188 #define REG_HI1Q_TXBD_IDX_8723D 0x03BC 189 #define REG_HI2Q_TXBD_IDX_8723D 0x03C0 190 #define REG_HI3Q_TXBD_IDX_8723D 0x03C4 191 #define REG_HI4Q_TXBD_IDX_8723D 0x03C8 192 #define REG_HI5Q_TXBD_IDX_8723D 0x03CC 193 #define REG_HI6Q_TXBD_IDX_8723D 0x03D0 194 #define REG_HI7Q_TXBD_IDX_8723D 0x03D4 195 196 #define REG_PCIE_HCPWM_8723DE 0x03D8 /* ?????? */ 197 #define REG_PCIE_HRPWM_8723DE 0x03DC /* PCIe RPWM ?????? */ 198 #define REG_DBI_WDATA_V1_8723D 0x03E8 199 #define REG_DBI_RDATA_V1_8723D 0x03EC 200 #define REG_DBI_FLAG_V1_8723D 0x03F0 201 #define REG_MDIO_V1_8723D 0x03F4 202 #define REG_PCIE_MIX_CFG_8723D 0x03F8 203 #define REG_HCI_MIX_CFG_8723D 0x03FC 204 205 /* ----------------------------------------------------- 206 * 207 * 0x0400h ~ 0x047Fh Protocol Configuration 208 * 209 * ----------------------------------------------------- */ 210 #define REG_VOQ_INFORMATION_8723D 0x0400 211 #define REG_VIQ_INFORMATION_8723D 0x0404 212 #define REG_BEQ_INFORMATION_8723D 0x0408 213 #define REG_BKQ_INFORMATION_8723D 0x040C 214 #define REG_MGQ_INFORMATION_8723D 0x0410 215 #define REG_HGQ_INFORMATION_8723D 0x0414 216 #define REG_BCNQ_INFORMATION_8723D 0x0418 217 #define REG_TXPKT_EMPTY_8723D 0x041A 218 219 #define REG_FWHW_TXQ_CTRL_8723D 0x0420 220 #define REG_HWSEQ_CTRL_8723D 0x0423 221 #define REG_TXPKTBUF_BCNQ_BDNY_8723D 0x0424 222 #define REG_TXPKTBUF_MGQ_BDNY_8723D 0x0425 223 #define REG_LIFECTRL_CTRL_8723D 0x0426 224 #define REG_MULTI_BCNQ_OFFSET_8723D 0x0427 225 #define REG_SPEC_SIFS_8723D 0x0428 226 #define REG_RL_8723D 0x042A 227 #define REG_TXBF_CTRL_8723D 0x042C 228 #define REG_DARFRC_8723D 0x0430 229 #define REG_RARFRC_8723D 0x0438 230 #define REG_RRSR_8723D 0x0440 231 #define REG_ARFR0_8723D 0x0444 232 #define REG_ARFR1_8723D 0x044C 233 #define REG_CCK_CHECK_8723D 0x0454 234 #define REG_AMPDU_MAX_TIME_8723D 0x0456 235 #define REG_TXPKTBUF_BCNQ_BDNY1_8723D 0x0457 236 237 #define REG_AMPDU_MAX_LENGTH_8723D 0x0458 238 #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723D 0x045D 239 #define REG_NDPA_OPT_CTRL_8723D 0x045F 240 #define REG_FAST_EDCA_CTRL_8723D 0x0460 241 #define REG_RD_RESP_PKT_TH_8723D 0x0463 242 #define REG_DATA_SC_8723D 0x0483 243 #ifdef CONFIG_WOWLAN 244 #define REG_TXPKTBUF_IV_LOW 0x0484 245 #define REG_TXPKTBUF_IV_HIGH 0x0488 246 #endif 247 #define REG_TXRPT_START_OFFSET 0x04AC 248 #define REG_POWER_STAGE1_8723D 0x04B4 249 #define REG_POWER_STAGE2_8723D 0x04B8 250 #define REG_AMPDU_BURST_MODE_8723D 0x04BC 251 #define REG_PKT_VO_VI_LIFE_TIME_8723D 0x04C0 252 #define REG_PKT_BE_BK_LIFE_TIME_8723D 0x04C2 253 #define REG_STBC_SETTING_8723D 0x04C4 254 #define REG_HT_SINGLE_AMPDU_8723D 0x04C7 255 #define REG_PROT_MODE_CTRL_8723D 0x04C8 256 #define REG_MAX_AGGR_NUM_8723D 0x04CA 257 #define REG_RTS_MAX_AGGR_NUM_8723D 0x04CB 258 #define REG_BAR_MODE_CTRL_8723D 0x04CC 259 #define REG_RA_TRY_RATE_AGG_LMT_8723D 0x04CF 260 #define REG_MACID_PKT_DROP0_8723D 0x04D0 261 #define REG_MACID_PKT_SLEEP_8723D 0x04D4 262 263 /* ----------------------------------------------------- 264 * 265 * 0x0500h ~ 0x05FFh EDCA Configuration 266 * 267 * ----------------------------------------------------- */ 268 #define REG_EDCA_VO_PARAM_8723D 0x0500 269 #define REG_EDCA_VI_PARAM_8723D 0x0504 270 #define REG_EDCA_BE_PARAM_8723D 0x0508 271 #define REG_EDCA_BK_PARAM_8723D 0x050C 272 #define REG_BCNTCFG_8723D 0x0510 273 #define REG_PIFS_8723D 0x0512 274 #define REG_RDG_PIFS_8723D 0x0513 275 #define REG_SIFS_CTX_8723D 0x0514 276 #define REG_SIFS_TRX_8723D 0x0516 277 #define REG_AGGR_BREAK_TIME_8723D 0x051A 278 #define REG_SLOT_8723D 0x051B 279 #define REG_TX_PTCL_CTRL_8723D 0x0520 280 #define REG_TXPAUSE_8723D 0x0522 281 #define REG_DIS_TXREQ_CLR_8723D 0x0523 282 #define REG_RD_CTRL_8723D 0x0524 283 /* 284 * Format for offset 540h-542h: 285 * [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. 286 * [7:4]: Reserved. 287 * [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. 288 * [23:20]: Reserved 289 * Description: 290 * | 291 * |<--Setup--|--Hold------------>| 292 * --------------|---------------------- 293 * | 294 * TBTT 295 * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. 296 * Described by Designer Tim and Bruce, 2011-01-14. 297 * */ 298 #define REG_TBTT_PROHIBIT_8723D 0x0540 299 #define REG_RD_NAV_NXT_8723D 0x0544 300 #define REG_NAV_PROT_LEN_8723D 0x0546 301 #define REG_BCN_CTRL_8723D 0x0550 302 #define REG_BCN_CTRL_1_8723D 0x0551 303 #define REG_MBID_NUM_8723D 0x0552 304 #define REG_DUAL_TSF_RST_8723D 0x0553 305 #define REG_BCN_INTERVAL_8723D 0x0554 306 #define REG_DRVERLYINT_8723D 0x0558 307 #define REG_BCNDMATIM_8723D 0x0559 308 #define REG_ATIMWND_8723D 0x055A 309 #define REG_USTIME_TSF_8723D 0x055C 310 #define REG_BCN_MAX_ERR_8723D 0x055D 311 #define REG_RXTSF_OFFSET_CCK_8723D 0x055E 312 #define REG_RXTSF_OFFSET_OFDM_8723D 0x055F 313 #define REG_TSFTR_8723D 0x0560 314 #define REG_CTWND_8723D 0x0572 315 #define REG_SECONDARY_CCA_CTRL_8723D 0x0577 316 #define REG_PSTIMER_8723D 0x0580 317 #define REG_TIMER0_8723D 0x0584 318 #define REG_TIMER1_8723D 0x0588 319 #define REG_ACMHWCTRL_8723D 0x05C0 320 #define REG_SCH_TXCMD_8723D 0x05F8 321 322 /* ----------------------------------------------------- 323 * 324 * 0x0600h ~ 0x07FFh WMAC Configuration 325 * 326 * ----------------------------------------------------- */ 327 #define REG_MAC_CR_8723D 0x0600 328 #define REG_TCR_8723D 0x0604 329 #define REG_RCR_8723D 0x0608 330 #define REG_RX_PKT_LIMIT_8723D 0x060C 331 #define REG_RX_DLK_TIME_8723D 0x060D 332 #define REG_RX_DRVINFO_SZ_8723D 0x060F 333 334 #define REG_MACID_8723D 0x0610 335 #define REG_BSSID_8723D 0x0618 336 #define REG_MAR_8723D 0x0620 337 #define REG_MBIDCAMCFG_8723D 0x0628 338 #define REG_WOWLAN_GTK_DBG1 0x630 339 #define REG_WOWLAN_GTK_DBG2 0x634 340 341 #define REG_USTIME_EDCA_8723D 0x0638 342 #define REG_MAC_SPEC_SIFS_8723D 0x063A 343 #define REG_RESP_SIFP_CCK_8723D 0x063C 344 #define REG_RESP_SIFS_OFDM_8723D 0x063E 345 #define REG_ACKTO_8723D 0x0640 346 #define REG_CTS2TO_8723D 0x0641 347 #define REG_EIFS_8723D 0x0642 348 349 #define REG_NAV_UPPER_8723D 0x0652 /* unit of 128 */ 350 #define REG_TRXPTCL_CTL_8723D 0x0668 351 352 /* Security */ 353 #define REG_CAMCMD_8723D 0x0670 354 #define REG_CAMWRITE_8723D 0x0674 355 #define REG_CAMREAD_8723D 0x0678 356 #define REG_CAMDBG_8723D 0x067C 357 #define REG_SECCFG_8723D 0x0680 358 359 /* Power */ 360 #define REG_WOW_CTRL_8723D 0x0690 361 #define REG_PS_RX_INFO_8723D 0x0692 362 #define REG_UAPSD_TID_8723D 0x0693 363 #define REG_WKFMCAM_CMD_8723D 0x0698 364 #define REG_WKFMCAM_NUM_8723D 0x0698 365 #define REG_WKFMCAM_RWD_8723D 0x069C 366 #define REG_RXFLTMAP0_8723D 0x06A0 367 #define REG_RXFLTMAP1_8723D 0x06A2 368 #define REG_RXFLTMAP2_8723D 0x06A4 369 #define REG_BCN_PSR_RPT_8723D 0x06A8 370 #define REG_BT_COEX_TABLE_8723D 0x06C0 371 #define REG_BFMER0_INFO_8723D 0x06E4 372 #define REG_BFMER1_INFO_8723D 0x06EC 373 #define REG_CSI_RPT_PARAM_BW20_8723D 0x06F4 374 #define REG_CSI_RPT_PARAM_BW40_8723D 0x06F8 375 #define REG_CSI_RPT_PARAM_BW80_8723D 0x06FC 376 377 /* Hardware Port 2 */ 378 #define REG_MACID1_8723D 0x0700 379 #define REG_BSSID1_8723D 0x0708 380 #define REG_BFMEE_SEL_8723D 0x0714 381 #define REG_SND_PTCL_CTRL_8723D 0x0718 382 383 /* LTE_COEX */ 384 #define REG_LTECOEX_CTRL 0x07C0 385 #define REG_LTECOEX_WRITE_DATA 0x07C4 386 #define REG_LTECOEX_READ_DATA 0x07C8 387 #define REG_LTECOEX_PATH_CONTROL 0x70 388 389 /* ************************************************************ 390 * SDIO Bus Specification 391 * ************************************************************ */ 392 393 /* ----------------------------------------------------- 394 * SDIO CMD Address Mapping 395 * ----------------------------------------------------- */ 396 397 /* ----------------------------------------------------- 398 * I/O bus domain (Host) 399 * ----------------------------------------------------- */ 400 401 /* ----------------------------------------------------- 402 * SDIO register 403 * ----------------------------------------------------- */ 404 #define SDIO_REG_HCPWM1_8723D 0x025 /* HCI Current Power Mode 1 */ 405 406 407 /* **************************************************************************** 408 * 8723 Regsiter Bit and Content definition 409 * **************************************************************************** */ 410 411 #define BIT_USB_RXDMA_AGG_EN BIT(31) 412 #define RXDMA_AGG_MODE_EN BIT(1) 413 414 #ifdef CONFIG_WOWLAN 415 #define RXPKT_RELEASE_POLL BIT(16) 416 #define RXDMA_IDLE BIT(17) 417 #define RW_RELEASE_EN BIT(18) 418 #endif 419 420 /* 2 HSISR 421 * interrupt mask which needs to clear */ 422 #define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\ 423 HSISR_SPS_OCP_INT |\ 424 HSISR_RON_INT |\ 425 HSISR_PDNINT |\ 426 HSISR_GPIO9_INT) 427 428 #ifdef CONFIG_RF_POWER_TRIM 429 #ifdef CONFIG_RTL8723D 430 #define EEPROM_RF_GAIN_OFFSET 0xC1 431 #endif 432 433 #define EEPROM_RF_GAIN_VAL 0x1F6 434 #endif /*CONFIG_RF_POWER_TRIM*/ 435 436 #ifdef CONFIG_PCI_HCI 437 /* #define IMR_RX_MASK (IMR_ROK_8723D|IMR_RDU_8723D|IMR_RXFOVW_8723D) */ 438 #define IMR_TX_MASK (IMR_VODOK_8723D | IMR_VIDOK_8723D | IMR_BEDOK_8723D | IMR_BKDOK_8723D | IMR_MGNTDOK_8723D | IMR_HIGHDOK_8723D) 439 440 #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8723D | IMR_TXBCN0OK_8723D | IMR_TXBCN0ERR_8723D | IMR_BCNDERR0_8723D) 441 442 #define RT_AC_INT_MASKS (IMR_VIDOK_8723D | IMR_VODOK_8723D | IMR_BEDOK_8723D | IMR_BKDOK_8723D) 443 #endif 444 445 /* ******************************************************** 446 * General definitions 447 * ******************************************************** */ 448 449 #define MACID_NUM_8723D 16 450 #define SEC_CAM_ENT_NUM_8723D 32 451 #define HW_PORT_NUM_8723D 3 /*port0, port1, port2*/ 452 #define NSS_NUM_8723D 1 453 #define BAND_CAP_8723D (BAND_CAP_2G) 454 #define BW_CAP_8723D (BW_CAP_20M | BW_CAP_40M) 455 #define PROTO_CAP_8723D (PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N) 456 457 #endif /* __RTL8723D_SPEC_H__ */ 458