1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 #ifndef __HAL_DATA_H__ 21 #define __HAL_DATA_H__ 22 23 #if 1/* def CONFIG_SINGLE_IMG */ 24 25 #include "../hal/phydm/phydm_precomp.h" 26 #ifdef CONFIG_BT_COEXIST 27 #include <hal_btcoex.h> 28 #endif 29 30 #ifdef CONFIG_SDIO_HCI 31 #include <hal_sdio.h> 32 #endif 33 #ifdef CONFIG_GSPI_HCI 34 #include <hal_gspi.h> 35 #endif 36 /* 37 * <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. 38 * */ 39 typedef enum _RT_MULTI_FUNC { 40 RT_MULTI_FUNC_NONE = 0x00, 41 RT_MULTI_FUNC_WIFI = 0x01, 42 RT_MULTI_FUNC_BT = 0x02, 43 RT_MULTI_FUNC_GPS = 0x04, 44 } RT_MULTI_FUNC, *PRT_MULTI_FUNC; 45 /* 46 * <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. 47 * */ 48 typedef enum _RT_POLARITY_CTL { 49 RT_POLARITY_LOW_ACT = 0, 50 RT_POLARITY_HIGH_ACT = 1, 51 } RT_POLARITY_CTL, *PRT_POLARITY_CTL; 52 53 /* For RTL8723 regulator mode. by tynli. 2011.01.14. */ 54 typedef enum _RT_REGULATOR_MODE { 55 RT_SWITCHING_REGULATOR = 0, 56 RT_LDO_REGULATOR = 1, 57 } RT_REGULATOR_MODE, *PRT_REGULATOR_MODE; 58 59 /* 60 * Interface type. 61 * */ 62 typedef enum _INTERFACE_SELECT_PCIE { 63 INTF_SEL0_SOLO_MINICARD = 0, /* WiFi solo-mCard */ 64 INTF_SEL1_BT_COMBO_MINICARD = 1, /* WiFi+BT combo-mCard */ 65 INTF_SEL2_PCIe = 2, /* PCIe Card */ 66 } INTERFACE_SELECT_PCIE, *PINTERFACE_SELECT_PCIE; 67 68 69 typedef enum _INTERFACE_SELECT_USB { 70 INTF_SEL0_USB = 0, /* USB */ 71 INTF_SEL1_USB_High_Power = 1, /* USB with high power PA */ 72 INTF_SEL2_MINICARD = 2, /* Minicard */ 73 INTF_SEL3_USB_Solo = 3, /* USB solo-Slim module */ 74 INTF_SEL4_USB_Combo = 4, /* USB Combo-Slim module */ 75 INTF_SEL5_USB_Combo_MF = 5, /* USB WiFi+BT Multi-Function Combo, i.e., Proprietary layout(AS-VAU) which is the same as SDIO card */ 76 } INTERFACE_SELECT_USB, *PINTERFACE_SELECT_USB; 77 78 typedef enum _RT_AMPDU_BRUST_MODE { 79 RT_AMPDU_BRUST_NONE = 0, 80 RT_AMPDU_BRUST_92D = 1, 81 RT_AMPDU_BRUST_88E = 2, 82 RT_AMPDU_BRUST_8812_4 = 3, 83 RT_AMPDU_BRUST_8812_8 = 4, 84 RT_AMPDU_BRUST_8812_12 = 5, 85 RT_AMPDU_BRUST_8812_15 = 6, 86 RT_AMPDU_BRUST_8723B = 7, 87 } RT_AMPDU_BRUST, *PRT_AMPDU_BRUST_MODE; 88 89 #if 0 90 #define CHANNEL_MAX_NUMBER 14+24+21 /* 14 is the max channel number */ 91 #endif 92 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, ch4~9, ch10~14 total three groups */ 93 #define MAX_PG_GROUP 13 94 95 /* Tx Power Limit Table Size */ 96 #define MAX_REGULATION_NUM 4 97 #define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE 4 98 #define MAX_2_4G_BANDWIDTH_NUM 2 99 #define MAX_RATE_SECTION_NUM 10 100 #define MAX_5G_BANDWIDTH_NUM 4 101 102 #define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 10 /* CCK:1, OFDM:1, HT:4, VHT:4 */ 103 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 9 /* OFDM:1, HT:4, VHT:4 */ 104 105 106 /* ###### duplicate code,will move to ODM ######### */ 107 /* #define IQK_MAC_REG_NUM 4 */ 108 /* #define IQK_ADDA_REG_NUM 16 */ 109 110 /* #define IQK_BB_REG_NUM 10 */ 111 #define IQK_BB_REG_NUM_92C 9 112 #define IQK_BB_REG_NUM_92D 10 113 #define IQK_BB_REG_NUM_test 6 114 115 #define IQK_Matrix_Settings_NUM_92D (1+24+21) 116 117 /* #define HP_THERMAL_NUM 8 */ 118 /* ###### duplicate code,will move to ODM ######### */ 119 120 #ifdef RTW_RX_AGGREGATION 121 typedef enum _RX_AGG_MODE { 122 RX_AGG_DISABLE, 123 RX_AGG_DMA, 124 RX_AGG_USB, 125 RX_AGG_MIX 126 } RX_AGG_MODE; 127 128 /* #define MAX_RX_DMA_BUFFER_SIZE 10240 */ /* 10K for 8192C RX DMA buffer */ 129 130 #endif /* RTW_RX_AGGREGATION */ 131 132 /* For store initial value of BB register */ 133 typedef struct _BB_INIT_REGISTER { 134 u16 offset; 135 u32 value; 136 137 } BB_INIT_REGISTER, *PBB_INIT_REGISTER; 138 139 #define PAGE_SIZE_128 128 140 #define PAGE_SIZE_256 256 141 #define PAGE_SIZE_512 512 142 143 #define HCI_SUS_ENTER 0 144 #define HCI_SUS_LEAVING 1 145 #define HCI_SUS_LEAVE 2 146 #define HCI_SUS_ENTERING 3 147 #define HCI_SUS_ERR 4 148 149 #ifdef CONFIG_AUTO_CHNL_SEL_NHM 150 typedef enum _ACS_OP { 151 ACS_INIT, /*ACS - Variable init*/ 152 ACS_RESET, /*ACS - NHM Counter reset*/ 153 ACS_SELECT, /*ACS - NHM Counter Statistics */ 154 } ACS_OP; 155 156 typedef enum _ACS_STATE { 157 ACS_DISABLE, 158 ACS_ENABLE, 159 } ACS_STATE; 160 161 struct auto_chan_sel { 162 ATOMIC_T state; 163 u8 ch; /* previous channel*/ 164 }; 165 #endif /*CONFIG_AUTO_CHNL_SEL_NHM*/ 166 167 #define EFUSE_FILE_UNUSED 0 168 #define EFUSE_FILE_FAILED 1 169 #define EFUSE_FILE_LOADED 2 170 171 #define MACADDR_FILE_UNUSED 0 172 #define MACADDR_FILE_FAILED 1 173 #define MACADDR_FILE_LOADED 2 174 175 #define KFREE_FLAG_ON BIT0 176 #define KFREE_FLAG_THERMAL_K_ON BIT1 177 178 #define MAX_IQK_INFO_BACKUP_CHNL_NUM 5 179 #define MAX_IQK_INFO_BACKUP_REG_NUM 10 180 181 struct kfree_data_t { 182 u8 flag; 183 s8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX]; 184 185 #ifdef CONFIG_IEEE80211_BAND_5GHZ 186 s8 pa_bias_5g[RF_PATH_MAX]; 187 s8 pad_bias_5g[RF_PATH_MAX]; 188 #endif 189 s8 thermal; 190 }; 191 192 bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data); 193 194 struct hal_spec_t { 195 u8 macid_num; 196 197 u8 sec_cam_ent_num; 198 u8 sec_cap; 199 200 u8 nss_num; 201 u8 band_cap; /* value of BAND_CAP_XXX */ 202 u8 bw_cap; /* value of BW_CAP_XXX */ 203 u8 port_num; 204 u8 proto_cap; /* value of PROTO_CAP_XXX */ 205 u8 wl_func; /* value of WL_FUNC_XXX */ 206 }; 207 208 struct hal_iqk_reg_backup { 209 u8 central_chnl; 210 u8 bw_mode; 211 u32 reg_backup[MAX_RF_PATH][MAX_IQK_INFO_BACKUP_REG_NUM]; 212 }; 213 214 typedef struct hal_com_data { 215 HAL_VERSION VersionID; 216 RT_MULTI_FUNC MultiFunc; /* For multi-function consideration. */ 217 RT_POLARITY_CTL PolarityCtl; /* For Wifi PDn Polarity control. */ 218 RT_REGULATOR_MODE RegulatorMode; /* switching regulator or LDO */ 219 u8 hw_init_completed; 220 /****** FW related ******/ 221 u16 FirmwareVersion; 222 u16 FirmwareVersionRev; 223 u16 FirmwareSubVersion; 224 u16 FirmwareSignature; 225 u8 RegFWOffload; 226 u8 fw_ractrl; 227 u8 FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.*/ 228 u8 LastHMEBoxNum; /* H2C - for host message to fw */ 229 230 /****** current WIFI_PHY values ******/ 231 WIRELESS_MODE CurrentWirelessMode; 232 CHANNEL_WIDTH CurrentChannelBW; 233 BAND_TYPE CurrentBandType; /* 0:2.4G, 1:5G */ 234 BAND_TYPE BandSet; 235 u8 CurrentChannel; 236 u8 CurrentCenterFrequencyIndex1; 237 u8 nCur40MhzPrimeSC; /* Control channel sub-carrier */ 238 u8 nCur80MhzPrimeSC; /* used for primary 40MHz of 80MHz mode */ 239 BOOLEAN bSwChnlAndSetBWInProgress; 240 u8 bDisableSWChannelPlan; /* flag of disable software change channel plan */ 241 u16 BasicRateSet; 242 u32 ReceiveConfig; 243 u8 rx_tsf_addr_filter_config; /* for 8822B/8821C USE */ 244 BOOLEAN bSwChnl; 245 BOOLEAN bSetChnlBW; 246 BOOLEAN bSWToBW40M; 247 BOOLEAN bSWToBW80M; 248 BOOLEAN bChnlBWInitialized; 249 u32 BackUp_BB_REG_4_2nd_CCA[3]; 250 #ifdef CONFIG_AUTO_CHNL_SEL_NHM 251 struct auto_chan_sel acs; 252 #endif 253 /****** rf_ctrl *****/ 254 u8 rf_chip; 255 u8 rf_type; 256 u8 PackageType; 257 u8 NumTotalRFPath; 258 u8 antenna_test; 259 260 /****** Debug ******/ 261 u16 ForcedDataRate; /* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */ 262 u8 u1ForcedIgiLb; /* forced IGI lower bound */ 263 u8 bDumpRxPkt; 264 u8 bDumpTxPkt; 265 u8 bDisableTXPowerTraining; 266 267 268 /****** EEPROM setting.******/ 269 u8 bautoload_fail_flag; 270 u8 efuse_file_status; 271 u8 macaddr_file_status; 272 u8 EepromOrEfuse; 273 u8 efuse_eeprom_data[EEPROM_MAX_SIZE]; /*92C:256bytes, 88E:512bytes, we use union set (512bytes)*/ 274 u8 InterfaceSel; /* board type kept in eFuse */ 275 u16 CustomerID; 276 277 u16 EEPROMVID; 278 u16 EEPROMSVID; 279 #ifdef CONFIG_USB_HCI 280 u8 EEPROMUsbSwitch; 281 u16 EEPROMPID; 282 u16 EEPROMSDID; 283 #endif 284 #ifdef CONFIG_PCI_HCI 285 u16 EEPROMDID; 286 u16 EEPROMSMID; 287 #endif 288 289 u8 EEPROMCustomerID; 290 u8 EEPROMSubCustomerID; 291 u8 EEPROMVersion; 292 u8 EEPROMRegulatory; 293 u8 EEPROMThermalMeter; 294 u8 EEPROMBluetoothCoexist; 295 u8 EEPROMBluetoothType; 296 u8 EEPROMBluetoothAntNum; 297 u8 EEPROMBluetoothAntIsolation; 298 u8 EEPROMBluetoothRadioShared; 299 u8 bTXPowerDataReadFromEEPORM; 300 u8 EEPROMMACAddr[ETH_ALEN]; 301 #ifdef RTW_TX_PA_BIAS 302 u8 tx_pa_bias_a; /* TX PA Bias for Path A */ 303 u8 tx_pa_bias_b; /* TX PA Bias for Path B */ 304 #endif /* RTW_TX_PA_BIAS */ 305 306 #ifdef CONFIG_RF_POWER_TRIM 307 u8 EEPROMRFGainOffset; 308 u8 EEPROMRFGainVal; 309 struct kfree_data_t kfree_data; 310 #endif /*CONFIG_RF_POWER_TRIM*/ 311 312 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || \ 313 defined(CONFIG_RTL8723D) 314 u8 adjuseVoltageVal; 315 u8 need_restore; 316 #endif 317 u8 EfuseUsedPercentage; 318 u16 EfuseUsedBytes; 319 /*u8 EfuseMap[2][HWSET_MAX_SIZE_JAGUAR];*/ 320 EFUSE_HAL EfuseHal; 321 322 /*---------------------------------------------------------------------------------*/ 323 /* 3 [2.4G] */ 324 u8 Index24G_CCK_Base[MAX_RF_PATH][CENTER_CH_2G_NUM]; 325 u8 Index24G_BW40_Base[MAX_RF_PATH][CENTER_CH_2G_NUM]; 326 /* If only one tx, only BW20 and OFDM are used. */ 327 s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 328 s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 329 s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 330 s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 331 /* 3 [5G] */ 332 u8 Index5G_BW40_Base[MAX_RF_PATH][CENTER_CH_5G_ALL_NUM]; 333 u8 Index5G_BW80_Base[MAX_RF_PATH][CENTER_CH_5G_80M_NUM]; 334 s8 OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 335 s8 BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 336 s8 BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 337 s8 BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 338 339 u8 Regulation2_4G; 340 u8 Regulation5G; 341 342 u8 TxPwrInPercentage; 343 344 /******************************** 345 * TX power by rate table at most 4RF path. 346 * The register is 347 * 348 * VHT TX power by rate off setArray = 349 * Band:-2G&5G = 0 / 1 350 * RF: at most 4*4 = ABCD=0/1/2/3 351 * CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11 352 **********************************/ 353 u8 TxPwrByRateTable; 354 u8 TxPwrByRateBand; 355 s8 TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND] 356 [TX_PWR_BY_RATE_NUM_RF] 357 [TX_PWR_BY_RATE_NUM_RF] 358 [TX_PWR_BY_RATE_NUM_RATE]; 359 360 #ifdef CONFIG_PHYDM_POWERTRACK_BY_TSSI 361 s8 TxPwrByRate[TX_PWR_BY_RATE_NUM_BAND] 362 [TX_PWR_BY_RATE_NUM_RF] 363 [TX_PWR_BY_RATE_NUM_RF] 364 [TX_PWR_BY_RATE_NUM_RATE]; 365 #endif 366 /* --------------------------------------------------------------------------------- */ 367 368 #if 0 369 /* 2 Power Limit Table */ 370 u8 TxPwrLevelCck[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; 371 u8 TxPwrLevelHT40_1S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; /* For HT 40MHZ pwr */ 372 u8 TxPwrLevelHT40_2S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; /* For HT 40MHZ pwr */ 373 s8 TxPwrHt20Diff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];/* HT 20<->40 Pwr diff */ 374 u8 TxPwrLegacyHtDiff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];/* For HT<->legacy pwr diff */ 375 #endif 376 377 u8 tx_pwr_lmt_5g_20_40_ref; 378 379 /* Power Limit Table for 2.4G */ 380 s8 TxPwrLimit_2_4G[MAX_REGULATION_NUM] 381 [MAX_2_4G_BANDWIDTH_NUM] 382 [MAX_RATE_SECTION_NUM] 383 [CENTER_CH_2G_NUM] 384 [MAX_RF_PATH]; 385 386 /* Power Limit Table for 5G */ 387 s8 TxPwrLimit_5G[MAX_REGULATION_NUM] 388 [MAX_5G_BANDWIDTH_NUM] 389 [MAX_RATE_SECTION_NUM] 390 [CENTER_CH_5G_ALL_NUM] 391 [MAX_RF_PATH]; 392 393 394 #ifdef CONFIG_PHYDM_POWERTRACK_BY_TSSI 395 s8 TxPwrLimit_2_4G_Original[MAX_REGULATION_NUM] 396 [MAX_2_4G_BANDWIDTH_NUM] 397 [MAX_RATE_SECTION_NUM] 398 [CENTER_CH_2G_NUM] 399 [MAX_RF_PATH]; 400 401 402 s8 TxPwrLimit_5G_Original[MAX_REGULATION_NUM] 403 [MAX_5G_BANDWIDTH_NUM] 404 [MAX_RATE_SECTION_NUM] 405 [CENTER_CH_5G_ALL_NUM] 406 [MAX_RF_PATH]; 407 408 #endif 409 410 /* Store the original power by rate value of the base of each rate section of rf path A & B */ 411 u8 TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF] 412 [TX_PWR_BY_RATE_NUM_RF] 413 [MAX_BASE_NUM_IN_PHY_REG_PG_2_4G]; 414 u8 TxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF] 415 [TX_PWR_BY_RATE_NUM_RF] 416 [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; 417 418 u8 txpwr_by_rate_loaded:1; 419 u8 txpwr_by_rate_from_file:1; 420 u8 txpwr_limit_loaded:1; 421 u8 txpwr_limit_from_file:1; 422 u8 RfPowerTrackingType; 423 424 /* For power group */ 425 /* 426 u8 PwrGroupHT20[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; 427 u8 PwrGroupHT40[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; 428 */ 429 u8 PGMaxGroup; 430 431 /* The current Tx Power Level */ 432 u8 CurrentCckTxPwrIdx; 433 u8 CurrentOfdm24GTxPwrIdx; 434 u8 CurrentBW2024GTxPwrIdx; 435 u8 CurrentBW4024GTxPwrIdx; 436 437 /* Read/write are allow for following hardware information variables */ 438 u8 pwrGroupCnt; 439 u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16]; 440 u32 CCKTxPowerLevelOriginalOffset; 441 442 u8 CrystalCap; 443 444 u8 PAType_2G; 445 u8 PAType_5G; 446 u8 LNAType_2G; 447 u8 LNAType_5G; 448 u8 ExternalPA_2G; 449 u8 ExternalLNA_2G; 450 u8 ExternalPA_5G; 451 u8 ExternalLNA_5G; 452 u16 TypeGLNA; 453 u16 TypeGPA; 454 u16 TypeALNA; 455 u16 TypeAPA; 456 u16 RFEType; 457 458 u8 bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */ 459 u32 AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */ 460 461 BB_REGISTER_DEFINITION_T PHYRegDef[MAX_RF_PATH]; /* Radio A/B/C/D */ 462 463 u32 RfRegChnlVal[MAX_RF_PATH]; 464 465 /* RDG enable */ 466 BOOLEAN bRDGEnable; 467 468 u8 RegTxPause; 469 /* Beacon function related global variable. */ 470 u8 RegBcnCtrlVal; 471 u8 RegFwHwTxQCtrl; 472 u8 RegReg542; 473 u8 RegCR_1; 474 u8 Reg837; 475 u16 RegRRSR; 476 477 /****** antenna diversity ******/ 478 u8 AntDivCfg; 479 u8 AntDetection; 480 u8 TRxAntDivType; 481 u8 ant_path; /* for 8723B s0/s1 selection */ 482 u32 AntennaTxPath; /* Antenna path Tx */ 483 u32 AntennaRxPath; /* Antenna path Rx */ 484 u8 sw_antdiv_bl_state; 485 486 /******** PHY DM & DM Section **********/ 487 u8 DM_Type; 488 _lock IQKSpinLock; 489 u8 INIDATA_RATE[MACID_NUM_SW_LIMIT]; 490 /* Upper and Lower Signal threshold for Rate Adaptive*/ 491 int EntryMinUndecoratedSmoothedPWDB; 492 int EntryMaxUndecoratedSmoothedPWDB; 493 int MinUndecoratedPWDBForDM; 494 DM_ODM_T odmpriv; 495 u8 bIQKInitialized; 496 u8 bNeedIQK; 497 u8 IQK_MP_Switch; 498 /******** PHY DM & DM Section **********/ 499 500 501 502 /* 2010/08/09 MH Add CU power down mode. */ 503 BOOLEAN pwrdown; 504 505 /* Add for dual MAC 0--Mac0 1--Mac1 */ 506 u32 interfaceIndex; 507 508 #ifdef CONFIG_P2P 509 u8 p2p_ps_offload; 510 #endif 511 /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */ 512 u8 bMacPwrCtrlOn; 513 u8 hci_sus_state; 514 515 u8 RegIQKFWOffload; 516 struct submit_ctx iqk_sctx; 517 518 RT_AMPDU_BRUST AMPDUBurstMode; /* 92C maybe not use, but for compile successfully */ 519 520 u8 OutEpQueueSel; 521 u8 OutEpNumber; 522 523 #ifdef RTW_RX_AGGREGATION 524 RX_AGG_MODE rxagg_mode; 525 526 /* For RX Aggregation DMA Mode */ 527 u8 rxagg_dma_size; 528 u8 rxagg_dma_timeout; 529 #endif /* RTW_RX_AGGREGATION */ 530 531 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) 532 /* */ 533 /* For SDIO Interface HAL related */ 534 /* */ 535 536 /* */ 537 /* SDIO ISR Related */ 538 /* 539 * u32 IntrMask[1]; 540 * u32 IntrMaskToSet[1]; 541 * LOG_INTERRUPT InterruptLog; */ 542 u32 sdio_himr; 543 u32 sdio_hisr; 544 #ifndef RTW_HALMAC 545 /* */ 546 /* SDIO Tx FIFO related. */ 547 /* */ 548 /* HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg */ 549 u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE]; 550 _lock SdioTxFIFOFreePageLock; 551 u8 SdioTxOQTMaxFreeSpace; 552 u8 SdioTxOQTFreeSpace; 553 #else /* RTW_HALMAC */ 554 u16 SdioTxOQTFreeSpace; 555 #endif /* RTW_HALMAC */ 556 557 /* */ 558 /* SDIO Rx FIFO related. */ 559 /* */ 560 u8 SdioRxFIFOCnt; 561 u16 SdioRxFIFOSize; 562 563 #ifndef RTW_HALMAC 564 u32 sdio_tx_max_len[SDIO_MAX_TX_QUEUE];/* H, N, L, used for sdio tx aggregation max length per queue */ 565 #else 566 #ifdef CONFIG_RTL8821C 567 u16 tx_high_page; 568 u16 tx_low_page; 569 u16 tx_normal_page; 570 u16 tx_extra_page; 571 u16 tx_pub_page; 572 u16 max_oqt_page; 573 u32 max_xmit_size_vovi; 574 u32 max_xmit_size_bebk; 575 #endif 576 #endif /* !RTW_HALMAC */ 577 #endif /* CONFIG_SDIO_HCI */ 578 579 #ifdef CONFIG_USB_HCI 580 581 /* 2010/12/10 MH Add for USB aggreation mode dynamic shceme. */ 582 BOOLEAN UsbRxHighSpeedMode; 583 BOOLEAN UsbTxVeryHighSpeedMode; 584 u32 UsbBulkOutSize; 585 BOOLEAN bSupportUSB3; 586 587 /* Interrupt relatd register information. */ 588 u32 IntArray[3];/* HISR0,HISR1,HSISR */ 589 u32 IntrMask[3]; 590 u8 C2hArray[16]; 591 #ifdef CONFIG_USB_TX_AGGREGATION 592 u8 UsbTxAggMode; 593 u8 UsbTxAggDescNum; 594 #endif /* CONFIG_USB_TX_AGGREGATION */ 595 596 #ifdef CONFIG_USB_RX_AGGREGATION 597 u16 HwRxPageSize; /* Hardware setting */ 598 599 /* For RX Aggregation USB Mode */ 600 u8 rxagg_usb_size; 601 u8 rxagg_usb_timeout; 602 #endif/* CONFIG_USB_RX_AGGREGATION */ 603 #endif /* CONFIG_USB_HCI */ 604 605 606 #ifdef CONFIG_PCI_HCI 607 /* */ 608 /* EEPROM setting. */ 609 /* */ 610 u32 TransmitConfig; 611 u32 IntrMaskToSet[2]; 612 u32 IntArray[4]; 613 u32 IntrMask[4]; 614 u32 SysIntArray[1]; 615 u32 SysIntrMask[1]; 616 u32 IntrMaskReg[2]; 617 u32 IntrMaskDefault[4]; 618 619 BOOLEAN bL1OffSupport; 620 BOOLEAN bSupportBackDoor; 621 622 u8 bDefaultAntenna; 623 624 u8 bInterruptMigration; 625 u8 bDisableTxInt; 626 627 u16 RxTag; 628 #endif /* CONFIG_PCI_HCI */ 629 630 631 #ifdef DBG_CONFIG_ERROR_DETECT 632 struct sreset_priv srestpriv; 633 #endif /* #ifdef DBG_CONFIG_ERROR_DETECT */ 634 635 #ifdef CONFIG_BT_COEXIST 636 /* For bluetooth co-existance */ 637 BT_COEXIST bt_coexist; 638 #endif /* CONFIG_BT_COEXIST */ 639 640 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) \ 641 || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8723D) 642 #ifndef CONFIG_PCI_HCI /* mutual exclusive with PCI -- so they're SDIO and GSPI */ 643 /* Interrupt relatd register information. */ 644 u32 SysIntrStatus; 645 u32 SysIntrMask; 646 #endif 647 #endif /*endif CONFIG_RTL8723B */ 648 649 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE 650 char para_file_buf[MAX_PARA_FILE_BUF_LEN]; 651 char *mac_reg; 652 u32 mac_reg_len; 653 char *bb_phy_reg; 654 u32 bb_phy_reg_len; 655 char *bb_agc_tab; 656 u32 bb_agc_tab_len; 657 char *bb_phy_reg_pg; 658 u32 bb_phy_reg_pg_len; 659 char *bb_phy_reg_mp; 660 u32 bb_phy_reg_mp_len; 661 char *rf_radio_a; 662 u32 rf_radio_a_len; 663 char *rf_radio_b; 664 u32 rf_radio_b_len; 665 char *rf_tx_pwr_track; 666 u32 rf_tx_pwr_track_len; 667 char *rf_tx_pwr_lmt; 668 u32 rf_tx_pwr_lmt_len; 669 #endif 670 671 #ifdef CONFIG_BACKGROUND_NOISE_MONITOR 672 s16 noise[ODM_MAX_CHANNEL_NUM]; 673 #endif 674 675 struct hal_spec_t hal_spec; 676 677 u8 RfKFreeEnable; 678 u8 RfKFree_ch_group; 679 BOOLEAN bCCKinCH14; 680 BB_INIT_REGISTER RegForRecover[5]; 681 682 #if defined(CONFIG_PCI_HCI) && defined(RTL8814AE_SW_BCN) 683 BOOLEAN bCorrectBCN; 684 #endif 685 u32 RxGainOffset[4]; /*{2G, 5G_Low, 5G_Middle, G_High}*/ 686 u8 BackUp_IG_REG_4_Chnl_Section[4]; /*{A,B,C,D}*/ 687 688 struct hal_iqk_reg_backup iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM]; 689 690 #ifdef CONFIG_BEAMFORMING 691 #ifdef RTW_BEAMFORMING_VERSION_2 692 struct beamforming_info beamforming_info; 693 #endif /* RTW_BEAMFORMING_VERSION_2 */ 694 #endif /* CONFIG_BEAMFORMING */ 695 } HAL_DATA_COMMON, *PHAL_DATA_COMMON; 696 697 698 699 typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE; 700 #define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData)) 701 #define GET_HAL_SPEC(__pAdapter) (&(GET_HAL_DATA((__pAdapter))->hal_spec)) 702 #define GET_ODM(__pAdapter) (&(GET_HAL_DATA((__pAdapter))->odmpriv)) 703 704 #define GET_HAL_RFPATH_NUM(__pAdapter) (((HAL_DATA_TYPE *)((__pAdapter)->HalData))->NumTotalRFPath) 705 #define RT_GetInterfaceSelection(_Adapter) (GET_HAL_DATA(_Adapter)->InterfaceSel) 706 #define GET_RF_TYPE(__pAdapter) (GET_HAL_DATA(__pAdapter)->rf_type) 707 #define GET_KFREE_DATA(_adapter) (&(GET_HAL_DATA((_adapter))->kfree_data)) 708 709 #define SUPPORT_HW_RADIO_DETECT(Adapter) (RT_GetInterfaceSelection(Adapter) == INTF_SEL2_MINICARD || \ 710 RT_GetInterfaceSelection(Adapter) == INTF_SEL3_USB_Solo || \ 711 RT_GetInterfaceSelection(Adapter) == INTF_SEL4_USB_Combo) 712 713 #define get_hal_mac_addr(adapter) (GET_HAL_DATA(adapter)->EEPROMMACAddr) 714 #define is_boot_from_eeprom(adapter) (GET_HAL_DATA(adapter)->EepromOrEfuse) 715 #define rtw_get_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed) 716 #define rtw_is_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed == _TRUE) 717 #endif 718 719 #ifdef CONFIG_AUTO_CHNL_SEL_NHM 720 #define GET_ACS_STATE(padapter) (ATOMIC_READ(&GET_HAL_DATA(padapter)->acs.state)) 721 #define SET_ACS_STATE(padapter, set_state) (ATOMIC_SET(&GET_HAL_DATA(padapter)->acs.state, set_state)) 722 #define rtw_get_acs_channel(padapter) (GET_HAL_DATA(padapter)->acs.ch) 723 #define rtw_set_acs_channel(padapter, survey_ch) (GET_HAL_DATA(padapter)->acs.ch = survey_ch) 724 #endif /*CONFIG_AUTO_CHNL_SEL_NHM*/ 725 726 #ifdef RTW_HALMAC 727 int rtw_halmac_deinit_adapter(struct dvobj_priv *); 728 #endif /* RTW_HALMAC */ 729 730 #endif /* __HAL_DATA_H__ */ 731