1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 #ifndef __INC_HAL8812PHYREG_H__ 21 #define __INC_HAL8812PHYREG_H__ 22 /*--------------------------Define Parameters-------------------------------*/ 23 /* 24 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF 25 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 26 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 27 * 3. RF register 0x00-2E 28 * 4. Bit Mask for BB/RF register 29 * 5. Other defintion for BB/RF R/W 30 * */ 31 32 33 /* BB Register Definition */ 34 35 #define rCCAonSec_Jaguar 0x838 36 #define rPwed_TH_Jaguar 0x830 37 38 /* BW and sideband setting */ 39 #define rBWIndication_Jaguar 0x834 40 #define rL1PeakTH_Jaguar 0x848 41 #define rFPGA0_XA_LSSIReadBack 0x8a0 /*Tranceiver LSSI Readback*/ 42 #define rRFMOD_Jaguar 0x8ac /* RF mode */ 43 #define rADC_Buf_Clk_Jaguar 0x8c4 44 #define rRFECTRL_Jaguar 0x900 45 #define bRFMOD_Jaguar 0xc3 46 #define rCCK_System_Jaguar 0xa00 /* for cck sideband */ 47 #define bCCK_System_Jaguar 0x10 48 49 /* Block & Path enable */ 50 #define rOFDMCCKEN_Jaguar 0x808 /* OFDM/CCK block enable */ 51 #define bOFDMEN_Jaguar 0x20000000 52 #define bCCKEN_Jaguar 0x10000000 53 #define rRxPath_Jaguar 0x808 /* Rx antenna */ 54 #define bRxPath_Jaguar 0xff 55 #define rTxPath_Jaguar 0x80c /* Tx antenna */ 56 #define bTxPath_Jaguar 0x0fffffff 57 #define rCCK_RX_Jaguar 0xa04 /* for cck rx path selection */ 58 #define bCCK_RX_Jaguar 0x0c000000 59 #define rVhtlen_Use_Lsig_Jaguar 0x8c3 /* Use LSIG for VHT length */ 60 61 /* RF read/write-related */ 62 #define rHSSIRead_Jaguar 0x8b0 /* RF read addr */ 63 #define bHSSIRead_addr_Jaguar 0xff 64 #define bHSSIRead_trigger_Jaguar 0x100 65 #define rA_PIRead_Jaguar 0xd04 /* RF readback with PI */ 66 #define rB_PIRead_Jaguar 0xd44 /* RF readback with PI */ 67 #define rA_SIRead_Jaguar 0xd08 /* RF readback with SI */ 68 #define rB_SIRead_Jaguar 0xd48 /* RF readback with SI */ 69 #define rRead_data_Jaguar 0xfffff 70 #define rA_LSSIWrite_Jaguar 0xc90 /* RF write addr */ 71 #define rB_LSSIWrite_Jaguar 0xe90 /* RF write addr */ 72 #define bLSSIWrite_data_Jaguar 0x000fffff 73 #define bLSSIWrite_addr_Jaguar 0x0ff00000 74 75 76 77 /* YN: mask the following register definition temporarily */ 78 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 79 #define rFPGA0_XB_RFInterfaceOE 0x864 80 81 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ 82 #define rFPGA0_XCD_RFInterfaceSW 0x874 83 84 /* #define rFPGA0_XAB_RFParameter 0x878 */ /* RF Parameter 85 * #define rFPGA0_XCD_RFParameter 0x87c */ 86 87 /* #define rFPGA0_AnalogParameter1 0x880 */ /* Crystal cap setting RF-R/W protection for parameter4?? 88 * #define rFPGA0_AnalogParameter2 0x884 89 * #define rFPGA0_AnalogParameter3 0x888 90 * #define rFPGA0_AdDaClockEn 0x888 */ /* enable ad/da clock1 for dual-phy 91 * #define rFPGA0_AnalogParameter4 0x88c */ 92 93 94 /* CCK TX scaling */ 95 #define rCCK_TxFilter1_Jaguar 0xa20 96 #define bCCK_TxFilter1_C0_Jaguar 0x00ff0000 97 #define bCCK_TxFilter1_C1_Jaguar 0xff000000 98 #define rCCK_TxFilter2_Jaguar 0xa24 99 #define bCCK_TxFilter2_C2_Jaguar 0x000000ff 100 #define bCCK_TxFilter2_C3_Jaguar 0x0000ff00 101 #define bCCK_TxFilter2_C4_Jaguar 0x00ff0000 102 #define bCCK_TxFilter2_C5_Jaguar 0xff000000 103 #define rCCK_TxFilter3_Jaguar 0xa28 104 #define bCCK_TxFilter3_C6_Jaguar 0x000000ff 105 #define bCCK_TxFilter3_C7_Jaguar 0x0000ff00 106 107 108 /* YN: mask the following register definition temporarily 109 * #define rPdp_AntA 0xb00 110 * #define rPdp_AntA_4 0xb04 111 * #define rConfig_Pmpd_AntA 0xb28 112 * #define rConfig_AntA 0xb68 113 * #define rConfig_AntB 0xb6c 114 * #define rPdp_AntB 0xb70 115 * #define rPdp_AntB_4 0xb74 116 * #define rConfig_Pmpd_AntB 0xb98 117 * #define rAPK 0xbd8 */ 118 119 /* RXIQC */ 120 #define rA_RxIQC_AB_Jaguar 0xc10 /* RxIQ imblance matrix coeff. A & B */ 121 #define rA_RxIQC_CD_Jaguar 0xc14 /* RxIQ imblance matrix coeff. C & D */ 122 #define rA_TxScale_Jaguar 0xc1c /* Pah_A TX scaling factor */ 123 #define rB_TxScale_Jaguar 0xe1c /* Path_B TX scaling factor */ 124 #define rB_RxIQC_AB_Jaguar 0xe10 /* RxIQ imblance matrix coeff. A & B */ 125 #define rB_RxIQC_CD_Jaguar 0xe14 /* RxIQ imblance matrix coeff. C & D */ 126 #define b_RxIQC_AC_Jaguar 0x02ff /* bit mask for IQC matrix element A & C */ 127 #define b_RxIQC_BD_Jaguar 0x02ff0000 /* bit mask for IQC matrix element A & C */ 128 129 130 /* DIG-related */ 131 #define rA_IGI_Jaguar 0xc50 /* Initial Gain for path-A */ 132 #define rB_IGI_Jaguar 0xe50 /* Initial Gain for path-B */ 133 #define rOFDM_FalseAlarm1_Jaguar 0xf48 /* counter for break */ 134 #define rOFDM_FalseAlarm2_Jaguar 0xf4c /* counter for spoofing */ 135 #define rCCK_FalseAlarm_Jaguar 0xa5c /* counter for cck false alarm */ 136 #define b_FalseAlarm_Jaguar 0xffff 137 #define rCCK_CCA_Jaguar 0xa08 /* cca threshold */ 138 #define bCCK_CCA_Jaguar 0x00ff0000 139 140 /* Tx Power Ttraining-related */ 141 #define rA_TxPwrTraing_Jaguar 0xc54 142 #define rB_TxPwrTraing_Jaguar 0xe54 143 144 /* Report-related */ 145 #define rOFDM_ShortCFOAB_Jaguar 0xf60 146 #define rOFDM_LongCFOAB_Jaguar 0xf64 147 #define rOFDM_EndCFOAB_Jaguar 0xf70 148 #define rOFDM_AGCReport_Jaguar 0xf84 149 #define rOFDM_RxSNR_Jaguar 0xf88 150 #define rOFDM_RxEVMCSI_Jaguar 0xf8c 151 #define rOFDM_SIGReport_Jaguar 0xf90 152 153 /* Misc functions */ 154 #define rEDCCA_Jaguar 0x8a4 /* EDCCA */ 155 #define bEDCCA_Jaguar 0xffff 156 #define rAGC_table_Jaguar 0x82c /* AGC tabel select */ 157 #define bAGC_table_Jaguar 0x3 158 #define b_sel5g_Jaguar 0x1000 /* sel5g */ 159 #define b_LNA_sw_Jaguar 0x8000 /* HW/WS control for LNA */ 160 #define rFc_area_Jaguar 0x860 /* fc_area */ 161 #define bFc_area_Jaguar 0x1ffe000 162 #define rSingleTone_ContTx_Jaguar 0x914 163 164 /* RFE */ 165 #define rA_RFE_Pinmux_Jaguar 0xcb0 /* Path_A RFE cotrol pinmux */ 166 #define rB_RFE_Pinmux_Jaguar 0xeb0 /* Path_B RFE control pinmux */ 167 #define rA_RFE_Inv_Jaguar 0xcb4 /* Path_A RFE cotrol */ 168 #define rB_RFE_Inv_Jaguar 0xeb4 /* Path_B RFE control */ 169 #define rA_RFE_Jaguar 0xcb8 /* Path_A RFE cotrol */ 170 #define rB_RFE_Jaguar 0xeb8 /* Path_B RFE control */ 171 #define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */ 172 #define bMask_RFEInv_Jaguar 0x3ff00000 173 #define bMask_AntselPathFollow_Jaguar 0x00030000 174 175 /* TX AGC */ 176 #define rTxAGC_A_CCK11_CCK1_JAguar 0xc20 177 #define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24 178 #define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28 179 #define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c 180 #define rTxAGC_A_MCS7_MCS4_JAguar 0xc30 181 #define rTxAGC_A_MCS11_MCS8_JAguar 0xc34 182 #define rTxAGC_A_MCS15_MCS12_JAguar 0xc38 183 #define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c 184 #define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40 185 #define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44 186 #define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48 187 #define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c 188 #define rTxAGC_B_CCK11_CCK1_JAguar 0xe20 189 #define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24 190 #define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28 191 #define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c 192 #define rTxAGC_B_MCS7_MCS4_JAguar 0xe30 193 #define rTxAGC_B_MCS11_MCS8_JAguar 0xe34 194 #define rTxAGC_B_MCS15_MCS12_JAguar 0xe38 195 #define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c 196 #define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40 197 #define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44 198 #define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48 199 #define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c 200 #define bTxAGC_byte0_Jaguar 0xff 201 #define bTxAGC_byte1_Jaguar 0xff00 202 #define bTxAGC_byte2_Jaguar 0xff0000 203 #define bTxAGC_byte3_Jaguar 0xff000000 204 205 /* IQK YN: temporaily mask this part 206 * #define rFPGA0_IQK 0xe28 207 * #define rTx_IQK_Tone_A 0xe30 208 * #define rRx_IQK_Tone_A 0xe34 209 * #define rTx_IQK_PI_A 0xe38 210 * #define rRx_IQK_PI_A 0xe3c */ 211 212 /* #define rTx_IQK 0xe40 */ 213 /* #define rRx_IQK 0xe44 */ 214 /* #define rIQK_AGC_Pts 0xe48 */ 215 /* #define rIQK_AGC_Rsp 0xe4c */ 216 /* #define rTx_IQK_Tone_B 0xe50 */ 217 /* #define rRx_IQK_Tone_B 0xe54 */ 218 /* #define rTx_IQK_PI_B 0xe58 */ 219 /* #define rRx_IQK_PI_B 0xe5c */ 220 /* #define rIQK_AGC_Cont 0xe60 */ 221 222 223 /* AFE-related */ 224 #define rA_AFEPwr1_Jaguar 0xc60 /* dynamic AFE power control */ 225 #define rA_AFEPwr2_Jaguar 0xc64 /* dynamic AFE power control */ 226 #define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xc68 227 #define rA_Tx_CCKBBON_OFDMRFON_Jaguar 0xc6c 228 #define rA_Tx_OFDMBBON_Tx2Rx_Jaguar 0xc70 229 #define rA_Tx2Tx_RXCCK_Jaguar 0xc74 230 #define rA_Rx_OFDM_WaitRIFS_Jaguar 0xc78 231 #define rA_Rx2Rx_BT_Jaguar 0xc7c 232 #define rA_sleep_nav_Jaguar 0xc80 233 #define rA_pmpd_Jaguar 0xc84 234 #define rB_AFEPwr1_Jaguar 0xe60 /* dynamic AFE power control */ 235 #define rB_AFEPwr2_Jaguar 0xe64 /* dynamic AFE power control */ 236 #define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xe68 237 #define rB_Tx_CCKBBON_OFDMRFON_Jaguar 0xe6c 238 #define rB_Tx_OFDMBBON_Tx2Rx_Jaguar 0xe70 239 #define rB_Tx2Tx_RXCCK_Jaguar 0xe74 240 #define rB_Rx_OFDM_WaitRIFS_Jaguar 0xe78 241 #define rB_Rx2Rx_BT_Jaguar 0xe7c 242 #define rB_sleep_nav_Jaguar 0xe80 243 #define rB_pmpd_Jaguar 0xe84 244 245 246 /* YN: mask these registers temporaily 247 * #define rTx_Power_Before_IQK_A 0xe94 248 * #define rTx_Power_After_IQK_A 0xe9c */ 249 250 /* #define rRx_Power_Before_IQK_A 0xea0 */ 251 /* #define rRx_Power_Before_IQK_A_2 0xea4 */ 252 /* #define rRx_Power_After_IQK_A 0xea8 */ 253 /* #define rRx_Power_After_IQK_A_2 0xeac */ 254 255 /* #define rTx_Power_Before_IQK_B 0xeb4 */ 256 /* #define rTx_Power_After_IQK_B 0xebc */ 257 258 /* #define rRx_Power_Before_IQK_B 0xec0 */ 259 /* #define rRx_Power_Before_IQK_B_2 0xec4 */ 260 /* #define rRx_Power_After_IQK_B 0xec8 */ 261 /* #define rRx_Power_After_IQK_B_2 0xecc */ 262 263 264 /* RSSI Dump */ 265 #define rA_RSSIDump_Jaguar 0xBF0 266 #define rB_RSSIDump_Jaguar 0xBF1 267 #define rS1_RXevmDump_Jaguar 0xBF4 268 #define rS2_RXevmDump_Jaguar 0xBF5 269 #define rA_RXsnrDump_Jaguar 0xBF6 270 #define rB_RXsnrDump_Jaguar 0xBF7 271 #define rA_CfoShortDump_Jaguar 0xBF8 272 #define rB_CfoShortDump_Jaguar 0xBFA 273 #define rA_CfoLongDump_Jaguar 0xBEC 274 #define rB_CfoLongDump_Jaguar 0xBEE 275 276 277 /* RF Register 278 * */ 279 #define RF_AC_Jaguar 0x00 /* */ 280 #define RF_RF_Top_Jaguar 0x07 /* */ 281 #define RF_TXLOK_Jaguar 0x08 /* */ 282 #define RF_TXAPK_Jaguar 0x0B 283 #define RF_CHNLBW_Jaguar 0x18 /* RF channel and BW switch */ 284 #define RF_RCK1_Jaguar 0x1c /* */ 285 #define RF_RCK2_Jaguar 0x1d 286 #define RF_RCK3_Jaguar 0x1e 287 #define RF_ModeTableAddr 0x30 288 #define RF_ModeTableData0 0x31 289 #define RF_ModeTableData1 0x32 290 #define RF_TxLCTank_Jaguar 0x54 291 #define RF_APK_Jaguar 0x63 292 #define RF_LCK 0xB4 293 #define RF_WeLut_Jaguar 0xEF 294 295 #define bRF_CHNLBW_MOD_AG_Jaguar 0x70300 296 #define bRF_CHNLBW_BW 0xc00 297 298 299 /* 300 * RL6052 Register definition 301 * */ 302 #define RF_AC 0x00 /* */ 303 #define RF_IPA_A 0x0C /* */ 304 #define RF_TXBIAS_A 0x0D 305 #define RF_BS_PA_APSET_G9_G11 0x0E 306 #define RF_MODE1 0x10 /* */ 307 #define RF_MODE2 0x11 /* */ 308 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ 309 #define RF_RCK_OS 0x30 /* RF TX PA control */ 310 #define RF_TXPA_G1 0x31 /* RF TX PA control */ 311 #define RF_TXPA_G2 0x32 /* RF TX PA control */ 312 #define RF_TXPA_G3 0x33 /* RF TX PA control */ 313 #define RF_0x52 0x52 314 #define RF_WE_LUT 0xEF 315 316 #define RF_TX_GAIN_OFFSET_8812A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0)) 317 #define RF_TX_GAIN_OFFSET_8821A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0)) 318 319 /* 320 * Bit Mask 321 * 322 * 1. Page1(0x100) */ 323 #define bBBResetB 0x100 /* Useless now? */ 324 #define bGlobalResetB 0x200 325 #define bOFDMTxStart 0x4 326 #define bCCKTxStart 0x8 327 #define bCRC32Debug 0x100 328 #define bPMACLoopback 0x10 329 #define bTxLSIG 0xffffff 330 #define bOFDMTxRate 0xf 331 #define bOFDMTxReserved 0x10 332 #define bOFDMTxLength 0x1ffe0 333 #define bOFDMTxParity 0x20000 334 #define bTxHTSIG1 0xffffff 335 #define bTxHTMCSRate 0x7f 336 #define bTxHTBW 0x80 337 #define bTxHTLength 0xffff00 338 #define bTxHTSIG2 0xffffff 339 #define bTxHTSmoothing 0x1 340 #define bTxHTSounding 0x2 341 #define bTxHTReserved 0x4 342 #define bTxHTAggreation 0x8 343 #define bTxHTSTBC 0x30 344 #define bTxHTAdvanceCoding 0x40 345 #define bTxHTShortGI 0x80 346 #define bTxHTNumberHT_LTF 0x300 347 #define bTxHTCRC8 0x3fc00 348 #define bCounterReset 0x10000 349 #define bNumOfOFDMTx 0xffff 350 #define bNumOfCCKTx 0xffff0000 351 #define bTxIdleInterval 0xffff 352 #define bOFDMService 0xffff0000 353 #define bTxMACHeader 0xffffffff 354 #define bTxDataInit 0xff 355 #define bTxHTMode 0x100 356 #define bTxDataType 0x30000 357 #define bTxRandomSeed 0xffffffff 358 #define bCCKTxPreamble 0x1 359 #define bCCKTxSFD 0xffff0000 360 #define bCCKTxSIG 0xff 361 #define bCCKTxService 0xff00 362 #define bCCKLengthExt 0x8000 363 #define bCCKTxLength 0xffff0000 364 #define bCCKTxCRC16 0xffff 365 #define bCCKTxStatus 0x1 366 #define bOFDMTxStatus 0x2 367 368 369 /* 370 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 371 * 1. Page1(0x100) 372 * */ 373 #define rPMAC_Reset 0x100 374 #define rPMAC_TxStart 0x104 375 #define rPMAC_TxLegacySIG 0x108 376 #define rPMAC_TxHTSIG1 0x10c 377 #define rPMAC_TxHTSIG2 0x110 378 #define rPMAC_PHYDebug 0x114 379 #define rPMAC_TxPacketNum 0x118 380 #define rPMAC_TxIdle 0x11c 381 #define rPMAC_TxMACHeader0 0x120 382 #define rPMAC_TxMACHeader1 0x124 383 #define rPMAC_TxMACHeader2 0x128 384 #define rPMAC_TxMACHeader3 0x12c 385 #define rPMAC_TxMACHeader4 0x130 386 #define rPMAC_TxMACHeader5 0x134 387 #define rPMAC_TxDataType 0x138 388 #define rPMAC_TxRandomSeed 0x13c 389 #define rPMAC_CCKPLCPPreamble 0x140 390 #define rPMAC_CCKPLCPHeader 0x144 391 #define rPMAC_CCKCRC16 0x148 392 #define rPMAC_OFDMRxCRC32OK 0x170 393 #define rPMAC_OFDMRxCRC32Er 0x174 394 #define rPMAC_OFDMRxParityEr 0x178 395 #define rPMAC_OFDMRxCRC8Er 0x17c 396 #define rPMAC_CCKCRxRC16Er 0x180 397 #define rPMAC_CCKCRxRC32Er 0x184 398 #define rPMAC_CCKCRxRC32OK 0x188 399 #define rPMAC_TxStatus 0x18c 400 401 /* 402 * 3. Page8(0x800) 403 * */ 404 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */ 405 406 #define rFPGA0_TxInfo 0x804 /* Status report?? */ 407 #define rFPGA0_PSDFunction 0x808 408 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 409 410 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 411 #define rFPGA0_XA_HSSIParameter2 0x824 412 #define rFPGA0_XB_HSSIParameter1 0x828 413 #define rFPGA0_XB_HSSIParameter2 0x82c 414 415 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 416 #define rFPGA0_XCD_SwitchControl 0x85c 417 418 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 419 #define rFPGA0_XCD_RFParameter 0x87c 420 421 #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ 422 #define rFPGA0_AnalogParameter2 0x884 423 #define rFPGA0_AnalogParameter3 0x888 424 #define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */ 425 #define rFPGA0_AnalogParameter4 0x88c 426 #define rFPGA0_XB_LSSIReadBack 0x8a4 427 #define rFPGA0_XCD_RFPara 0x8b4 428 429 /* 430 * 4. Page9(0x900) 431 * */ 432 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */ 433 434 #define rFPGA1_TxBlock 0x904 /* Useless now */ 435 #define rFPGA1_DebugSelect 0x908 /* Useless now */ 436 #define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */ 437 438 /* 439 * PageA(0xA00) 440 * */ 441 #define rCCK0_System 0xa00 442 #define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */ 443 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 444 #define rCCK0_TxFilter1 0xa20 445 #define rCCK0_TxFilter2 0xa24 446 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 447 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ 448 449 /* 450 * PageB(0xB00) 451 * */ 452 #define rPdp_AntA 0xb00 453 #define rPdp_AntA_4 0xb04 454 #define rConfig_Pmpd_AntA 0xb28 455 #define rConfig_AntA 0xb68 456 #define rConfig_AntB 0xb6c 457 #define rPdp_AntB 0xb70 458 #define rPdp_AntB_4 0xb74 459 #define rConfig_Pmpd_AntB 0xb98 460 #define rAPK 0xbd8 461 462 /* 463 * 6. PageC(0xC00) 464 * */ 465 #define rOFDM0_LSTF 0xc00 466 467 #define rOFDM0_TRxPathEnable 0xc04 468 #define rOFDM0_TRMuxPar 0xc08 469 #define rOFDM0_TRSWIsolation 0xc0c 470 471 #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 472 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ 473 #define rOFDM0_XBRxAFE 0xc18 474 #define rOFDM0_XBRxIQImbalance 0xc1c 475 #define rOFDM0_XCRxAFE 0xc20 476 #define rOFDM0_XCRxIQImbalance 0xc24 477 #define rOFDM0_XDRxAFE 0xc28 478 #define rOFDM0_XDRxIQImbalance 0xc2c 479 480 #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */ 481 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 482 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 483 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 484 485 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 486 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 487 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 488 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 489 490 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 491 #define rOFDM0_XAAGCCore2 0xc54 492 #define rOFDM0_XBAGCCore1 0xc58 493 #define rOFDM0_XBAGCCore2 0xc5c 494 #define rOFDM0_XCAGCCore1 0xc60 495 #define rOFDM0_XCAGCCore2 0xc64 496 #define rOFDM0_XDAGCCore1 0xc68 497 #define rOFDM0_XDAGCCore2 0xc6c 498 499 #define rOFDM0_AGCParameter1 0xc70 500 #define rOFDM0_AGCParameter2 0xc74 501 #define rOFDM0_AGCRSSITable 0xc78 502 #define rOFDM0_HTSTFAGC 0xc7c 503 504 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 505 #define rOFDM0_XATxAFE 0xc84 506 #define rOFDM0_XBTxIQImbalance 0xc88 507 #define rOFDM0_XBTxAFE 0xc8c 508 #define rOFDM0_XCTxIQImbalance 0xc90 509 #define rOFDM0_XCTxAFE 0xc94 510 #define rOFDM0_XDTxIQImbalance 0xc98 511 #define rOFDM0_XDTxAFE 0xc9c 512 513 #define rOFDM0_RxIQExtAnta 0xca0 514 #define rOFDM0_TxCoeff1 0xca4 515 #define rOFDM0_TxCoeff2 0xca8 516 #define rOFDM0_TxCoeff3 0xcac 517 #define rOFDM0_TxCoeff4 0xcb0 518 #define rOFDM0_TxCoeff5 0xcb4 519 #define rOFDM0_TxCoeff6 0xcb8 520 #define rOFDM0_RxHPParameter 0xce0 521 #define rOFDM0_TxPseudoNoiseWgt 0xce4 522 #define rOFDM0_FrameSync 0xcf0 523 #define rOFDM0_DFSReport 0xcf4 524 525 /* 526 * 7. PageD(0xD00) 527 * */ 528 #define rOFDM1_LSTF 0xd00 529 #define rOFDM1_TRxPathEnable 0xd04 530 531 /* 532 * 8. PageE(0xE00) 533 * */ 534 #define rTxAGC_A_Rate18_06 0xe00 535 #define rTxAGC_A_Rate54_24 0xe04 536 #define rTxAGC_A_CCK1_Mcs32 0xe08 537 #define rTxAGC_A_Mcs03_Mcs00 0xe10 538 #define rTxAGC_A_Mcs07_Mcs04 0xe14 539 #define rTxAGC_A_Mcs11_Mcs08 0xe18 540 #define rTxAGC_A_Mcs15_Mcs12 0xe1c 541 542 #define rTxAGC_B_Rate18_06 0x830 543 #define rTxAGC_B_Rate54_24 0x834 544 #define rTxAGC_B_CCK1_55_Mcs32 0x838 545 #define rTxAGC_B_Mcs03_Mcs00 0x83c 546 #define rTxAGC_B_Mcs07_Mcs04 0x848 547 #define rTxAGC_B_Mcs11_Mcs08 0x84c 548 #define rTxAGC_B_Mcs15_Mcs12 0x868 549 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c 550 551 #define rFPGA0_IQK 0xe28 552 #define rTx_IQK_Tone_A 0xe30 553 #define rRx_IQK_Tone_A 0xe34 554 #define rTx_IQK_PI_A 0xe38 555 #define rRx_IQK_PI_A 0xe3c 556 557 #define rTx_IQK 0xe40 558 #define rRx_IQK 0xe44 559 #define rIQK_AGC_Pts 0xe48 560 #define rIQK_AGC_Rsp 0xe4c 561 #define rTx_IQK_Tone_B 0xe50 562 #define rRx_IQK_Tone_B 0xe54 563 #define rTx_IQK_PI_B 0xe58 564 #define rRx_IQK_PI_B 0xe5c 565 #define rIQK_AGC_Cont 0xe60 566 567 #define rBlue_Tooth 0xe6c 568 #define rRx_Wait_CCA 0xe70 569 #define rTx_CCK_RFON 0xe74 570 #define rTx_CCK_BBON 0xe78 571 #define rTx_OFDM_RFON 0xe7c 572 #define rTx_OFDM_BBON 0xe80 573 #define rTx_To_Rx 0xe84 574 #define rTx_To_Tx 0xe88 575 #define rRx_CCK 0xe8c 576 577 #define rTx_Power_Before_IQK_A 0xe94 578 #define rTx_Power_After_IQK_A 0xe9c 579 580 #define rRx_Power_Before_IQK_A 0xea0 581 #define rRx_Power_Before_IQK_A_2 0xea4 582 #define rRx_Power_After_IQK_A 0xea8 583 #define rRx_Power_After_IQK_A_2 0xeac 584 585 #define rTx_Power_Before_IQK_B 0xeb4 586 #define rTx_Power_After_IQK_B 0xebc 587 588 #define rRx_Power_Before_IQK_B 0xec0 589 #define rRx_Power_Before_IQK_B_2 0xec4 590 #define rRx_Power_After_IQK_B 0xec8 591 #define rRx_Power_After_IQK_B_2 0xecc 592 593 #define rRx_OFDM 0xed0 594 #define rRx_Wait_RIFS 0xed4 595 #define rRx_TO_Rx 0xed8 596 #define rStandby 0xedc 597 #define rSleep 0xee0 598 #define rPMPD_ANAEN 0xeec 599 600 601 /* 2. Page8(0x800) */ 602 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 603 #define bJapanMode 0x2 604 #define bCCKTxSC 0x30 605 #define bCCKEn 0x1000000 606 #define bOFDMEn 0x2000000 607 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 608 #define bXCTxAGC 0xf000 609 #define bXDTxAGC 0xf0000 610 611 /* 4. PageA(0xA00) */ 612 #define bCCKBBMode 0x3 /* Useless */ 613 #define bCCKTxPowerSaving 0x80 614 #define bCCKRxPowerSaving 0x40 615 616 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ 617 618 #define bCCKScramble 0x8 /* Useless */ 619 #define bCCKAntDiversity 0x8000 620 #define bCCKCarrierRecovery 0x4000 621 #define bCCKTxRate 0x3000 622 #define bCCKDCCancel 0x0800 623 #define bCCKISICancel 0x0400 624 #define bCCKMatchFilter 0x0200 625 #define bCCKEqualizer 0x0100 626 #define bCCKPreambleDetect 0x800000 627 #define bCCKFastFalseCCA 0x400000 628 #define bCCKChEstStart 0x300000 629 #define bCCKCCACount 0x080000 630 #define bCCKcs_lim 0x070000 631 #define bCCKBistMode 0x80000000 632 #define bCCKCCAMask 0x40000000 633 #define bCCKTxDACPhase 0x4 634 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 635 #define bCCKr_cp_mode0 0x0100 636 #define bCCKTxDCOffset 0xf0 637 #define bCCKRxDCOffset 0xf 638 #define bCCKCCAMode 0xc000 639 #define bCCKFalseCS_lim 0x3f00 640 #define bCCKCS_ratio 0xc00000 641 #define bCCKCorgBit_sel 0x300000 642 #define bCCKPD_lim 0x0f0000 643 #define bCCKNewCCA 0x80000000 644 #define bCCKRxHPofIG 0x8000 645 #define bCCKRxIG 0x7f00 646 #define bCCKLNAPolarity 0x800000 647 #define bCCKRx1stGain 0x7f0000 648 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 649 #define bCCKRxAGCSatLevel 0x1f000000 650 #define bCCKRxAGCSatCount 0xe0 651 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 652 #define bCCKFixedRxAGC 0x8000 653 /* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ 654 #define bCCKAntennaPolarity 0x2000 655 #define bCCKTxFilterType 0x0c00 656 #define bCCKRxAGCReportType 0x0300 657 #define bCCKRxDAGCEn 0x80000000 658 #define bCCKRxDAGCPeriod 0x20000000 659 #define bCCKRxDAGCSatLevel 0x1f000000 660 #define bCCKTimingRecovery 0x800000 661 #define bCCKTxC0 0x3f0000 662 #define bCCKTxC1 0x3f000000 663 #define bCCKTxC2 0x3f 664 #define bCCKTxC3 0x3f00 665 #define bCCKTxC4 0x3f0000 666 #define bCCKTxC5 0x3f000000 667 #define bCCKTxC6 0x3f 668 #define bCCKTxC7 0x3f00 669 #define bCCKDebugPort 0xff0000 670 #define bCCKDACDebug 0x0f000000 671 #define bCCKFalseAlarmEnable 0x8000 672 #define bCCKFalseAlarmRead 0x4000 673 #define bCCKTRSSI 0x7f 674 #define bCCKRxAGCReport 0xfe 675 #define bCCKRxReport_AntSel 0x80000000 676 #define bCCKRxReport_MFOff 0x40000000 677 #define bCCKRxRxReport_SQLoss 0x20000000 678 #define bCCKRxReport_Pktloss 0x10000000 679 #define bCCKRxReport_Lockedbit 0x08000000 680 #define bCCKRxReport_RateError 0x04000000 681 #define bCCKRxReport_RxRate 0x03000000 682 #define bCCKRxFACounterLower 0xff 683 #define bCCKRxFACounterUpper 0xff000000 684 #define bCCKRxHPAGCStart 0xe000 685 #define bCCKRxHPAGCFinal 0x1c00 686 #define bCCKRxFalseAlarmEnable 0x8000 687 #define bCCKFACounterFreeze 0x4000 688 #define bCCKTxPathSel 0x10000000 689 #define bCCKDefaultRxPath 0xc000000 690 #define bCCKOptionRxPath 0x3000000 691 692 /* 6. PageE(0xE00) */ 693 #define bSTBCEn 0x4 /* Useless */ 694 #define bAntennaMapping 0x10 695 #define bNss 0x20 696 #define bCFOAntSumD 0x200 697 #define bPHYCounterReset 0x8000000 698 #define bCFOReportGet 0x4000000 699 #define bOFDMContinueTx 0x10000000 700 #define bOFDMSingleCarrier 0x20000000 701 #define bOFDMSingleTone 0x40000000 702 703 704 /* 705 * Other Definition 706 * */ 707 708 #define bEnable 0x1 /* Useless */ 709 #define bDisable 0x0 710 711 /* byte endable for srwrite */ 712 #define bByte0 0x1 /* Useless */ 713 #define bByte1 0x2 714 #define bByte2 0x4 715 #define bByte3 0x8 716 #define bWord0 0x3 717 #define bWord1 0xc 718 #define bDWord 0xf 719 720 /* for PutRegsetting & GetRegSetting BitMask */ 721 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 722 #define bMaskByte1 0xff00 723 #define bMaskByte2 0xff0000 724 #define bMaskByte3 0xff000000 725 #define bMaskHWord 0xffff0000 726 #define bMaskLWord 0x0000ffff 727 #define bMaskDWord 0xffffffff 728 #define bMaskH3Bytes 0xffffff00 729 #define bMask12Bits 0xfff 730 #define bMaskH4Bits 0xf0000000 731 #define bMaskOFDM_D 0xffc00000 732 #define bMaskCCK 0x3f3f3f3f 733 734 735 /*--------------------------Define Parameters-------------------------------*/ 736 737 738 #endif 739