1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20 #define _HAL_MP_C_
21
22 #include <drv_types.h>
23
24 #ifdef CONFIG_MP_INCLUDED
25
26 #ifdef RTW_HALMAC
27 #include <hal_data.h> /* struct HAL_DATA_TYPE, RF register definition and etc. */
28 #else /* !RTW_HALMAC */
29 #ifdef CONFIG_RTL8188E
30 #include <rtl8188e_hal.h>
31 #endif
32 #ifdef CONFIG_RTL8723B
33 #include <rtl8723b_hal.h>
34 #endif
35 #ifdef CONFIG_RTL8192E
36 #include <rtl8192e_hal.h>
37 #endif
38 #ifdef CONFIG_RTL8814A
39 #include <rtl8814a_hal.h>
40 #endif
41 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
42 #include <rtl8812a_hal.h>
43 #endif
44 #ifdef CONFIG_RTL8703B
45 #include <rtl8703b_hal.h>
46 #endif
47 #ifdef CONFIG_RTL8723D
48 #include <rtl8723d_hal.h>
49 #endif
50 #ifdef CONFIG_RTL8188F
51 #include <rtl8188f_hal.h>
52 #endif
53 #endif /* !RTW_HALMAC */
54
55
MgntQuery_NssTxRate(u16 Rate)56 u8 MgntQuery_NssTxRate(u16 Rate)
57 {
58 u8 NssNum = RF_TX_NUM_NONIMPLEMENT;
59
60 if ((Rate >= MGN_MCS8 && Rate <= MGN_MCS15) ||
61 (Rate >= MGN_VHT2SS_MCS0 && Rate <= MGN_VHT2SS_MCS9))
62 NssNum = RF_2TX;
63 else if ((Rate >= MGN_MCS16 && Rate <= MGN_MCS23) ||
64 (Rate >= MGN_VHT3SS_MCS0 && Rate <= MGN_VHT3SS_MCS9))
65 NssNum = RF_3TX;
66 else if ((Rate >= MGN_MCS24 && Rate <= MGN_MCS31) ||
67 (Rate >= MGN_VHT4SS_MCS0 && Rate <= MGN_VHT4SS_MCS9))
68 NssNum = RF_4TX;
69 else
70 NssNum = RF_1TX;
71
72 return NssNum;
73 }
74
hal_mpt_SwitchRfSetting(PADAPTER pAdapter)75 void hal_mpt_SwitchRfSetting(PADAPTER pAdapter)
76 {
77 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
78 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
79 u8 ChannelToSw = pMptCtx->MptChannelToSw;
80 ULONG ulRateIdx = pMptCtx->MptRateIndex;
81 ULONG ulbandwidth = pMptCtx->MptBandWidth;
82
83 /* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/
84 if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) &&
85 (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) {
86 pMptCtx->backup0x52_RF_A = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0);
87 pMptCtx->backup0x52_RF_B = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0);
88
89 if ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) {
90 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB);
91 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB);
92 } else {
93 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xD);
94 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xD);
95 }
96 } else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/
97 if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) {
98 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
99 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
100 } else {
101 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
102 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
103 }
104 } else if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
105 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A);
106 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B);
107 }
108 }
109
hal_mpt_SetPowerTracking(PADAPTER padapter,u8 enable)110 s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable)
111 {
112 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
113 PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
114
115
116 if (!netif_running(padapter->pnetdev)) {
117 RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: interface not opened!\n"));
118 return _FAIL;
119 }
120
121 if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
122 RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: not in MP mode!\n"));
123 return _FAIL;
124 }
125 if (enable)
126 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE;
127 else
128 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _FALSE;
129
130 return _SUCCESS;
131 }
132
hal_mpt_GetPowerTracking(PADAPTER padapter,u8 * enable)133 void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable)
134 {
135 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
136 PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
137
138
139 *enable = pDM_Odm->RFCalibrateInfo.TxPowerTrackControl;
140 }
141
142
hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter,BOOLEAN bInCH14)143 void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
144 {
145 u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0;
146 u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12;
147 u8 i;
148 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
149 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);
150 u1Byte u1Channel = pHalData->CurrentChannel;
151 ULONG ulRateIdx = pMptCtx->MptRateIndex;
152 u1Byte DataRate = 0xFF;
153
154 /* Suggested by BB David. 2015.04.27*/
155 if(IS_HARDWARE_TYPE_8188F(Adapter))
156 return;
157
158 /* Do not modify CCK TX filter parameters for 8822B*/
159 if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) || IS_HARDWARE_TYPE_8723D(Adapter))
160 return;
161
162 DataRate = MptToMgntRate(ulRateIdx);
163
164 if (u1Channel == 14 && IS_CCK_RATE(DataRate))
165 pHalData->bCCKinCH14 = TRUE;
166 else
167 pHalData->bCCKinCH14 = FALSE;
168
169 if (IS_HARDWARE_TYPE_8703B(Adapter)) {
170 if ((u1Channel == 14) && IS_CCK_RATE(DataRate)) {
171 /* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */
172 PHY_SetBBReg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0);
173 PHY_SetBBReg(Adapter, rCCK0_DebugPort, bMaskLWord, 0);
174
175 RT_TRACE(_module_mp_, DBG_LOUD, ("MPT_CCKTxPowerAdjust 8703B CCK in Channel %u\n", u1Channel));
176 } else {
177 /* Normal setting for 8703B, just recover to the default setting. */
178 /* This hardcore values reference from the parameter which BB team gave. */
179 for (i = 0 ; i < 2 ; ++i)
180 PHY_SetBBReg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);
181
182 RT_TRACE(_module_mp_, DBG_LOUD, ("MPT_CCKTxPowerAdjust 8703B in Channel %u restore to default setting\n", u1Channel));
183 }
184 } else if (IS_HARDWARE_TYPE_8723D(Adapter)) {
185 /* 2.4G CCK TX DFIR */
186 /* 2016.01.20 Suggest from RS BB mingzhi*/
187 if ((u1Channel == 14)) {
188 PHY_SetBBReg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C);
189 PHY_SetBBReg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000000);
190 PHY_SetBBReg(Adapter, 0xAAC, bMaskDWord, 0x00003667);
191 } else {
192 for (i = 0 ; i < 3 ; ++i) {
193 PHY_SetBBReg(Adapter,
194 pHalData->RegForRecover[i].offset,
195 bMaskDWord,
196 pHalData->RegForRecover[i].value);
197 }
198 }
199 } else {
200
201 /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
202 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
203
204 if (!pHalData->bCCKinCH14) {
205 /* Readback the current bb cck swing value and compare with the table to */
206 /* get the current swing index */
207 for (i = 0; i < CCK_TABLE_SIZE; i++) {
208 if (((CurrCCKSwingVal & 0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) &&
209 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)CCKSwingTable_Ch1_Ch13[i][1])) {
210 CCKSwingIndex = i;
211 RT_TRACE(_module_mp_, DBG_LOUD, ("Ch1~13, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",
212 (rCCK0_TxFilter1 + 2), CurrCCKSwingVal, CCKSwingIndex));
213 break;
214 }
215 }
216
217 /*Write 0xa22 0xa23*/
218 TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] +
219 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1] << 8);
220
221
222 /*Write 0xa24 ~ 0xa27*/
223 TempVal2 = 0;
224 TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] +
225 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3] << 8) +
226 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4] << 16) +
227 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5] << 24);
228
229 /*Write 0xa28 0xa29*/
230 TempVal3 = 0;
231 TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] +
232 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7] << 8);
233 } else {
234 for (i = 0; i < CCK_TABLE_SIZE; i++) {
235 if (((CurrCCKSwingVal & 0xff) == (u32)CCKSwingTable_Ch14[i][0]) &&
236 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)CCKSwingTable_Ch14[i][1])) {
237 CCKSwingIndex = i;
238 RT_TRACE(_module_mp_, DBG_LOUD, ("Ch14, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",
239 (rCCK0_TxFilter1 + 2), CurrCCKSwingVal, CCKSwingIndex));
240 break;
241 }
242 }
243
244 /*Write 0xa22 0xa23*/
245 TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] +
246 (CCKSwingTable_Ch14[CCKSwingIndex][1] << 8);
247
248 /*Write 0xa24 ~ 0xa27*/
249 TempVal2 = 0;
250 TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] +
251 (CCKSwingTable_Ch14[CCKSwingIndex][3] << 8) +
252 (CCKSwingTable_Ch14[CCKSwingIndex][4] << 16) +
253 (CCKSwingTable_Ch14[CCKSwingIndex][5] << 24);
254
255 /*Write 0xa28 0xa29*/
256 TempVal3 = 0;
257 TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] +
258 (CCKSwingTable_Ch14[CCKSwingIndex][7] << 8);
259 }
260
261 write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
262 write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
263 write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
264 }
265
266 }
267
hal_mpt_SetChannel(PADAPTER pAdapter)268 void hal_mpt_SetChannel(PADAPTER pAdapter)
269 {
270 u8 eRFPath;
271 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
272 PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
273 struct mp_priv *pmp = &pAdapter->mppriv;
274 u8 channel = pmp->channel;
275 u8 bandwidth = pmp->bandwidth;
276
277 hal_mpt_SwitchRfSetting(pAdapter);
278
279 SelectChannel(pAdapter, channel);
280
281 pHalData->bSwChnl = _TRUE;
282 pHalData->bSetChnlBW = _TRUE;
283 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);
284
285 hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
286
287 }
288
289 /*
290 * Notice
291 * Switch bandwitdth may change center frequency(channel)
292 */
hal_mpt_SetBandwidth(PADAPTER pAdapter)293 void hal_mpt_SetBandwidth(PADAPTER pAdapter)
294 {
295 struct mp_priv *pmp = &pAdapter->mppriv;
296 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
297
298 u8 channel = pmp->channel;
299 u8 bandwidth = pmp->bandwidth;
300
301 SetBWMode(pAdapter, pmp->bandwidth, pmp->prime_channel_offset);
302 pHalData->bSwChnl = _TRUE;
303 pHalData->bSetChnlBW = _TRUE;
304 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);
305
306 hal_mpt_SwitchRfSetting(pAdapter);
307 }
308
mpt_SetTxPower_Old(PADAPTER pAdapter,MPT_TXPWR_DEF Rate,u8 * pTxPower)309 void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)
310 {
311 RT_TRACE(_module_mp_, DBG_LOUD, ("===>mpt_SetTxPower_Old(): Case = %d\n", Rate));
312 switch (Rate) {
313 case MPT_CCK: {
314 u4Byte TxAGC = 0, pwr = 0;
315 u1Byte rf;
316
317 pwr = pTxPower[ODM_RF_PATH_A];
318 if (pwr < 0x3f) {
319 TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
320 PHY_SetBBReg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[ODM_RF_PATH_A]);
321 PHY_SetBBReg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC);
322 }
323 pwr = pTxPower[ODM_RF_PATH_B];
324 if (pwr < 0x3f) {
325 TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
326 PHY_SetBBReg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[ODM_RF_PATH_B]);
327 PHY_SetBBReg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC);
328 }
329 }
330 break;
331
332 case MPT_OFDM_AND_HT: {
333 u4Byte TxAGC = 0;
334 u1Byte pwr = 0, rf;
335
336 pwr = pTxPower[0];
337 if (pwr < 0x3f) {
338 TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
339 RTW_INFO("HT Tx-rf(A) Power = 0x%x\n", TxAGC);
340 PHY_SetBBReg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
341 PHY_SetBBReg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
342 PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
343 PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
344 PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
345 PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
346 }
347 TxAGC = 0;
348 pwr = pTxPower[1];
349 if (pwr < 0x3f) {
350 TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
351 RTW_INFO("HT Tx-rf(B) Power = 0x%x\n", TxAGC);
352 PHY_SetBBReg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
353 PHY_SetBBReg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
354 PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
355 PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
356 PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
357 PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
358 }
359 }
360 break;
361
362 default:
363 break;
364 }
365 RTW_INFO("<===mpt_SetTxPower_Old()\n");
366 }
367
368 void
mpt_SetTxPower(PADAPTER pAdapter,MPT_TXPWR_DEF Rate,pu1Byte pTxPower)369 mpt_SetTxPower(
370 PADAPTER pAdapter,
371 MPT_TXPWR_DEF Rate,
372 pu1Byte pTxPower
373 )
374 {
375 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
376
377 u1Byte path = 0 , i = 0, MaxRate = MGN_6M;
378 u1Byte StartPath = ODM_RF_PATH_A, EndPath = ODM_RF_PATH_B;
379
380 if (IS_HARDWARE_TYPE_8814A(pAdapter))
381 EndPath = ODM_RF_PATH_D;
382 else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter))
383 EndPath = ODM_RF_PATH_A;
384
385 switch (Rate) {
386 case MPT_CCK: {
387 u1Byte rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
388
389 for (path = StartPath; path <= EndPath; path++)
390 for (i = 0; i < sizeof(rate); ++i)
391 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
392 }
393 break;
394 case MPT_OFDM: {
395 u1Byte rate[] = {
396 MGN_6M, MGN_9M, MGN_12M, MGN_18M,
397 MGN_24M, MGN_36M, MGN_48M, MGN_54M,
398 };
399
400 for (path = StartPath; path <= EndPath; path++)
401 for (i = 0; i < sizeof(rate); ++i)
402 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
403 }
404 break;
405 case MPT_HT: {
406 u1Byte rate[] = {
407 MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4,
408 MGN_MCS5, MGN_MCS6, MGN_MCS7, MGN_MCS8, MGN_MCS9,
409 MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14,
410 MGN_MCS15, MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19,
411 MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23, MGN_MCS24,
412 MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29,
413 MGN_MCS30, MGN_MCS31,
414 };
415 if (pHalData->rf_type == RF_3T3R)
416 MaxRate = MGN_MCS23;
417 else if (pHalData->rf_type == RF_2T2R)
418 MaxRate = MGN_MCS15;
419 else
420 MaxRate = MGN_MCS7;
421 for (path = StartPath; path <= EndPath; path++) {
422 for (i = 0; i < sizeof(rate); ++i) {
423 if (rate[i] > MaxRate)
424 break;
425 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
426 }
427 }
428 }
429 break;
430 case MPT_VHT: {
431 u1Byte rate[] = {
432 MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
433 MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9,
434 MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
435 MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9,
436 MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
437 MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9,
438 MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4,
439 MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9,
440 };
441 if (pHalData->rf_type == RF_3T3R)
442 MaxRate = MGN_VHT3SS_MCS9;
443 else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
444 MaxRate = MGN_VHT2SS_MCS9;
445 else
446 MaxRate = MGN_VHT1SS_MCS9;
447
448 for (path = StartPath; path <= EndPath; path++) {
449 for (i = 0; i < sizeof(rate); ++i) {
450 if (rate[i] > MaxRate)
451 break;
452 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
453 }
454 }
455 }
456 break;
457 default:
458 RTW_INFO("<===mpt_SetTxPower: Illegal channel!!\n");
459 break;
460 }
461 }
462
hal_mpt_SetTxPower(PADAPTER pAdapter)463 void hal_mpt_SetTxPower(PADAPTER pAdapter)
464 {
465 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
466 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
467 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
468
469 if (pHalData->rf_chip < RF_TYPE_MAX) {
470 if (IS_HARDWARE_TYPE_8188E(pAdapter) ||
471 IS_HARDWARE_TYPE_8723B(pAdapter) ||
472 IS_HARDWARE_TYPE_8192E(pAdapter) ||
473 IS_HARDWARE_TYPE_8703B(pAdapter) ||
474 IS_HARDWARE_TYPE_8188F(pAdapter)) {
475 u8 path = (pHalData->AntennaTxPath == ANTENNA_A) ? (ODM_RF_PATH_A) : (ODM_RF_PATH_B);
476
477 RTW_INFO("===> MPT_ProSetTxPower: Old\n");
478
479 RT_TRACE(_module_mp_, DBG_LOUD, ("===> MPT_ProSetTxPower[Old]:\n"));
480 mpt_SetTxPower_Old(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
481 mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel);
482
483 } else {
484 RTW_INFO("===> MPT_ProSetTxPower: Jaguar/Jaguar2\n");
485 mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
486 mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);
487 mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel);
488 mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel);
489
490 }
491 } else
492 RTW_INFO("RFChipID < RF_TYPE_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);
493
494 ODM_ClearTxPowerTrackingState(pDM_Odm);
495 }
496
hal_mpt_SetDataRate(PADAPTER pAdapter)497 void hal_mpt_SetDataRate(PADAPTER pAdapter)
498 {
499 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
500 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
501 u32 DataRate;
502
503 DataRate = MptToMgntRate(pMptCtx->MptRateIndex);
504
505 hal_mpt_SwitchRfSetting(pAdapter);
506
507 hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
508 #ifdef CONFIG_RTL8723B
509 if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter)) {
510 if (IS_CCK_RATE(DataRate)) {
511 if (pMptCtx->MptRfPath == ODM_RF_PATH_A)
512 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0x6);
513 else
514 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0x6);
515 } else {
516 if (pMptCtx->MptRfPath == ODM_RF_PATH_A)
517 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE);
518 else
519 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE);
520 }
521 }
522
523 if ((IS_HARDWARE_TYPE_8723BS(pAdapter) &&
524 ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) {
525 if (pMptCtx->MptRfPath == ODM_RF_PATH_A)
526 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE);
527 else
528 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE);
529 }
530 #endif
531 }
532
533 #define RF_PATH_AB 22
534
535 #ifdef CONFIG_RTL8814A
mpt_ToggleIG_8814A(PADAPTER pAdapter)536 VOID mpt_ToggleIG_8814A(PADAPTER pAdapter)
537 {
538 u1Byte Path = 0;
539 u4Byte IGReg = rA_IGI_Jaguar, IGvalue = 0;
540
541 for (Path; Path <= ODM_RF_PATH_D; Path++) {
542 switch (Path) {
543 case ODM_RF_PATH_B:
544 IGReg = rB_IGI_Jaguar;
545 break;
546 case ODM_RF_PATH_C:
547 IGReg = rC_IGI_Jaguar2;
548 break;
549 case ODM_RF_PATH_D:
550 IGReg = rD_IGI_Jaguar2;
551 break;
552 default:
553 IGReg = rA_IGI_Jaguar;
554 break;
555 }
556
557 IGvalue = PHY_QueryBBReg(pAdapter, IGReg, bMaskByte0);
558 PHY_SetBBReg(pAdapter, IGReg, bMaskByte0, IGvalue + 2);
559 PHY_SetBBReg(pAdapter, IGReg, bMaskByte0, IGvalue);
560 }
561 }
562
mpt_SetRFPath_8814A(PADAPTER pAdapter)563 VOID mpt_SetRFPath_8814A(PADAPTER pAdapter)
564 {
565
566 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
567 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
568 R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
569 R_ANTENNA_SELECT_CCK *p_cck_txrx;
570 u8 ForcedDataRate = MptToMgntRate(pMptCtx->MptRateIndex);
571 u8 HtStbcCap = pAdapter->registrypriv.stbc_cap;
572 /*/PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo);*/
573 /*/PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pMgntInfo);*/
574
575 u32 ulAntennaTx = pHalData->AntennaTxPath;
576 u32 ulAntennaRx = pHalData->AntennaRxPath;
577 u8 NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
578
579 if ((NssforRate == RF_2TX) || ((NssforRate == RF_1TX) && IS_HT_RATE(ForcedDataRate)) || ((NssforRate == RF_1TX) && IS_VHT_RATE(ForcedDataRate))) {
580 RTW_INFO("===> SetAntenna 2T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
581
582 switch (ulAntennaTx) {
583 case ANTENNA_BC:
584 pMptCtx->MptRfPath = ODM_RF_PATH_BC;
585 /*pHalData->ValidTxPath = 0x06; linux no use */
586 PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x106); /*/ 0x940[15:4]=12'b0000_0100_0011*/
587 break;
588
589 case ANTENNA_CD:
590 pMptCtx->MptRfPath = ODM_RF_PATH_CD;
591 /*pHalData->ValidTxPath = 0x0C;*/
592 PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x40c); /*/ 0x940[15:4]=12'b0000_0100_0011*/
593 break;
594 case ANTENNA_AB:
595 default:
596 pMptCtx->MptRfPath = ODM_RF_PATH_AB;
597 /*pHalData->ValidTxPath = 0x03;*/
598 PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x043); /*/ 0x940[15:4]=12'b0000_0100_0011*/
599 break;
600 }
601
602 } else if (NssforRate == RF_3TX) {
603 RTW_INFO("===> SetAntenna 3T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
604
605 switch (ulAntennaTx) {
606 case ANTENNA_BCD:
607 pMptCtx->MptRfPath = ODM_RF_PATH_BCD;
608 /*pHalData->ValidTxPath = 0x0e;*/
609 PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e); /*/ 0x940[27:16]=12'b0010_0100_0111*/
610 break;
611
612 case ANTENNA_ABC:
613 default:
614 pMptCtx->MptRfPath = ODM_RF_PATH_ABC;
615 /*pHalData->ValidTxPath = 0x0d;*/
616 PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247); /*/ 0x940[27:16]=12'b0010_0100_0111*/
617 break;
618 }
619
620 } else { /*/if(NssforRate == RF_1TX)*/
621 RTW_INFO("===> SetAntenna 1T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
622 switch (ulAntennaTx) {
623 case ANTENNA_BCD:
624 pMptCtx->MptRfPath = ODM_RF_PATH_BCD;
625 /*pHalData->ValidTxPath = 0x0e;*/
626 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x7);
627 PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0xe);
628 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0xe);
629 break;
630
631 case ANTENNA_BC:
632 pMptCtx->MptRfPath = ODM_RF_PATH_BC;
633 /*pHalData->ValidTxPath = 0x06;*/
634 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x6);
635 PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0x6);
636 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x6);
637 break;
638 case ANTENNA_B:
639 pMptCtx->MptRfPath = ODM_RF_PATH_B;
640 /*pHalData->ValidTxPath = 0x02;*/
641 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4); /*/ 0xa07[7:4] = 4'b0100*/
642 PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002); /*/ 0x93C[31:20]=12'b0000_0000_0010*/
643 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2); /* 0x80C[7:4] = 4'b0010*/
644 break;
645
646 case ANTENNA_C:
647 pMptCtx->MptRfPath = ODM_RF_PATH_C;
648 /*pHalData->ValidTxPath = 0x04;*/
649 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2); /*/ 0xa07[7:4] = 4'b0010*/
650 PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004); /*/ 0x93C[31:20]=12'b0000_0000_0100*/
651 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4); /*/ 0x80C[7:4] = 4'b0100*/
652 break;
653
654 case ANTENNA_D:
655 pMptCtx->MptRfPath = ODM_RF_PATH_D;
656 /*pHalData->ValidTxPath = 0x08;*/
657 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1); /*/ 0xa07[7:4] = 4'b0001*/
658 PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008); /*/ 0x93C[31:20]=12'b0000_0000_1000*/
659 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8); /*/ 0x80C[7:4] = 4'b1000*/
660 break;
661
662 case ANTENNA_A:
663 default:
664 pMptCtx->MptRfPath = ODM_RF_PATH_A;
665 /*pHalData->ValidTxPath = 0x01;*/
666 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8); /*/ 0xa07[7:4] = 4'b1000*/
667 PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001); /*/ 0x93C[31:20]=12'b0000_0000_0001*/
668 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1); /*/ 0x80C[7:4] = 4'b0001*/
669 break;
670 }
671 }
672
673 switch (ulAntennaRx) {
674 case ANTENNA_A:
675 /*pHalData->ValidRxPath = 0x01;*/
676 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
677 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
678 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
679 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0);
680 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
681 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
682 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
683 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
684 /*/ CCA related PD_delay_th*/
685 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
686 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
687 break;
688
689 case ANTENNA_B:
690 /*pHalData->ValidRxPath = 0x02;*/
691 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
692 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
693 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
694 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1);
695 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
696 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
697 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
698 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
699 /*/ CCA related PD_delay_th*/
700 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
701 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
702 break;
703
704 case ANTENNA_C:
705 /*pHalData->ValidRxPath = 0x04;*/
706 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
707 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44);
708 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
709 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2);
710 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
711 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
712 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
713 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
714 /*/ CCA related PD_delay_th*/
715 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
716 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
717 break;
718
719 case ANTENNA_D:
720 /*pHalData->ValidRxPath = 0x08;*/
721 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
722 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88);
723 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
724 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3);
725 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
726 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
727 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
728 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
729 /*/ CCA related PD_delay_th*/
730 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
731 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
732 break;
733
734 case ANTENNA_BC:
735 /*pHalData->ValidRxPath = 0x06;*/
736 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
737 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66);
738 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
739 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
740 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
741 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
742 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
743 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
744 /*/ CCA related PD_delay_th*/
745 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
746 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
747 break;
748
749 case ANTENNA_CD:
750 /*pHalData->ValidRxPath = 0x0C;*/
751 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
752 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc);
753 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
754 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB);
755 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
756 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
757 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
758 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
759 /*/ CCA related PD_delay_th*/
760 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
761 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
762 break;
763
764 case ANTENNA_BCD:
765 /*pHalData->ValidRxPath = 0x0e;*/
766 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
767 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee);
768 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
769 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
770 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
771 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
772 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
773 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/
774 /*/ CCA related PD_delay_th*/
775 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
776 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
777 break;
778
779 case ANTENNA_ABCD:
780 /*pHalData->ValidRxPath = 0x0f;*/
781 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
782 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff);
783 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
784 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1);
785 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
786 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
787 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
788 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
789 /*/ CCA related PD_delay_th*/
790 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
791 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
792 break;
793
794 default:
795 RT_TRACE(_module_mp_, _drv_warning_, ("Unknown Rx antenna.\n"));
796 break;
797 }
798
799 PHY_Set_SecCCATH_by_RXANT_8814A(pAdapter, ulAntennaRx);
800
801 mpt_ToggleIG_8814A(pAdapter);
802 RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
803 }
804 #endif /* CONFIG_RTL8814A */
805 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
806 VOID
mpt_SetSingleTone_8814A(IN PADAPTER pAdapter,IN BOOLEAN bSingleTone,IN BOOLEAN bEnPMacTx)807 mpt_SetSingleTone_8814A(
808 IN PADAPTER pAdapter,
809 IN BOOLEAN bSingleTone,
810 IN BOOLEAN bEnPMacTx)
811 {
812
813 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
814 u1Byte StartPath = ODM_RF_PATH_A, EndPath = ODM_RF_PATH_A;
815 static u4Byte regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0;
816
817 if (bSingleTone) {
818 regIG0 = PHY_QueryBBReg(pAdapter, rA_TxScale_Jaguar, bMaskDWord); /*/ 0xC1C[31:21]*/
819 regIG1 = PHY_QueryBBReg(pAdapter, rB_TxScale_Jaguar, bMaskDWord); /*/ 0xE1C[31:21]*/
820 regIG2 = PHY_QueryBBReg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord); /*/ 0x181C[31:21]*/
821 regIG3 = PHY_QueryBBReg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord); /*/ 0x1A1C[31:21]*/
822
823 switch (pMptCtx->MptRfPath) {
824 case ODM_RF_PATH_A:
825 case ODM_RF_PATH_B:
826 case ODM_RF_PATH_C:
827 case ODM_RF_PATH_D:
828 StartPath = pMptCtx->MptRfPath;
829 EndPath = pMptCtx->MptRfPath;
830 break;
831 case ODM_RF_PATH_AB:
832 EndPath = ODM_RF_PATH_B;
833 break;
834 case ODM_RF_PATH_BC:
835 StartPath = ODM_RF_PATH_B;
836 EndPath = ODM_RF_PATH_C;
837 break;
838 case ODM_RF_PATH_ABC:
839 EndPath = ODM_RF_PATH_C;
840 break;
841 case ODM_RF_PATH_BCD:
842 StartPath = ODM_RF_PATH_B;
843 EndPath = ODM_RF_PATH_D;
844 break;
845 case ODM_RF_PATH_ABCD:
846 EndPath = ODM_RF_PATH_D;
847 break;
848 }
849
850 if (bEnPMacTx == FALSE) {
851 hal_mpt_SetOFDMContinuousTx(pAdapter, _TRUE);
852 issue_nulldata(pAdapter, NULL, 1, 3, 500);
853 }
854
855 PHY_SetBBReg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/
856
857 for (StartPath; StartPath <= EndPath; StartPath++) {
858 PHY_SetRFReg(pAdapter, StartPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
859 PHY_SetRFReg(pAdapter, StartPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
860
861 PHY_SetRFReg(pAdapter, StartPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/
862 }
863
864 PHY_SetBBReg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/
865 PHY_SetBBReg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/
866 PHY_SetBBReg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/
867 PHY_SetBBReg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/
868 } else {
869 switch (pMptCtx->MptRfPath) {
870 case ODM_RF_PATH_A:
871 case ODM_RF_PATH_B:
872 case ODM_RF_PATH_C:
873 case ODM_RF_PATH_D:
874 StartPath = pMptCtx->MptRfPath;
875 EndPath = pMptCtx->MptRfPath;
876 break;
877 case ODM_RF_PATH_AB:
878 EndPath = ODM_RF_PATH_B;
879 break;
880 case ODM_RF_PATH_BC:
881 StartPath = ODM_RF_PATH_B;
882 EndPath = ODM_RF_PATH_C;
883 break;
884 case ODM_RF_PATH_ABC:
885 EndPath = ODM_RF_PATH_C;
886 break;
887 case ODM_RF_PATH_BCD:
888 StartPath = ODM_RF_PATH_B;
889 EndPath = ODM_RF_PATH_D;
890 break;
891 case ODM_RF_PATH_ABCD:
892 EndPath = ODM_RF_PATH_D;
893 break;
894 }
895 for (StartPath; StartPath <= EndPath; StartPath++)
896 PHY_SetRFReg(pAdapter, StartPath, LNA_Low_Gain_3, BIT1, 0x0); /* RF LO disabled */
897
898 PHY_SetBBReg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/
899
900 if (bEnPMacTx == FALSE)
901 hal_mpt_SetOFDMContinuousTx(pAdapter, _FALSE);
902
903 PHY_SetBBReg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/
904 PHY_SetBBReg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/
905 PHY_SetBBReg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/
906 PHY_SetBBReg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/
907 }
908 }
909
910 #endif
911
912 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
mpt_SetRFPath_8812A(PADAPTER pAdapter)913 void mpt_SetRFPath_8812A(PADAPTER pAdapter)
914 {
915 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
916 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
917 struct mp_priv *pmp = &pAdapter->mppriv;
918 u8 channel = pmp->channel;
919 u8 bandwidth = pmp->bandwidth;
920 u8 eLNA_2g = pHalData->ExternalLNA_2G;
921 u32 ulAntennaTx, ulAntennaRx;
922
923 ulAntennaTx = pHalData->AntennaTxPath;
924 ulAntennaRx = pHalData->AntennaRxPath;
925
926 switch (ulAntennaTx) {
927 case ANTENNA_A:
928 pMptCtx->MptRfPath = ODM_RF_PATH_A;
929 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
930 if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
931 PHY_SetBBReg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
932 break;
933 case ANTENNA_B:
934 pMptCtx->MptRfPath = ODM_RF_PATH_B;
935 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222);
936 if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
937 PHY_SetBBReg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1);
938 break;
939 case ANTENNA_AB:
940 pMptCtx->MptRfPath = ODM_RF_PATH_AB;
941 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333);
942 if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
943 PHY_SetBBReg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
944 break;
945 default:
946 pMptCtx->MptRfPath = ODM_RF_PATH_AB;
947 RTW_INFO("Unknown Tx antenna.\n");
948 break;
949 }
950
951 switch (ulAntennaRx) {
952 u32 reg0xC50 = 0;
953 case ANTENNA_A:
954 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
955 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
956 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
957 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
958
959 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
960 reg0xC50 = PHY_QueryBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
961 PHY_SetBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
962 PHY_SetBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50);
963
964 /* set PWED_TH for BB Yn user guide R29 */
965 if (IS_HARDWARE_TYPE_8812(pAdapter)) {
966 if (channel <= 14) { /* 2.4G */
967 if (bandwidth == CHANNEL_WIDTH_20
968 && eLNA_2g == 0) {
969 /* 0x830[3:1]=3'b010 */
970 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
971 } else
972 /* 0x830[3:1]=3'b100 */
973 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
974 } else
975 /* 0x830[3:1]=3'b100 for 5G */
976 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
977 }
978 break;
979 case ANTENNA_B:
980 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
981 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */
982 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1);
983 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
984
985 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
986 reg0xC50 = PHY_QueryBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
987 PHY_SetBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
988 PHY_SetBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50);
989
990 /* set PWED_TH for BB Yn user guide R29 */
991 if (IS_HARDWARE_TYPE_8812(pAdapter)) {
992 if (channel <= 14) {
993 if (bandwidth == CHANNEL_WIDTH_20
994 && eLNA_2g == 0) {
995 /* 0x830[3:1]=3'b010 */
996 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
997 } else
998 /* 0x830[3:1]=3'b100 */
999 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1000 } else
1001 /* 0x830[3:1]=3'b100 for 5G */
1002 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1003 }
1004 break;
1005 case ANTENNA_AB:
1006 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33);
1007 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/
1008 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
1009 /* set PWED_TH for BB Yn user guide R29 */
1010 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1011 break;
1012 default:
1013 RTW_INFO("Unknown Rx antenna.\n");
1014 break;
1015 }
1016 RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
1017 }
1018 #endif
1019
1020 #ifdef CONFIG_RTL8723B
mpt_SetRFPath_8723B(PADAPTER pAdapter)1021 void mpt_SetRFPath_8723B(PADAPTER pAdapter)
1022 {
1023 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1024 u32 ulAntennaTx, ulAntennaRx;
1025 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
1026 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1027 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
1028
1029 ulAntennaTx = pHalData->AntennaTxPath;
1030 ulAntennaRx = pHalData->AntennaRxPath;
1031
1032 if (pHalData->rf_chip >= RF_TYPE_MAX) {
1033 RTW_INFO("This RF chip ID is not supported\n");
1034 return;
1035 }
1036
1037 switch (pAdapter->mppriv.antenna_tx) {
1038 u8 p = 0, i = 0;
1039 case ANTENNA_A: { /*/ Actually path S1 (Wi-Fi)*/
1040 pMptCtx->MptRfPath = ODM_RF_PATH_A;
1041 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1042 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1043
1044 /*/<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/
1045 if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))
1046 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);
1047 else
1048 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
1049
1050 for (i = 0; i < 3; ++i) {
1051 u4Byte offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0];
1052 u4Byte data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][1];
1053
1054 if (offset != 0) {
1055 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1056 RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1057 }
1058 }
1059 for (i = 0; i < 2; ++i) {
1060 u4Byte offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0];
1061 u4Byte data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][1];
1062
1063 if (offset != 0) {
1064 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1065 RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1066 }
1067 }
1068 }
1069 break;
1070 case ANTENNA_B: { /*/ Actually path S0 (BT)*/
1071 u4Byte offset;
1072 u4Byte data;
1073
1074 pMptCtx->MptRfPath = ODM_RF_PATH_B;
1075 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1076 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/
1077 /* <20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/
1078 if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))
1079 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);
1080 else
1081 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
1082
1083 for (i = 0; i < 3; ++i) {
1084 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1085 offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0];
1086 data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][1];
1087 if (pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) {
1088 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1089 RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1090 }
1091 }
1092 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1093 for (i = 0; i < 2; ++i) {
1094 offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0];
1095 data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][1];
1096 if (pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) {
1097 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1098 RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1099 }
1100 }
1101 }
1102 break;
1103 default:
1104 pMptCtx->MptRfPath = RF_PATH_AB;
1105 RT_TRACE(_module_mp_, _drv_notice_, ("Unknown Tx antenna.\n"));
1106 break;
1107 }
1108 RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
1109 }
1110 #endif
1111
1112 #ifdef CONFIG_RTL8703B
mpt_SetRFPath_8703B(PADAPTER pAdapter)1113 void mpt_SetRFPath_8703B(PADAPTER pAdapter)
1114 {
1115 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1116 u4Byte ulAntennaTx, ulAntennaRx;
1117 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
1118 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1119 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
1120
1121 ulAntennaTx = pHalData->AntennaTxPath;
1122 ulAntennaRx = pHalData->AntennaRxPath;
1123
1124 if (pHalData->rf_chip >= RF_TYPE_MAX) {
1125 RTW_INFO("This RF chip ID is not supported\n");
1126 return;
1127 }
1128
1129 switch (pAdapter->mppriv.antenna_tx) {
1130 u1Byte p = 0, i = 0;
1131
1132 case ANTENNA_A: { /* Actually path S1 (Wi-Fi) */
1133 pMptCtx->MptRfPath = ODM_RF_PATH_A;
1134 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1135 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1136
1137 for (i = 0; i < 3; ++i) {
1138 u4Byte offset = pRFCalibrateInfo->TxIQC_8703B[i][0];
1139 u4Byte data = pRFCalibrateInfo->TxIQC_8703B[i][1];
1140
1141 if (offset != 0) {
1142 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1143 RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1144 }
1145
1146 }
1147 for (i = 0; i < 2; ++i) {
1148 u4Byte offset = pRFCalibrateInfo->RxIQC_8703B[i][0];
1149 u4Byte data = pRFCalibrateInfo->RxIQC_8703B[i][1];
1150
1151 if (offset != 0) {
1152 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1153 RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1154 }
1155 }
1156 }
1157 break;
1158 case ANTENNA_B: { /* Actually path S0 (BT)*/
1159 pMptCtx->MptRfPath = ODM_RF_PATH_B;
1160 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1161 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */
1162
1163 for (i = 0; i < 3; ++i) {
1164 u4Byte offset = pRFCalibrateInfo->TxIQC_8703B[i][0];
1165 u4Byte data = pRFCalibrateInfo->TxIQC_8703B[i][1];
1166
1167 if (pRFCalibrateInfo->TxIQC_8703B[i][0] != 0) {
1168 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1169 RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1170 }
1171 }
1172 for (i = 0; i < 2; ++i) {
1173 u4Byte offset = pRFCalibrateInfo->RxIQC_8703B[i][0];
1174 u4Byte data = pRFCalibrateInfo->RxIQC_8703B[i][1];
1175
1176 if (pRFCalibrateInfo->RxIQC_8703B[i][0] != 0) {
1177 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1178 RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1179 }
1180 }
1181 }
1182 break;
1183 default:
1184 pMptCtx->MptRfPath = RF_PATH_AB;
1185 RT_TRACE(_module_mp_, _drv_notice_, ("Unknown Tx antenna.\n"));
1186 break;
1187 }
1188
1189 RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
1190 }
1191 #endif
1192
1193 #ifdef CONFIG_RTL8723D
mpt_SetRFPath_8723D(PADAPTER pAdapter)1194 void mpt_SetRFPath_8723D(PADAPTER pAdapter)
1195 {
1196 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1197 u1Byte p = 0, i = 0;
1198 u4Byte ulAntennaTx, ulAntennaRx, offset = 0, data = 0, val32 = 0;
1199 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
1200 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1201 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
1202
1203 ulAntennaTx = pHalData->AntennaTxPath;
1204 ulAntennaRx = pHalData->AntennaRxPath;
1205
1206 if (pHalData->rf_chip >= RF_TYPE_MAX) {
1207 RTW_INFO("This RF chip ID is not supported\n");
1208 return;
1209 }
1210
1211 switch (pAdapter->mppriv.antenna_tx) {
1212 /* Actually path S1 (Wi-Fi) */
1213 case ANTENNA_A: {
1214 pMptCtx->MptRfPath = ODM_RF_PATH_A;
1215 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch,
1216 BIT9 | BIT8 | BIT7, 0x0);
1217 /* AGC Table Sel */
1218 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x0);
1219
1220 /*<20130522, Kordan> 0x51 and 0x71 should be set immediately
1221 after path switched, or they might be overwritten.*/
1222 if ((pHalData->PackageType == PACKAGE_TFBGA79) ||
1223 (pHalData->PackageType == PACKAGE_TFBGA90))
1224 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A,
1225 0x51, bRFRegOffsetMask, 0x6B10E);
1226 else
1227 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A,
1228 0x51, bRFRegOffsetMask, 0x6B04E);
1229
1230
1231 for (i = 0; i < 3; ++i) {
1232 offset = pRFCalibrateInfo->TxIQC_8723D[RF_PATH_A][i][0];
1233 data = pRFCalibrateInfo->TxIQC_8723D[RF_PATH_A][i][1];
1234 if (offset != 0) {
1235 PHY_SetBBReg(pAdapter, offset,
1236 bMaskDWord, data);
1237 RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1238 }
1239
1240 }
1241 for (i = 0; i < 2; ++i) {
1242 offset = pRFCalibrateInfo->RxIQC_8723D[RF_PATH_A][i][0];
1243 data = pRFCalibrateInfo->RxIQC_8723D[RF_PATH_A][i][1];
1244 if (offset != 0) {
1245 PHY_SetBBReg(pAdapter, offset,
1246 bMaskDWord, data);
1247 RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1248 }
1249 }
1250 }
1251 break;
1252 /* Actually path S0 (BT) */
1253 case ANTENNA_B: {
1254 pMptCtx->MptRfPath = ODM_RF_PATH_B;
1255 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1256 /* AGC Table Sel */
1257 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x1);
1258 /* <20130522, Kordan> 0x51 and 0x71 should be set immediately
1259 after path switched, or they might be overwritten.*/
1260 if ((pHalData->PackageType == PACKAGE_TFBGA79) ||
1261 (pHalData->PackageType == PACKAGE_TFBGA90))
1262 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51,
1263 bRFRegOffsetMask, 0x6B10E);
1264 else
1265 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51,
1266 bRFRegOffsetMask, 0x6B04E);
1267
1268
1269 for (i = 0; i < 3; ++i) {
1270 /* <20130603, Kordan> Because BB suppors only 1T1R,
1271 we restore IQC to S1 instead of S0.*/
1272 offset = pRFCalibrateInfo->TxIQC_8723D[RF_PATH_A][i][0];
1273 data = pRFCalibrateInfo->TxIQC_8723D[RF_PATH_B][i][1];
1274 val32 = pRFCalibrateInfo->TxIQC_8723D[RF_PATH_B][i][0];
1275 if (val32 != 0) {
1276 PHY_SetBBReg(pAdapter, offset,
1277 bMaskDWord, data);
1278 RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1279 }
1280 }
1281 for (i = 0; i < 2; ++i) {
1282 /* <20130603, Kordan> Because BB suppors only 1T1R, we restore
1283 * IQC to S1 instead of S0.*/
1284 offset = pRFCalibrateInfo->RxIQC_8723D[RF_PATH_A][i][0];
1285 data = pRFCalibrateInfo->RxIQC_8723D[RF_PATH_B][i][1];
1286 val32 = pRFCalibrateInfo->RxIQC_8723D[RF_PATH_B][i][0];
1287 if (val32 != 0) {
1288 PHY_SetBBReg(pAdapter, offset,
1289 bMaskDWord, data);
1290 RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1291 }
1292 }
1293
1294 }
1295 break;
1296 default:
1297 pMptCtx->MptRfPath = RF_PATH_AB;
1298 RT_TRACE(_module_mp_, _drv_notice_, ("Unknown Tx antenna.\n"));
1299 break;
1300 }
1301 RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
1302 }
1303 #endif
1304
mpt_SetRFPath_819X(PADAPTER pAdapter)1305 VOID mpt_SetRFPath_819X(PADAPTER pAdapter)
1306 {
1307 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1308 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
1309 u4Byte ulAntennaTx, ulAntennaRx;
1310 R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
1311 R_ANTENNA_SELECT_CCK *p_cck_txrx;
1312 u1Byte r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
1313 u1Byte chgTx = 0, chgRx = 0;
1314 u4Byte r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
1315
1316 ulAntennaTx = pHalData->AntennaTxPath;
1317 ulAntennaRx = pHalData->AntennaRxPath;
1318
1319 p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;
1320 p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;
1321
1322 p_ofdm_tx->r_ant_ht1 = 0x1;
1323 p_ofdm_tx->r_ant_ht2 = 0x2;/*Second TX RF path is A*/
1324 p_ofdm_tx->r_ant_non_ht = 0x3;/*/ 0x1+0x2=0x3 */
1325
1326 switch (ulAntennaTx) {
1327 case ANTENNA_A:
1328 p_ofdm_tx->r_tx_antenna = 0x1;
1329 r_ofdm_tx_en_val = 0x1;
1330 p_ofdm_tx->r_ant_l = 0x1;
1331 p_ofdm_tx->r_ant_ht_s1 = 0x1;
1332 p_ofdm_tx->r_ant_non_ht_s1 = 0x1;
1333 p_cck_txrx->r_ccktx_enable = 0x8;
1334 chgTx = 1;
1335 /*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
1336 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1337 {
1338 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1339 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
1340 r_ofdm_tx_en_val = 0x3;
1341 /*/ Power save*/
1342 /*/cosa r_ant_select_ofdm_val = 0x11111111;*/
1343 /*/ We need to close RFB by SW control*/
1344 if (pHalData->rf_type == RF_2T2R) {
1345 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1346 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
1347 PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
1348 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1349 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
1350 }
1351 }
1352 pMptCtx->MptRfPath = ODM_RF_PATH_A;
1353 break;
1354 case ANTENNA_B:
1355 p_ofdm_tx->r_tx_antenna = 0x2;
1356 r_ofdm_tx_en_val = 0x2;
1357 p_ofdm_tx->r_ant_l = 0x2;
1358 p_ofdm_tx->r_ant_ht_s1 = 0x2;
1359 p_ofdm_tx->r_ant_non_ht_s1 = 0x2;
1360 p_cck_txrx->r_ccktx_enable = 0x4;
1361 chgTx = 1;
1362 /*/ From SD3 Willis suggestion !!! Set RF A as standby*/
1363 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1364 {
1365 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
1366 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1367
1368 /*/ 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.*/
1369 /*/ 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control*/
1370 if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
1371 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
1372 PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
1373 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1374 /*/PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1375 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
1376 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1377 }
1378 }
1379 pMptCtx->MptRfPath = ODM_RF_PATH_B;
1380 break;
1381 case ANTENNA_AB:/*/ For 8192S*/
1382 p_ofdm_tx->r_tx_antenna = 0x3;
1383 r_ofdm_tx_en_val = 0x3;
1384 p_ofdm_tx->r_ant_l = 0x3;
1385 p_ofdm_tx->r_ant_ht_s1 = 0x3;
1386 p_ofdm_tx->r_ant_non_ht_s1 = 0x3;
1387 p_cck_txrx->r_ccktx_enable = 0xC;
1388 chgTx = 1;
1389 /*/ From SD3Willis suggestion !!! Set RF B as standby*/
1390 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1391 {
1392 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1393 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1394 /* Disable Power save*/
1395 /*cosa r_ant_select_ofdm_val = 0x3321333;*/
1396 /* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control*/
1397 if (pHalData->rf_type == RF_2T2R) {
1398 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1399
1400 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1401 /*/PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1402 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1403 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1404 }
1405 }
1406 pMptCtx->MptRfPath = ODM_RF_PATH_AB;
1407 break;
1408 default:
1409 break;
1410 }
1411 #if 0
1412 /* r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */
1413 /* r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */
1414 /* r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D */
1415 #endif
1416 switch (ulAntennaRx) {
1417 case ANTENNA_A:
1418 r_rx_antenna_ofdm = 0x1; /* A*/
1419 p_cck_txrx->r_cckrx_enable = 0x0; /* default: A*/
1420 p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A*/
1421 chgRx = 1;
1422 break;
1423 case ANTENNA_B:
1424 r_rx_antenna_ofdm = 0x2; /*/ B*/
1425 p_cck_txrx->r_cckrx_enable = 0x1; /*/ default: B*/
1426 p_cck_txrx->r_cckrx_enable_2 = 0x1; /*/ option: B*/
1427 chgRx = 1;
1428 break;
1429 case ANTENNA_AB:/*/ For 8192S and 8192E/U...*/
1430 r_rx_antenna_ofdm = 0x3;/*/ AB*/
1431 p_cck_txrx->r_cckrx_enable = 0x0;/*/ default:A*/
1432 p_cck_txrx->r_cckrx_enable_2 = 0x1;/*/ option:B*/
1433 chgRx = 1;
1434 break;
1435 default:
1436 break;
1437 }
1438
1439
1440 if (chgTx && chgRx) {
1441 switch (pHalData->rf_chip) {
1442 case RF_8225:
1443 case RF_8256:
1444 case RF_6052:
1445 /*/r_ant_sel_cck_val = r_ant_select_cck_val;*/
1446 PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); /*/OFDM Tx*/
1447 PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); /*/OFDM Tx*/
1448 PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
1449 PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
1450 if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1451 PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
1452 PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
1453 }
1454 PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/
1455 break;
1456
1457 default:
1458 RTW_INFO("Unsupported RFChipID for switching antenna.\n");
1459 break;
1460 }
1461 }
1462 } /* MPT_ProSetRFPath */
1463
1464
hal_mpt_SetAntenna(PADAPTER pAdapter)1465 void hal_mpt_SetAntenna(PADAPTER pAdapter)
1466
1467 {
1468 RTW_INFO("Do %s\n", __func__);
1469 #ifdef CONFIG_RTL8814A
1470 if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
1471 mpt_SetRFPath_8814A(pAdapter);
1472 return;
1473 }
1474 #endif
1475 #ifdef CONFIG_RTL8822B
1476 if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
1477 rtl8822b_mp_config_rfpath(pAdapter);
1478 return;
1479 }
1480 #endif
1481 #ifdef CONFIG_RTL8821C
1482 if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
1483 rtl8821c_mp_config_rfpath(pAdapter);
1484 return;
1485 }
1486 #endif
1487 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1488 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {
1489 mpt_SetRFPath_8812A(pAdapter);
1490 return;
1491 }
1492 #endif
1493 #ifdef CONFIG_RTL8723B
1494 if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1495 mpt_SetRFPath_8723B(pAdapter);
1496 return;
1497 }
1498 #endif
1499
1500 #ifdef CONFIG_RTL8703B
1501 if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1502 mpt_SetRFPath_8703B(pAdapter);
1503 return;
1504 }
1505 #endif
1506
1507 #ifdef CONFIG_RTL8723D
1508 if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1509 mpt_SetRFPath_8723D(pAdapter);
1510 return;
1511 }
1512 #endif
1513 /* else if (IS_HARDWARE_TYPE_8821B(pAdapter))
1514 mpt_SetRFPath_8821B(pAdapter);
1515 Prepare for 8822B
1516 else if (IS_HARDWARE_TYPE_8822B(Context))
1517 mpt_SetRFPath_8822B(Context);
1518 */
1519 mpt_SetRFPath_819X(pAdapter);
1520 RTW_INFO("mpt_SetRFPath_819X Do %s\n", __func__);
1521 }
1522
hal_mpt_SetThermalMeter(PADAPTER pAdapter,u8 target_ther)1523 s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
1524 {
1525 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1526
1527 if (!netif_running(pAdapter->pnetdev)) {
1528 RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter! Fail: interface not opened!\n"));
1529 return _FAIL;
1530 }
1531
1532
1533 if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
1534 RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter: Fail! not in MP mode!\n"));
1535 return _FAIL;
1536 }
1537
1538
1539 target_ther &= 0xff;
1540 if (target_ther < 0x07)
1541 target_ther = 0x07;
1542 else if (target_ther > 0x1d)
1543 target_ther = 0x1d;
1544
1545 pHalData->EEPROMThermalMeter = target_ther;
1546
1547 return _SUCCESS;
1548 }
1549
1550
hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)1551 void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)
1552 {
1553 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x42, BIT17 | BIT16, 0x03);
1554
1555 }
1556
1557
hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter)1558 u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter)
1559
1560 {
1561 u32 ThermalValue = 0;
1562
1563 ThermalValue = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, 0x42, 0xfc00); /*0x42: RF Reg[15:10]*/
1564 return (u8)ThermalValue;
1565
1566 }
1567
1568
hal_mpt_GetThermalMeter(PADAPTER pAdapter,u8 * value)1569 void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 *value)
1570 {
1571 #if 0
1572 fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
1573 rtw_msleep_os(1000);
1574 fw_cmd_data(pAdapter, value, 1);
1575 *value &= 0xFF;
1576 #else
1577 hal_mpt_TriggerRFThermalMeter(pAdapter);
1578 rtw_msleep_os(1000);
1579 *value = hal_mpt_ReadRFThermalMeter(pAdapter);
1580 #endif
1581
1582 }
1583
1584
hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter,u8 bStart)1585 void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
1586 {
1587 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1588
1589 pAdapter->mppriv.MptCtx.bSingleCarrier = bStart;
1590
1591 if (bStart) {/*/ Start Single Carrier.*/
1592 RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleCarrierTx: test start\n"));
1593 /*/ Start Single Carrier.*/
1594 /*/ 1. if OFDM block on?*/
1595 if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
1596 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/
1597
1598 /*/ 2. set CCK test mode off, set to CCK normal mode*/
1599 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0);
1600
1601 /*/ 3. turn on scramble setting*/
1602 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1);
1603
1604 /*/ 4. Turn On Continue Tx and turn off the other test modes.*/
1605 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1606 if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
1607 PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_SingleCarrier);
1608 else
1609 #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1610 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleCarrier);
1611
1612 } else {
1613 /*/ Stop Single Carrier.*/
1614 /*/ Stop Single Carrier.*/
1615 /*/ Turn off all test modes.*/
1616 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1617 if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
1618 PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1619 else
1620 #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1621 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1622
1623 rtw_msleep_os(10);
1624 /*/BB Reset*/
1625 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1626 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1627 }
1628 }
1629
1630
hal_mpt_SetSingleToneTx(PADAPTER pAdapter,u8 bStart)1631 void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
1632 {
1633 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1634 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
1635 u4Byte ulAntennaTx = pHalData->AntennaTxPath;
1636 static u4Byte regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0;
1637 u8 rfPath;
1638
1639 switch (ulAntennaTx) {
1640 case ANTENNA_B:
1641 rfPath = ODM_RF_PATH_B;
1642 break;
1643 case ANTENNA_C:
1644 rfPath = ODM_RF_PATH_C;
1645 break;
1646 case ANTENNA_D:
1647 rfPath = ODM_RF_PATH_D;
1648 break;
1649 case ANTENNA_A:
1650 default:
1651 rfPath = ODM_RF_PATH_A;
1652 break;
1653 }
1654
1655 pAdapter->mppriv.MptCtx.bSingleTone = bStart;
1656 if (bStart) {
1657 /*/ Start Single Tone.*/
1658 /*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/
1659 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1660 regRF = PHY_QueryRFReg(pAdapter, rfPath, LNA_Low_Gain_3, bRFRegOffsetMask);
1661 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1662 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
1663 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
1664 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
1665 /*/Set MAC REG 88C: Prevent SingleTone Fail*/
1666 PHY_SetMacReg(pAdapter, 0x88C, 0xF00000, 0xF);
1667 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO disabled*/
1668 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1669 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1670 if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
1671 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1672 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/
1673 } else {
1674 /*/ S0/S1 both use PATH A to configure*/
1675 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1676 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/
1677 }
1678 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1679 if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
1680 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */
1681 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */
1682 }
1683 } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) {
1684 /*Set BB REG 88C: Prevent SingleTone Fail*/
1685 PHY_SetBBReg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF);
1686 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1);
1687 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x2);
1688
1689 } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1690 if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
1691 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1692 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x0);
1693 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x53, BIT0, 0x1);
1694 } else {/* S0/S1 both use PATH A to configure */
1695 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1696 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x0);
1697 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x63, BIT0, 0x1);
1698 }
1699 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) {
1700 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1701 u1Byte p = ODM_RF_PATH_A;
1702
1703 regRF = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);
1704 regBB0 = PHY_QueryBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);
1705 regBB1 = PHY_QueryBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);
1706 regBB2 = PHY_QueryBBReg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1707 regBB3 = PHY_QueryBBReg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1708
1709 PHY_SetBBReg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x0); /*/ Disable CCK and OFDM*/
1710
1711 if (pMptCtx->MptRfPath == ODM_RF_PATH_AB) {
1712 for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) {
1713 PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1714 PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1715 PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1716 }
1717 } else {
1718 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1719 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1720 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1721 }
1722
1723 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1724 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1725
1726 if (pHalData->ExternalPA_5G) {
1727 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/
1728 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/
1729 } else if (pHalData->ExternalPA_2G) {
1730 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/
1731 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/
1732 }
1733 #endif
1734 }
1735 #ifdef CONFIG_RTL8814A
1736 else if (IS_HARDWARE_TYPE_8814A(pAdapter))
1737 mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE);
1738 #endif
1739 else /*/ Turn On SingleTone and turn off the other test modes.*/
1740 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone);
1741
1742 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1743 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1744
1745 } else {/*/ Stop Single Ton e.*/
1746
1747 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1748 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, regRF);
1749 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
1750 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
1751 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1752 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/
1753 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x0);/*/ RF LO disabled */
1754 /*/ RESTORE MAC REG 88C: Enable RF Functions*/
1755 PHY_SetMacReg(pAdapter, 0x88C, 0xF00000, 0x0);
1756 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1757 if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
1758 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1759 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/
1760 } else {
1761 /*/ S0/S1 both use PATH A to configure*/
1762 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1763 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/
1764 }
1765 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1766 if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
1767 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */
1768 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */
1769 }
1770 } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) {
1771 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x3); /*Tx mode*/
1772 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x0); /*RF LO disabled*/
1773 /*Set BB REG 88C: Prevent SingleTone Fail*/
1774 PHY_SetBBReg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc);
1775 } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1776 if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
1777 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
1778 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x1);
1779 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x53, BIT0, 0x0);
1780 } else { /* S0/S1 both use PATH A to configure */
1781 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
1782 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x1);
1783 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x63, BIT0, 0x0);
1784 }
1785 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) {
1786 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1787 u1Byte p = ODM_RF_PATH_A;
1788
1789 PHY_SetBBReg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x3); /*/ Disable CCK and OFDM*/
1790
1791 if (pMptCtx->MptRfPath == ODM_RF_PATH_AB) {
1792 for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) {
1793 PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
1794 PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x0); /*/ RF LO disabled*/
1795 }
1796 } else {
1797 PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
1798 PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x0); /*/ RF LO disabled*/
1799 }
1800
1801 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0);
1802 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1);
1803 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB2);
1804 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB3);
1805 #endif
1806 }
1807 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1808 else if (IS_HARDWARE_TYPE_8814A(pAdapter))
1809 mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE);
1810
1811 else/*/ Turn off all test modes.*/
1812 PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1813 #endif
1814 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1815 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1816
1817 }
1818 }
1819
hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter,u8 bStart)1820 void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
1821 {
1822 u8 Rate;
1823
1824 pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;
1825
1826 Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
1827 if (bStart) {/* Start Carrier Suppression.*/
1828 RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test start\n"));
1829 if (Rate <= MPT_RATE_11M) {
1830 /*/ 1. if CCK block on?*/
1831 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
1832 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
1833
1834 /*/Turn Off All Test Mode*/
1835 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
1836 PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /* rSingleTone_ContTx_Jaguar*/
1837 else
1838 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1839
1840 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/
1841 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); /*/turn off scramble setting*/
1842
1843 /*/Set CCK Tx Test Rate*/
1844 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); /*/Set FTxRate to 1Mbps*/
1845 }
1846
1847 /*Set for dynamic set Power index*/
1848 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1849 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1850
1851 } else {/* Stop Carrier Suppression.*/
1852 RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test stop\n"));
1853
1854 if (Rate <= MPT_RATE_11M) {
1855 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
1856 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
1857
1858 /*BB Reset*/
1859 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1860 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1861 }
1862 /*Stop for dynamic set Power index*/
1863 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1864 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1865 }
1866 RTW_INFO("\n MPT_ProSetCarrierSupp() is finished.\n");
1867 }
1868
hal_mpt_SetCCKContinuousTx(PADAPTER pAdapter,u8 bStart)1869 void hal_mpt_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)
1870 {
1871 u32 cckrate;
1872
1873 if (bStart) {
1874 RT_TRACE(_module_mp_, _drv_alert_,
1875 ("SetCCKContinuousTx: test start\n"));
1876
1877 /*/ 1. if CCK block on?*/
1878 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
1879 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
1880
1881 /*/Turn Off All Test Mode*/
1882 if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
1883 PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /*rSingleTone_ContTx_Jaguar*/
1884 else
1885 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1886
1887 /*/Set CCK Tx Test Rate*/
1888
1889 cckrate = pAdapter->mppriv.rateidx;
1890
1891 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
1892 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/
1893 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); /*/turn on scramble setting*/
1894
1895 if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) {
1896 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* rCCK0_RxHP 0xa15[1:0] = 11 force cck rxiq = 0*/
1897 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /*/ 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
1898 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
1899 PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 1);
1900 }
1901
1902 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1903 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1904
1905 } else {
1906 RT_TRACE(_module_mp_, _drv_info_,
1907 ("SetCCKContinuousTx: test stop\n"));
1908
1909 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*/normal mode*/
1910 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); /*/turn on scramble setting*/
1911
1912 if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_8814A(pAdapter) /* && !IS_HARDWARE_TYPE_8822B(pAdapter) */) {
1913 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0);/* rCCK0_RxHP 0xa15[1:0] = 2b00*/
1914 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /*/ 0xc08[16] = 0*/
1915 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
1916 PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 0);
1917 }
1918
1919 /*/BB Reset*/
1920 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1921 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1922
1923 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1924 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1925 }
1926
1927 pAdapter->mppriv.MptCtx.bCckContTx = bStart;
1928 pAdapter->mppriv.MptCtx.bOfdmContTx = _FALSE;
1929 }
1930
hal_mpt_SetOFDMContinuousTx(PADAPTER pAdapter,u8 bStart)1931 void hal_mpt_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)
1932 {
1933 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1934
1935 if (bStart) {
1936 RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n"));/*/ 1. if OFDM block on?*/
1937 if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
1938 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*/set OFDM block on*/
1939
1940 /*/ 2. set CCK test mode off, set to CCK normal mode*/
1941 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0);
1942
1943 /*/ 3. turn on scramble setting*/
1944 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1);
1945
1946 if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_8814A(pAdapter) /*&& !IS_HARDWARE_TYPE_8822B(pAdapter)*/) {
1947 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* rCCK0_RxHP 0xa15[1:0] = 2b'11*/
1948 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/
1949 }
1950
1951 /*/ 4. Turn On Continue Tx and turn off the other test modes.*/
1952 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
1953 PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx); /*rSingleTone_ContTx_Jaguar*/
1954 else
1955 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx);
1956
1957 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1958 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1959
1960 } else {
1961 RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test stop\n"));
1962 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
1963 PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1964 else
1965 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1966 /*/Delay 10 ms*/
1967 rtw_msleep_os(10);
1968
1969 if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_8814A(pAdapter) /*&&! IS_HARDWARE_TYPE_8822B(pAdapter)*/) {
1970 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0);/*/ 0xa15[1:0] = 0*/
1971 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0);/*/ 0xc08[16] = 0*/
1972 }
1973
1974 /*/BB Reset*/
1975 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1976 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1977
1978 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1979 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1980 }
1981
1982 pAdapter->mppriv.MptCtx.bCckContTx = _FALSE;
1983 pAdapter->mppriv.MptCtx.bOfdmContTx = bStart;
1984 }
1985
hal_mpt_query_phytxok(PADAPTER pAdapter)1986 u32 hal_mpt_query_phytxok(PADAPTER pAdapter)
1987 {
1988 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
1989 RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
1990 u16 count = 0;
1991
1992 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
1993 count = PHY_QueryBBReg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/
1994 else
1995 count = PHY_QueryBBReg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/
1996
1997 if (count > 50000) {
1998 rtw_reset_phy_trx_ok_counters(pAdapter);
1999 pAdapter->mppriv.tx.sended += count;
2000 count = 0;
2001 }
2002
2003 return pAdapter->mppriv.tx.sended + count;
2004
2005 }
2006
2007 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
2008 /* for HW TX mode */
mpt_StopCckContTx(PADAPTER pAdapter)2009 static VOID mpt_StopCckContTx(
2010 PADAPTER pAdapter
2011 )
2012 {
2013 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2014 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
2015 u1Byte u1bReg;
2016
2017 pMptCtx->bCckContTx = FALSE;
2018 pMptCtx->bOfdmContTx = FALSE;
2019
2020 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
2021 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
2022
2023 if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
2024 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 2b00*/
2025 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
2026
2027 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
2028 PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 0);
2029 }
2030
2031 /*BB Reset*/
2032 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2033 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2034
2035 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2036 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2037
2038 } /* mpt_StopCckContTx */
2039
2040
mpt_StopOfdmContTx(PADAPTER pAdapter)2041 static VOID mpt_StopOfdmContTx(
2042 PADAPTER pAdapter
2043 )
2044 {
2045 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2046 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
2047 u1Byte u1bReg;
2048 u4Byte data;
2049
2050 pMptCtx->bCckContTx = FALSE;
2051 pMptCtx->bOfdmContTx = FALSE;
2052
2053 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter))
2054 PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
2055 else
2056 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2057
2058 rtw_mdelay_os(10);
2059
2060 if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
2061 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 0*/
2062 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
2063 }
2064
2065 /*BB Reset*/
2066 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2067 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2068
2069 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2070 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2071 } /* mpt_StopOfdmContTx */
2072
2073
mpt_StartCckContTx(PADAPTER pAdapter)2074 static VOID mpt_StartCckContTx(
2075 PADAPTER pAdapter
2076 )
2077 {
2078 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2079 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
2080 u4Byte cckrate;
2081
2082 /* 1. if CCK block on */
2083 if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn))
2084 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/
2085
2086 /*Turn Off All Test Mode*/
2087 if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
2088 PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
2089 else
2090 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2091
2092 cckrate = pAdapter->mppriv.rateidx;
2093
2094 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
2095
2096 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*transmit mode*/
2097 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
2098
2099 if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) {
2100 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 11 force cck rxiq = 0*/
2101 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
2102 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
2103 PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 1);
2104 }
2105
2106 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2107 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2108
2109 pMptCtx->bCckContTx = TRUE;
2110 pMptCtx->bOfdmContTx = FALSE;
2111
2112 } /* mpt_StartCckContTx */
2113
2114
mpt_StartOfdmContTx(PADAPTER pAdapter)2115 static VOID mpt_StartOfdmContTx(
2116 PADAPTER pAdapter
2117 )
2118 {
2119 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2120 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
2121
2122 /* 1. if OFDM block on?*/
2123 if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
2124 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/
2125
2126 /* 2. set CCK test mode off, set to CCK normal mode*/
2127 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0);
2128
2129 /* 3. turn on scramble setting*/
2130 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1);
2131
2132 if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
2133 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 2b'11*/
2134 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/
2135 }
2136
2137 /* 4. Turn On Continue Tx and turn off the other test modes.*/
2138 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter))
2139 PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx);
2140 else
2141 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx);
2142
2143 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2144 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2145
2146 pMptCtx->bCckContTx = FALSE;
2147 pMptCtx->bOfdmContTx = TRUE;
2148 } /* mpt_StartOfdmContTx */
2149
2150
mpt_ProSetPMacTx(PADAPTER Adapter)2151 void mpt_ProSetPMacTx(PADAPTER Adapter)
2152 {
2153 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);
2154 RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
2155 u32 u4bTmp;
2156
2157 DbgPrint("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound);
2158 DbgPrint("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount,
2159 PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern);
2160 #if 0
2161 PRINT_DATA("LSIG ", PMacTxInfo.LSIG, 3);
2162 PRINT_DATA("HT_SIG", PMacTxInfo.HT_SIG, 6);
2163 PRINT_DATA("VHT_SIG_A", PMacTxInfo.VHT_SIG_A, 6);
2164 PRINT_DATA("VHT_SIG_B", PMacTxInfo.VHT_SIG_B, 4);
2165 DbgPrint("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC);
2166 PRINT_DATA("VHT_Delimiter", PMacTxInfo.VHT_Delimiter, 4);
2167
2168 PRINT_DATA("Src Address", Adapter->mac_addr, 6);
2169 PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, 6);
2170 #endif
2171
2172 if (PMacTxInfo.bEnPMacTx == FALSE) {
2173 if (PMacTxInfo.Mode == CONTINUOUS_TX) {
2174 PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
2175 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2176 mpt_StopCckContTx(Adapter);
2177 else
2178 mpt_StopOfdmContTx(Adapter);
2179 } else if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2180 u4bTmp = PHY_QueryBBReg(Adapter, 0xf50, bMaskLWord);
2181 PHY_SetBBReg(Adapter, 0xb1c, bMaskLWord, u4bTmp + 50);
2182 PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); /*TX Stop*/
2183 } else
2184 PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
2185
2186 if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
2187 /* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/
2188 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2189 mpt_StopCckContTx(Adapter);
2190 else
2191 mpt_StopOfdmContTx(Adapter);
2192
2193 mpt_SetSingleTone_8814A(Adapter, FALSE, TRUE);
2194 }
2195
2196 return;
2197 }
2198
2199 if (PMacTxInfo.Mode == CONTINUOUS_TX) {
2200 PMacTxInfo.PacketCount = 1;
2201
2202 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2203 mpt_StartCckContTx(Adapter);
2204 else
2205 mpt_StartOfdmContTx(Adapter);
2206 } else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
2207 /* Continuous TX -> HW TX -> RF Setting */
2208 PMacTxInfo.PacketCount = 1;
2209
2210 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2211 mpt_StartCckContTx(Adapter);
2212 else
2213 mpt_StartOfdmContTx(Adapter);
2214 } else if (PMacTxInfo.Mode == PACKETS_TX) {
2215 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0)
2216 PMacTxInfo.PacketCount = 0xffff;
2217 }
2218
2219 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2220 /* 0xb1c[0:15] TX packet count 0xb1C[31:16] SFD*/
2221 u4bTmp = PMacTxInfo.PacketCount | (PMacTxInfo.SFD << 16);
2222 PHY_SetBBReg(Adapter, 0xb1c, bMaskDWord, u4bTmp);
2223 /* 0xb40 7:0 SIGNAL 15:8 SERVICE 31:16 LENGTH*/
2224 u4bTmp = PMacTxInfo.SignalField | (PMacTxInfo.ServiceField << 8) | (PMacTxInfo.LENGTH << 16);
2225 PHY_SetBBReg(Adapter, 0xb40, bMaskDWord, u4bTmp);
2226 u4bTmp = PMacTxInfo.CRC16[0] | (PMacTxInfo.CRC16[1] << 8);
2227 PHY_SetBBReg(Adapter, 0xb44, bMaskLWord, u4bTmp);
2228
2229 if (PMacTxInfo.bSPreamble)
2230 PHY_SetBBReg(Adapter, 0xb0c, BIT27, 0);
2231 else
2232 PHY_SetBBReg(Adapter, 0xb0c, BIT27, 1);
2233 } else {
2234 PHY_SetBBReg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount);
2235
2236 u4bTmp = PMacTxInfo.LSIG[0] | ((PMacTxInfo.LSIG[1]) << 8) | ((PMacTxInfo.LSIG[2]) << 16) | ((PMacTxInfo.PacketPattern) << 24);
2237 PHY_SetBBReg(Adapter, 0xb08, bMaskDWord, u4bTmp); /* Set 0xb08[23:0] = LSIG, 0xb08[31:24] = Data init octet*/
2238
2239 if (PMacTxInfo.PacketPattern == 0x12)
2240 u4bTmp = 0x3000000;
2241 else
2242 u4bTmp = 0;
2243 }
2244
2245 if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) {
2246 u4bTmp |= PMacTxInfo.HT_SIG[0] | ((PMacTxInfo.HT_SIG[1]) << 8) | ((PMacTxInfo.HT_SIG[2]) << 16);
2247 PHY_SetBBReg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2248 u4bTmp = PMacTxInfo.HT_SIG[3] | ((PMacTxInfo.HT_SIG[4]) << 8) | ((PMacTxInfo.HT_SIG[5]) << 16);
2249 PHY_SetBBReg(Adapter, 0xb10, 0xffffff, u4bTmp);
2250 } else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2251 u4bTmp |= PMacTxInfo.VHT_SIG_A[0] | ((PMacTxInfo.VHT_SIG_A[1]) << 8) | ((PMacTxInfo.VHT_SIG_A[2]) << 16);
2252 PHY_SetBBReg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2253 u4bTmp = PMacTxInfo.VHT_SIG_A[3] | ((PMacTxInfo.VHT_SIG_A[4]) << 8) | ((PMacTxInfo.VHT_SIG_A[5]) << 16);
2254 PHY_SetBBReg(Adapter, 0xb10, 0xffffff, u4bTmp);
2255
2256 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_SIG_B, 4);
2257 PHY_SetBBReg(Adapter, 0xb14, bMaskDWord, u4bTmp);
2258 }
2259
2260 if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2261 u4bTmp = (PMacTxInfo.VHT_SIG_B_CRC << 24) | PMacTxInfo.PacketPeriod; /* for TX interval */
2262 PHY_SetBBReg(Adapter, 0xb20, bMaskDWord, u4bTmp);
2263
2264 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_Delimiter, 4);
2265 PHY_SetBBReg(Adapter, 0xb24, bMaskDWord, u4bTmp);
2266
2267 /* 0xb28 - 0xb34 24 byte Probe Request MAC Header*/
2268 /*& Duration & Frame control*/
2269 PHY_SetBBReg(Adapter, 0xb28, bMaskDWord, 0x00000040);
2270
2271 /* Address1 [0:3]*/
2272 u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2273 PHY_SetBBReg(Adapter, 0xb2C, bMaskDWord, u4bTmp);
2274
2275 /* Address3 [3:0]*/
2276 PHY_SetBBReg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2277
2278 /* Address2[0:1] & Address1 [5:4]*/
2279 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2280 PHY_SetBBReg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2281
2282 /* Address2 [5:2]*/
2283 u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2284 PHY_SetBBReg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2285
2286 /* Sequence Control & Address3 [5:4]*/
2287 /*u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8) ;*/
2288 /*PHY_SetBBReg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/
2289 } else {
2290 PHY_SetBBReg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod); /* for TX interval*/
2291 /* & Duration & Frame control */
2292 PHY_SetBBReg(Adapter, 0xb24, bMaskDWord, 0x00000040);
2293
2294 /* 0xb24 - 0xb38 24 byte Probe Request MAC Header*/
2295 /* Address1 [0:3]*/
2296 u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2297 PHY_SetBBReg(Adapter, 0xb28, bMaskDWord, u4bTmp);
2298
2299 /* Address3 [3:0]*/
2300 PHY_SetBBReg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2301
2302 /* Address2[0:1] & Address1 [5:4]*/
2303 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2304 PHY_SetBBReg(Adapter, 0xb2c, bMaskDWord, u4bTmp);
2305
2306 /* Address2 [5:2] */
2307 u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2308 PHY_SetBBReg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2309
2310 /* Sequence Control & Address3 [5:4]*/
2311 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8);
2312 PHY_SetBBReg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2313 }
2314
2315 PHY_SetBBReg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX);
2316
2317 /* 0xb4c 3:0 TXSC 5:4 BW 7:6 m_STBC 8 NDP_Sound*/
2318 u4bTmp = (PMacTxInfo.TX_SC) | ((PMacTxInfo.BandWidth) << 4) | ((PMacTxInfo.m_STBC - 1) << 6) | ((PMacTxInfo.NDP_sound) << 8);
2319 PHY_SetBBReg(Adapter, 0xb4c, 0x1ff, u4bTmp);
2320
2321 if (IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8822B(Adapter)) {
2322 u4Byte offset = 0xb44;
2323
2324 if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
2325 PHY_SetBBReg(Adapter, offset, 0xc0000000, 0);
2326 else if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
2327 PHY_SetBBReg(Adapter, offset, 0xc0000000, 1);
2328 else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
2329 PHY_SetBBReg(Adapter, offset, 0xc0000000, 2);
2330 }
2331
2332 PHY_SetBBReg(Adapter, 0xb00, BIT8, 1); /* Turn on PMAC*/
2333 /* PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); */ /* TX Stop */
2334 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2335 PHY_SetBBReg(Adapter, 0xb04, 0xf, 8); /*TX CCK ON*/
2336 PHY_SetBBReg(Adapter, 0xA84, BIT31, 0);
2337 } else
2338 PHY_SetBBReg(Adapter, 0xb04, 0xf, 4); /* TX Ofdm ON */
2339
2340 if (PMacTxInfo.Mode == OFDM_Single_Tone_TX)
2341 mpt_SetSingleTone_8814A(Adapter, TRUE, TRUE);
2342
2343 }
2344 #endif
2345
hal_mpt_SetContinuousTx(PADAPTER pAdapter,u8 bStart)2346 void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
2347 {
2348 u8 Rate;
2349
2350 RT_TRACE(_module_mp_, _drv_info_,
2351 ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx));
2352 Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
2353 pAdapter->mppriv.MptCtx.bStartContTx = bStart;
2354
2355 if (Rate <= MPT_RATE_11M) {
2356 if (IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
2357 if (bStart)
2358 mpt_StartCckContTx(pAdapter);
2359 else
2360 mpt_StopCckContTx(pAdapter);
2361 } else
2362 hal_mpt_SetCCKContinuousTx(pAdapter, bStart);
2363
2364 } else if (Rate >= MPT_RATE_6M) {
2365 if (IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
2366 if (bStart)
2367 mpt_StartOfdmContTx(pAdapter);
2368 else
2369 mpt_StopOfdmContTx(pAdapter);
2370 } else
2371 hal_mpt_SetOFDMContinuousTx(pAdapter, bStart);
2372 }
2373 }
2374
2375 #endif /* CONFIG_MP_INCLUDE*/
2376