1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20 /*++
21 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
22
23 Module Name:
24 HalPwrSeqCmd.c
25
26 Abstract:
27 Implement HW Power sequence configuration CMD handling routine for Realtek devices.
28
29 Major Change History:
30 When Who What
31 ---------- --------------- -------------------------------
32 2011-10-26 Lucas Modify to be compatible with SD4-CE driver.
33 2011-07-07 Roger Create.
34
35 --*/
36 #include <HalPwrSeqCmd.h>
37
38
39 /*
40 * Description:
41 * This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
42 *
43 * Assumption:
44 * We should follow specific format which was released from HW SD.
45 *
46 * 2011.07.07, added by Roger.
47 * */
HalPwrSeqCmdParsing(PADAPTER padapter,u8 CutVersion,u8 FabVersion,u8 InterfaceType,WLAN_PWR_CFG PwrSeqCmd[])48 u8 HalPwrSeqCmdParsing(
49 PADAPTER padapter,
50 u8 CutVersion,
51 u8 FabVersion,
52 u8 InterfaceType,
53 WLAN_PWR_CFG PwrSeqCmd[])
54 {
55 WLAN_PWR_CFG PwrCfgCmd = {0};
56 u8 bPollingBit = _FALSE;
57 u32 AryIdx = 0;
58 u8 value = 0;
59 u32 offset = 0;
60 u32 pollingCount = 0; /* polling autoload done. */
61 u32 maxPollingCnt = 5000;
62
63 do {
64 PwrCfgCmd = PwrSeqCmd[AryIdx];
65
66 RT_TRACE(_module_hal_init_c_ , _drv_info_,
67 ("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",
68 GET_PWR_CFG_OFFSET(PwrCfgCmd),
69 GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
70 GET_PWR_CFG_FAB_MASK(PwrCfgCmd),
71 GET_PWR_CFG_INTF_MASK(PwrCfgCmd),
72 GET_PWR_CFG_BASE(PwrCfgCmd),
73 GET_PWR_CFG_CMD(PwrCfgCmd),
74 GET_PWR_CFG_MASK(PwrCfgCmd),
75 GET_PWR_CFG_VALUE(PwrCfgCmd)));
76
77 /* 2 Only Handle the command whose FAB, CUT, and Interface are matched */
78 if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
79 (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
80 (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)) {
81 switch (GET_PWR_CFG_CMD(PwrCfgCmd)) {
82 case PWR_CMD_READ:
83 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n"));
84 break;
85
86 case PWR_CMD_WRITE:
87 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n"));
88 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
89
90 #ifdef CONFIG_SDIO_HCI
91 /* */
92 /* <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface */
93 /* 2011.07.07. */
94 /* */
95 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) {
96 /* Read Back SDIO Local value */
97 value = SdioLocalCmd52Read1Byte(padapter, offset);
98
99 value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
100 value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
101
102 /* Write Back SDIO Local value */
103 SdioLocalCmd52Write1Byte(padapter, offset, value);
104 } else
105 #endif
106 {
107 #ifdef CONFIG_GSPI_HCI
108 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
109 offset = SPI_LOCAL_OFFSET | offset;
110 #endif
111 /* Read the value from system register */
112 value = rtw_read8(padapter, offset);
113
114 value = value & (~(GET_PWR_CFG_MASK(PwrCfgCmd)));
115 value = value | (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
116
117 /* Write the value back to sytem register */
118 rtw_write8(padapter, offset, value);
119 }
120 break;
121
122 case PWR_CMD_POLLING:
123 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n"));
124
125 bPollingBit = _FALSE;
126 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
127 #ifdef CONFIG_GSPI_HCI
128 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
129 offset = SPI_LOCAL_OFFSET | offset;
130 #endif
131 do {
132 #ifdef CONFIG_SDIO_HCI
133 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
134 value = SdioLocalCmd52Read1Byte(padapter, offset);
135 else
136 #endif
137 value = rtw_read8(padapter, offset);
138
139 value = value & GET_PWR_CFG_MASK(PwrCfgCmd);
140 if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))
141 bPollingBit = _TRUE;
142 else
143 rtw_udelay_os(10);
144
145 if (pollingCount++ > maxPollingCnt) {
146 RTW_ERR("HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value);
147 return _FALSE;
148 }
149 } while (!bPollingBit);
150
151 break;
152
153 case PWR_CMD_DELAY:
154 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n"));
155 if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
156 rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));
157 else
158 rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd) * 1000);
159 break;
160
161 case PWR_CMD_END:
162 /* When this command is parsed, end the process */
163 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n"));
164 return _TRUE;
165 break;
166
167 default:
168 RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n"));
169 break;
170 }
171 }
172
173 AryIdx++;/* Add Array Index */
174 } while (1);
175
176 return _TRUE;
177 }
178