1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2015 - 2017 Realtek Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 *****************************************************************************/ 16 #ifndef _RTL8822C_HAL_H_ 17 #define _RTL8822C_HAL_H_ 18 19 #include <osdep_service.h> /* BIT(x) */ 20 #include <drv_types.h> /* PADAPTER */ 21 #include "../hal/halmac/halmac_api.h" /* MAC REG definition */ 22 23 #ifdef CONFIG_SUPPORT_TRX_SHARED 24 #define DEF_RECVBUF_SZ 24576 /* RX 24K */ 25 #if (DFT_TRX_SHARE_MODE == 1) 26 #define RX_FIFO_EXPANDING 40960 /* RX= 24K+40K=64K , TX=256K-40K=216K */ 27 #elif (DFT_TRX_SHARE_MODE == 2) 28 #define RX_FIFO_EXPANDING 65536 /* RX= 24K+40K+24=88K , TX=256K-40K-24K=192K */ 29 #elif (DFT_TRX_SHARE_MODE ==3) 30 #define RX_FIFO_EXPANDING 106496 /* RX= 24K+40K+24+40K=128K , TX=256K-40K-24K-40K=152K */ 31 #elif (DFT_TRX_SHARE_MODE ==4) 32 #define RX_FIFO_EXPANDING 131072 /* RX= 24K+40K+24+40K+24K=128K , TX=256K-40K-24K-40K-24K=128K */ 33 #else 34 #define RX_FIFO_EXPANDING 0 35 #endif 36 #define MAX_RECVBUF_SZ (DEF_RECVBUF_SZ + RX_FIFO_EXPANDING) 37 #else /* !CONFIG_SUPPORT_TRX_SHARED */ 38 #ifdef CONFIG_PCI_HCI 39 #define MAX_RECVBUF_SZ 12288 /* 12KB */ 40 #else 41 #define MAX_RECVBUF_SZ 24576 /* 24KB, TX: 256KB */ 42 #endif /* !CONFIG_PCI_HCI */ 43 #endif /* !CONFIG_SUPPORT_TRX_SHARED */ 44 45 /* 46 * MAC Register definition 47 */ 48 #define REG_AFE_XTAL_CTRL REG_AFE_CTRL1_8822C /* hal_com.c & phydm */ 49 #define REG_LEDCFG0 REG_LED_CFG_8822C /* rtw_mp.c */ 50 #define MSR (REG_CR_8822C + 2) /* rtw_mp.c & hal_com.c */ 51 #define MSR1 REG_CR_EXT_8822C /* rtw_mp.c & hal_com.c */ 52 #define REG_C2HEVT_MSG_NORMAL 0x1A0 /* hal_com.c */ 53 #define REG_C2HEVT_CLEAR 0x1AF /* hal_com.c */ 54 #define REG_BCN_CTRL_1 REG_BCN_CTRL_CLINT0_8822C /* hal_com.c */ 55 56 #define REG_WOWLAN_WAKE_REASON 0x01C7 /* hal_com.c */ 57 #define REG_GPIO_PIN_CTRL_2 REG_GPIO_EXT_CTRL_8822C /* hal_com.c */ 58 59 /* RXERR_RPT, for rtw_mp.c */ 60 #define RXERR_TYPE_OFDM_PPDU 0 61 #define RXERR_TYPE_OFDM_FALSE_ALARM 2 62 #define RXERR_TYPE_OFDM_MPDU_OK 0 63 #define RXERR_TYPE_OFDM_MPDU_FAIL 1 64 #define RXERR_TYPE_CCK_PPDU 3 65 #define RXERR_TYPE_CCK_FALSE_ALARM 5 66 #define RXERR_TYPE_CCK_MPDU_OK 3 67 #define RXERR_TYPE_CCK_MPDU_FAIL 4 68 #define RXERR_TYPE_HT_PPDU 8 69 #define RXERR_TYPE_HT_FALSE_ALARM 9 70 #define RXERR_TYPE_HT_MPDU_TOTAL 6 71 #define RXERR_TYPE_HT_MPDU_OK 6 72 #define RXERR_TYPE_HT_MPDU_FAIL 7 73 #define RXERR_TYPE_RX_FULL_DROP 10 74 75 #define RXERR_COUNTER_MASK BIT_MASK_RPT_COUNTER_8822C 76 #define RXERR_RPT_RST BIT_RXERR_RPT_RST_8822C 77 #define _RXERR_RPT_SEL(type) (BIT_RXERR_RPT_SEL_V1_3_0_8822C(type) \ 78 | ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8822C : 0)) 79 80 /* 81 * BB Register definition 82 */ 83 #define rPMAC_Reset 0x100 /* hal_mp.c */ 84 85 #define rFPGA0_RFMOD 0x800 86 #define rFPGA0_TxInfo 0x804 87 #define rOFDMCCKEN_Jaguar 0x808 /* hal_mp.c */ 88 #define rFPGA0_TxGainStage 0x80C /* phydm only */ 89 #define rFPGA0_XA_HSSIParameter1 0x820 /* hal_mp.c */ 90 #define rFPGA0_XA_HSSIParameter2 0x824 /* hal_mp.c */ 91 #define rFPGA0_XB_HSSIParameter1 0x828 /* hal_mp.c */ 92 #define rFPGA0_XB_HSSIParameter2 0x82C /* hal_mp.c */ 93 #define rTxAGC_B_Rate18_06 0x830 94 #define rTxAGC_B_Rate54_24 0x834 95 #define rTxAGC_B_CCK1_55_Mcs32 0x838 96 #define rCCAonSec_Jaguar 0x838 /* hal_mp.c */ 97 #define rTxAGC_B_Mcs03_Mcs00 0x83C 98 #define rTxAGC_B_Mcs07_Mcs04 0x848 99 #define rTxAGC_B_Mcs11_Mcs08 0x84C 100 #define rFPGA0_XA_RFInterfaceOE 0x860 101 #define rFPGA0_XB_RFInterfaceOE 0x864 102 #define rTxAGC_B_Mcs15_Mcs12 0x868 103 #define rTxAGC_B_CCK11_A_CCK2_11 0x86C 104 #define rFPGA0_XAB_RFInterfaceSW 0x870 105 #define rFPGA0_XAB_RFParameter 0x878 106 #define rFPGA0_AnalogParameter4 0x88C /* hal_mp.c & phydm */ 107 #define rFPGA0_XB_LSSIReadBack 0x8A4 /* phydm */ 108 #define rHSSIRead_Jaguar 0x8B0 /* RF read addr (rtl8822c_phy.c) */ 109 110 #define rC_TxScale_Jaguar2 0x181C /* Pah_C TX scaling factor (hal_mp.c) */ 111 #define rC_IGI_Jaguar2 0x1850 /* Initial Gain for path-C (hal_mp.c) */ 112 113 #define rFPGA1_TxInfo 0x90C /* hal_mp.c */ 114 #define rSingleTone_ContTx_Jaguar 0x914 /* hal_mp.c */ 115 /* TX BeamForming */ 116 #define REG_BB_TX_PATH_SEL_1_8822C 0x93C /* rtl8822c_phy.c */ 117 #define REG_BB_TX_PATH_SEL_2_8822C 0x940 /* rtl8822c_phy.c */ 118 119 /* TX BeamForming */ 120 #define REG_BB_TXBF_ANT_SET_BF1_8822C 0x19AC /* rtl8822c_phy.c */ 121 #define REG_BB_TXBF_ANT_SET_BF0_8822C 0x19B4 /* rtl8822c_phy.c */ 122 123 #define rCCK0_System 0xA00 124 #define rCCK0_AFESetting 0xA04 125 126 #define rCCK0_DSPParameter2 0xA1C 127 #define rCCK0_TxFilter1 0xA20 128 #define rCCK0_TxFilter2 0xA24 129 #define rCCK0_DebugPort 0xA28 130 #define rCCK0_FalseAlarmReport 0xA2C 131 132 #define rD_TxScale_Jaguar2 0x1A1C /* Path_D TX scaling factor (hal_mp.c) */ 133 #define rD_IGI_Jaguar2 0x1A50 /* Initial Gain for path-D (hal_mp.c) */ 134 135 #define rOFDM0_TRxPathEnable 0xC04 136 #define rOFDM0_TRMuxPar 0xC08 137 #define rA_TxScale_Jaguar 0xC1C /* Pah_A TX scaling factor (hal_mp.c) */ 138 #define rOFDM0_RxDetector1 0xC30 /* rtw_mp.c */ 139 #define rOFDM0_ECCAThreshold 0xC4C /* phydm only */ 140 #define rOFDM0_XAAGCCore1 0xC50 /* phydm only */ 141 #define rA_IGI_Jaguar 0xC50 /* Initial Gain for path-A (hal_mp.c) */ 142 #define rOFDM0_XBAGCCore1 0xC58 /* phydm only */ 143 #define rOFDM0_XATxIQImbalance 0xC80 /* phydm only */ 144 #define rA_LSSIWrite_Jaguar 0xC90 /* RF write addr, LSSI Parameter (rtl8822b_phy.c) */ 145 146 #define rOFDM1_LSTF 0xD00 147 #define rOFDM1_TRxPathEnable 0xD04 /* hal_mp.c */ 148 #define rA_PIRead_Jaguar 0xD04 /* RF readback with PI (rtl8822c_phy.c) */ 149 #define rA_SIRead_Jaguar 0xD08 /* RF readback with SI (rtl8822c_phy.c) */ 150 #define rB_PIRead_Jaguar 0xD44 /* RF readback with PI (rtl8822c_phy.c) */ 151 #define rB_SIRead_Jaguar 0xD48 /* RF readback with SI (rtl8822c_phy.c) */ 152 153 #define rTxAGC_A_Rate18_06 0xE00 154 #define rTxAGC_A_Rate54_24 0xE04 155 #define rTxAGC_A_CCK1_Mcs32 0xE08 156 #define rTxAGC_A_Mcs03_Mcs00 0xE10 157 #define rTxAGC_A_Mcs07_Mcs04 0xE14 158 #define rTxAGC_A_Mcs11_Mcs08 0xE18 159 #define rTxAGC_A_Mcs15_Mcs12 0xE1C 160 #define rB_TxScale_Jaguar 0xE1C /* Path_B TX scaling factor (hal_mp.c) */ 161 #define rB_IGI_Jaguar 0xE50 /* Initial Gain for path-B (hal_mp.c) */ 162 #define rB_LSSIWrite_Jaguar 0xE90 /* RF write addr, LSSI Parameter (rtl8822b_phy.c) */ 163 /* RFE */ 164 #define rA_RFE_Pinmux_Jaguar 0xCB0 /* hal_mp.c */ 165 #define rB_RFE_Pinmux_Jaguar 0xEB0 /* Path_B RFE control pinmux */ 166 #define rA_RFE_Inv_Jaguar 0xCB4 /* Path_A RFE cotrol */ 167 #define rB_RFE_Inv_Jaguar 0xEB4 /* Path_B RFE control */ 168 #define rA_RFE_Jaguar 0xCB8 /* Path_A RFE cotrol */ 169 #define rB_RFE_Jaguar 0xEB8 /* Path_B RFE control */ 170 #define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */ 171 #define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */ 172 #define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */ 173 #define bMask_RFEInv_Jaguar 0x3FF00000 174 #define bMask_AntselPathFollow_Jaguar 0x00030000 175 176 #define rC_RFE_Pinmux_Jaguar 0x18B4 /* Path_C RFE cotrol pinmux*/ 177 #define rD_RFE_Pinmux_Jaguar 0x1AB4 /* Path_D RFE cotrol pinmux*/ 178 #define rA_RFE_Sel_Jaguar2 0x1990 179 180 /* Page1(0x100) */ 181 #define bBBResetB 0x100 182 183 /* Page8(0x800) */ 184 #define bCCKEn 0x1000000 185 #define bOFDMEn 0x2000000 186 /* Reg 0x80C rFPGA0_TxGainStage */ 187 #define bXBTxAGC 0xF00 188 #define bXCTxAGC 0xF000 189 #define bXDTxAGC 0xF0000 190 191 /* PageA(0xA00) */ 192 #define bCCKBBMode 0x3 193 194 #define bCCKScramble 0x8 195 #define bCCKTxRate 0x3000 196 197 /* General */ 198 #define bMaskByte0 0xFF /* mp, rtw_odm.c & phydm */ 199 #define bMaskByte1 0xFF00 /* hal_mp.c & phydm */ 200 #define bMaskByte2 0xFF0000 /* hal_mp.c & phydm */ 201 #define bMaskByte3 0xFF000000 /* hal_mp.c & phydm */ 202 #define bMaskHWord 0xFFFF0000 /* hal_com.c, rtw_mp.c */ 203 #define bMaskLWord 0x0000FFFF /* mp, hal_com.c & phydm */ 204 #define bMaskDWord 0xFFFFFFFF /* mp, hal, rtw_odm.c & phydm */ 205 206 #define bEnable 0x1 /* hal_mp.c, rtw_mp.c */ 207 #define bDisable 0x0 /* rtw_mp.c */ 208 209 #define MAX_STALL_TIME 50 /* unit: us, hal_com_phycfg.c */ 210 211 #define Rx_Smooth_Factor 20 /* phydm only */ 212 213 /* 214 * RF Register definition 215 */ 216 #define RF_AC 0x00 217 #define RF_AC_Jaguar 0x00 /* hal_mp.c */ 218 #define RF_CHNLBW 0x18 /* rtl8822c_phy.c */ 219 #define RF_ModeTableAddr 0x30 /* rtl8822c_phy.c */ 220 #define RF_ModeTableData0 0x31 /* rtl8822c_phy.c */ 221 #define RF_ModeTableData1 0x32 /* rtl8822c_phy.c */ 222 #define RF_0x52 0x52 223 #define RF_WeLut_Jaguar 0xEF /* rtl8822c_phy.c */ 224 225 /* rtw_lps_state_chk()@hal_com.c */ 226 #define BIT_PWRBIT_OW_EN BIT_WMAC_TCRPWRMGT_HWDATA_EN_8822C 227 228 /* General Functions */ 229 void rtl8822c_init_hal_spec(PADAPTER); /* hal/hal_com.c */ 230 231 #ifdef CONFIG_MP_INCLUDED 232 /* MP Functions */ 233 #include <rtw_mp.h> /* struct mp_priv */ 234 void rtl8822c_prepare_mp_txdesc(PADAPTER, struct mp_priv *); /* rtw_mp.c */ 235 void rtl8822c_mp_config_rfpath(PADAPTER); /* hal_mp.c */ 236 #endif 237 void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus); 238 239 #ifdef CONFIG_USB_HCI 240 #include <rtl8822cu_hal.h> 241 #elif defined(CONFIG_SDIO_HCI) 242 #include <rtl8822cs_hal.h> 243 #elif defined(CONFIG_PCI_HCI) 244 #include <rtl8822ce_hal.h> 245 #endif 246 247 #endif /* _RTL8822C_HAL_H_ */ 248