1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2013 - 2017 Realtek Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 *****************************************************************************/ 16 #ifndef __RTL8821A_SPEC_H__ 17 #define __RTL8821A_SPEC_H__ 18 19 #include <drv_conf.h> 20 /* This file should based on "hal_com_reg.h" */ 21 #include <hal_com_reg.h> 22 /* Because 8812a and 8821a is the same serial, 23 * most of 8821a register definitions are the same as 8812a. */ 24 #include <rtl8812a_spec.h> 25 26 27 /* ************************************************************ 28 * 8821A Regsiter offset definition 29 * ************************************************************ */ 30 31 /* ************************************************************ 32 * MAC register 33 * ************************************************************ */ 34 35 /* ----------------------------------------------------- 36 * 0x0000h ~ 0x00FFh System Configuration 37 * ----------------------------------------------------- */ 38 39 /* ----------------------------------------------------- 40 * 0x0100h ~ 0x01FFh MACTOP General Configuration 41 * ----------------------------------------------------- */ 42 #define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN 43 44 /* ----------------------------------------------------- 45 * 0x0200h ~ 0x027Fh TXDMA Configuration 46 * ----------------------------------------------------- */ 47 48 /* ----------------------------------------------------- 49 * 0x0280h ~ 0x02FFh RXDMA Configuration 50 * ----------------------------------------------------- */ 51 52 /* ----------------------------------------------------- 53 * 0x0300h ~ 0x03FFh PCIe 54 * ----------------------------------------------------- */ 55 56 /* ----------------------------------------------------- 57 * 0x0400h ~ 0x047Fh Protocol Configuration 58 * ----------------------------------------------------- */ 59 60 /* ----------------------------------------------------- 61 * 0x0500h ~ 0x05FFh EDCA Configuration 62 * ----------------------------------------------------- */ 63 64 /* ----------------------------------------------------- 65 * 0x0600h ~ 0x07FFh WMAC Configuration 66 * ----------------------------------------------------- */ 67 68 69 /* ************************************************************ 70 * SDIO Bus Specification 71 * ************************************************************ */ 72 73 /* ----------------------------------------------------- 74 * SDIO CMD Address Mapping 75 * ----------------------------------------------------- */ 76 77 /* ----------------------------------------------------- 78 * I/O bus domain (Host) 79 * ----------------------------------------------------- */ 80 81 /* ----------------------------------------------------- 82 * SDIO register 83 * ----------------------------------------------------- */ 84 #define SDIO_REG_FREE_TXPG2 0x024 85 #define SDIO_REG_HCPWM1_8821A 0x025 86 87 /* ************************************************************ 88 * Regsiter Bit and Content definition 89 * ************************************************************ */ 90 91 #endif /* __RTL8821A_SPEC_H__ */ 92