1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2017 Realtek Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 *****************************************************************************/ 16 #ifndef __RTL8192F_XMIT_H__ 17 #define __RTL8192F_XMIT_H__ 18 19 20 #define MAX_TID (15) 21 22 23 #ifndef __INC_HAL8192FDESC_H 24 #define __INC_HAL8192FDESC_H 25 26 #define RX_STATUS_DESC_SIZE_8192F 24 27 #define RX_DRV_INFO_SIZE_UNIT_8192F 8 28 29 30 /* DWORD 0 */ 31 #define SET_RX_STATUS_DESC_PKT_LEN_8192F(__pRxStatusDesc, __Value) \ 32 SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value) 33 #define SET_RX_STATUS_DESC_EOR_8192F(__pRxStatusDesc, __Value) \ 34 SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value) 35 #define SET_RX_STATUS_DESC_OWN_8192F(__pRxStatusDesc, __Value) \ 36 SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value) 37 38 #define GET_RX_STATUS_DESC_PKT_LEN_8192F(__pRxStatusDesc) \ 39 LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14) 40 #define GET_RX_STATUS_DESC_CRC32_8192F(__pRxStatusDesc) \ 41 LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1) 42 #define GET_RX_STATUS_DESC_ICV_8192F(__pRxStatusDesc) \ 43 LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1) 44 #define GET_RX_STATUS_DESC_DRVINFO_SIZE_8192F(__pRxStatusDesc) \ 45 LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4) 46 #define GET_RX_STATUS_DESC_SECURITY_8192F(__pRxStatusDesc) \ 47 LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3) 48 #define GET_RX_STATUS_DESC_QOS_8192F(__pRxStatusDesc) \ 49 LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1) 50 #define GET_RX_STATUS_DESC_SHIFT_8192F(__pRxStatusDesc) \ 51 LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2) 52 #define GET_RX_STATUS_DESC_PHY_STATUS_8192F(__pRxStatusDesc) \ 53 LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1) 54 #define GET_RX_STATUS_DESC_SWDEC_8192F(__pRxStatusDesc) \ 55 LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1) 56 #define GET_RX_STATUS_DESC_EOR_8192F(__pRxStatusDesc) \ 57 LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1) 58 #define GET_RX_STATUS_DESC_OWN_8192F(__pRxStatusDesc) \ 59 LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1) 60 61 /* DWORD 1 */ 62 #define GET_RX_STATUS_DESC_MACID_8192F(__pRxDesc) \ 63 LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7) 64 #define GET_RX_STATUS_DESC_TID_8192F(__pRxDesc) \ 65 LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4) 66 #define GET_RX_STATUS_DESC_AMSDU_8192F(__pRxDesc) \ 67 LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1) 68 #define GET_RX_STATUS_DESC_RXID_MATCH_8192F(__pRxDesc) \ 69 LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1) 70 #define GET_RX_STATUS_DESC_PAGGR_8192F(__pRxDesc) \ 71 LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1) 72 #define GET_RX_STATUS_DESC_A1_FIT_8192F(__pRxDesc) \ 73 LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4) 74 #define GET_RX_STATUS_DESC_CHKERR_8192F(__pRxDesc) \ 75 LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1) 76 #define GET_RX_STATUS_DESC_IPVER_8192F(__pRxDesc) \ 77 LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1) 78 #define GET_RX_STATUS_DESC_IS_TCPUDP__8192F(__pRxDesc) \ 79 LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1) 80 #define GET_RX_STATUS_DESC_CHK_VLD_8192F(__pRxDesc) \ 81 LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1) 82 #define GET_RX_STATUS_DESC_PAM_8192F(__pRxDesc) \ 83 LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1) 84 #define GET_RX_STATUS_DESC_PWR_8192F(__pRxDesc) \ 85 LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1) 86 #define GET_RX_STATUS_DESC_MORE_DATA_8192F(__pRxDesc) \ 87 LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1) 88 #define GET_RX_STATUS_DESC_MORE_FRAG_8192F(__pRxDesc) \ 89 LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1) 90 #define GET_RX_STATUS_DESC_TYPE_8192F(__pRxDesc) \ 91 LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2) 92 #define GET_RX_STATUS_DESC_MC_8192F(__pRxDesc) \ 93 LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1) 94 #define GET_RX_STATUS_DESC_BC_8192F(__pRxDesc) \ 95 LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1) 96 97 /* DWORD 2 */ 98 #define GET_RX_STATUS_DESC_SEQ_8192F(__pRxStatusDesc) \ 99 LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12) 100 #define GET_RX_STATUS_DESC_FRAG_8192F(__pRxStatusDesc) \ 101 LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4) 102 #define GET_RX_STATUS_DESC_RX_IS_QOS_8192F(__pRxStatusDesc) \ 103 LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1) 104 #define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8192F(__pRxStatusDesc) \ 105 LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6) 106 #define GET_RX_STATUS_DESC_RPT_SEL_8192F(__pRxStatusDesc) \ 107 LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1) 108 #define GET_RX_STATUS_DESC_FCS_OK_8192F(__pRxStatusDesc) \ 109 LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1) 110 111 /* DWORD 3 */ 112 #define GET_RX_STATUS_DESC_RX_RATE_8192F(__pRxStatusDesc) \ 113 LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7) 114 #define GET_RX_STATUS_DESC_HTC_8192F(__pRxStatusDesc) \ 115 LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1) 116 #define GET_RX_STATUS_DESC_EOSP_8192F(__pRxStatusDesc) \ 117 LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1) 118 #define GET_RX_STATUS_DESC_BSSID_FIT_8192F(__pRxStatusDesc) \ 119 LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2) 120 #ifdef CONFIG_USB_RX_AGGREGATION 121 #define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8192F(__pRxStatusDesc) \ 122 LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8) 123 #endif 124 #define GET_RX_STATUS_DESC_PATTERN_MATCH_8192F(__pRxDesc) \ 125 LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1) 126 #define GET_RX_STATUS_DESC_UNICAST_MATCH_8192F(__pRxDesc) \ 127 LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1) 128 #define GET_RX_STATUS_DESC_MAGIC_MATCH_8192F(__pRxDesc) \ 129 LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1) 130 131 /* DWORD 6 */ 132 #define GET_RX_STATUS_DESC_MATCH_ID_8192F(__pRxDesc) \ 133 LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 7) 134 135 /* DWORD 5 */ 136 #define GET_RX_STATUS_DESC_TSFL_8192F(__pRxStatusDesc) \ 137 LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32) 138 139 #define GET_RX_STATUS_DESC_BUFF_ADDR64_8192F(__pRxDesc) \ 140 LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32) 141 142 143 144 /* Dword 0, rsvd: bit26, bit28 */ 145 #define GET_TX_DESC_OWN_8192F(__pTxDesc)\ 146 LE_BITS_TO_4BYTE(__pTxDesc, 31, 1) 147 148 #define SET_TX_DESC_PKT_SIZE_8192F(__pTxDesc, __Value) \ 149 SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value) 150 #define SET_TX_DESC_OFFSET_8192F(__pTxDesc, __Value) \ 151 SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value) 152 #define SET_TX_DESC_BMC_8192F(__pTxDesc, __Value) \ 153 SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value) 154 #define SET_TX_DESC_HTC_8192F(__pTxDesc, __Value) \ 155 SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value) 156 #define SET_TX_DESC_AMSDU_PAD_EN_8192F(__pTxDesc, __Value) \ 157 SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value) 158 #define SET_TX_DESC_NO_ACM_8192F(__pTxDesc, __Value) \ 159 SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value) 160 #define SET_TX_DESC_GF_8192F(__pTxDesc, __Value) \ 161 SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value) 162 163 /* Dword 1 */ 164 #define SET_TX_DESC_MACID_8192F(__pTxDesc, __Value) \ 165 SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value) 166 #define SET_TX_DESC_QUEUE_SEL_8192F(__pTxDesc, __Value) \ 167 SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value) 168 #define SET_TX_DESC_RDG_NAV_EXT_8192F(__pTxDesc, __Value) \ 169 SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value) 170 #define SET_TX_DESC_LSIG_TXOP_EN_8192F(__pTxDesc, __Value) \ 171 SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value) 172 #define SET_TX_DESC_PIFS_8192F(__pTxDesc, __Value) \ 173 SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value) 174 #define SET_TX_DESC_RATE_ID_8192F(__pTxDesc, __Value) \ 175 SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value) 176 #define SET_TX_DESC_EN_DESC_ID_8192F(__pTxDesc, __Value) \ 177 SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value) 178 #define SET_TX_DESC_SEC_TYPE_8192F(__pTxDesc, __Value) \ 179 SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value) 180 #define SET_TX_DESC_PKT_OFFSET_8192F(__pTxDesc, __Value) \ 181 SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value) 182 #define SET_TX_DESC_MORE_DATA_8192F(__pTxDesc, __Value) \ 183 SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value) 184 185 /* Dword 2 ADD HW_DIG*/ 186 #define SET_TX_DESC_PAID_92F(__pTxDesc, __Value) \ 187 SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value) 188 #define SET_TX_DESC_CCA_RTS_8192F(__pTxDesc, __Value) \ 189 SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value) 190 #define SET_TX_DESC_AGG_ENABLE_8192F(__pTxDesc, __Value) \ 191 SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value) 192 #define SET_TX_DESC_RDG_ENABLE_8192F(__pTxDesc, __Value) \ 193 SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value) 194 #define SET_TX_DESC_NULL0_8192F(__pTxDesc, __Value) \ 195 SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value) 196 #define SET_TX_DESC_NULL1_8192F(__pTxDesc, __Value) \ 197 SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value) 198 #define SET_TX_DESC_BK_8192F(__pTxDesc, __Value) \ 199 SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value) 200 #define SET_TX_DESC_MORE_FRAG_8192F(__pTxDesc, __Value) \ 201 SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value) 202 #define SET_TX_DESC_RAW_8192F(__pTxDesc, __Value) \ 203 SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value) 204 #define SET_TX_DESC_CCX_8192F(__pTxDesc, __Value) \ 205 SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value) 206 #define SET_TX_DESC_AMPDU_DENSITY_8192F(__pTxDesc, __Value) \ 207 SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value) 208 #define SET_TX_DESC_BT_INT_8192F(__pTxDesc, __Value) \ 209 SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value) 210 #define SET_TX_DESC_HW_DIG_8192F(__pTxDesc, __Value) \ 211 SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 7, __Value) 212 213 /* Dword 3 */ 214 #define SET_TX_DESC_HWSEQ_SEL_8192F(__pTxDesc, __Value) \ 215 SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value) 216 #define SET_TX_DESC_USE_RATE_8192F(__pTxDesc, __Value) \ 217 SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value) 218 #define SET_TX_DESC_DISABLE_RTS_FB_8192F(__pTxDesc, __Value) \ 219 SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value) 220 #define SET_TX_DESC_DISABLE_FB_8192F(__pTxDesc, __Value) \ 221 SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value) 222 #define SET_TX_DESC_CTS2SELF_8192F(__pTxDesc, __Value) \ 223 SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value) 224 #define SET_TX_DESC_RTS_ENABLE_8192F(__pTxDesc, __Value) \ 225 SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value) 226 #define SET_TX_DESC_HW_RTS_ENABLE_8192F(__pTxDesc, __Value) \ 227 SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value) 228 #define SET_TX_DESC_CHK_EN_92F(__pTxDesc, __Value) \ 229 SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 1, __Value) 230 #define SET_TX_DESC_NAV_USE_HDR_8192F(__pTxDesc, __Value) \ 231 SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value) 232 #define SET_TX_DESC_USE_MAX_LEN_8192F(__pTxDesc, __Value) \ 233 SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value) 234 #define SET_TX_DESC_MAX_AGG_NUM_8192F(__pTxDesc, __Value) \ 235 SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value) 236 #define SET_TX_DESC_NDPA_8192F(__pTxDesc, __Value) \ 237 SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value) 238 #define SET_TX_DESC_AMPDU_MAX_TIME_8192F(__pTxDesc, __Value) \ 239 SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value) 240 241 /* Dword 4 */ 242 #define SET_TX_DESC_TX_RATE_8192F(__pTxDesc, __Value) \ 243 SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value) 244 #define SET_TX_DESC_TX_TRY_RATE_8192F(__pTxDesc, __Value) \ 245 SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value) 246 #define SET_TX_DESC_DATA_RATE_FB_LIMIT_8192F(__pTxDesc, __Value) \ 247 SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value) 248 #define SET_TX_DESC_RTS_RATE_FB_LIMIT_8192F(__pTxDesc, __Value) \ 249 SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value) 250 #define SET_TX_DESC_RETRY_LIMIT_ENABLE_8192F(__pTxDesc, __Value) \ 251 SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value) 252 #define SET_TX_DESC_DATA_RETRY_LIMIT_8192F(__pTxDesc, __Value) \ 253 SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value) 254 #define SET_TX_DESC_RTS_RATE_8192F(__pTxDesc, __Value) \ 255 SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value) 256 #define SET_TX_DESC_PCTS_EN_8192F(__pTxDesc, __Value) \ 257 SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value) 258 #define SET_TX_DESC_PCTS_MASK_IDX_8192F(__pTxDesc, __Value) \ 259 SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value) 260 261 /* Dword 5 */ 262 #define SET_TX_DESC_DATA_SC_8192F(__pTxDesc, __Value) \ 263 SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value) 264 #define SET_TX_DESC_DATA_SHORT_8192F(__pTxDesc, __Value) \ 265 SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value) 266 #define SET_TX_DESC_DATA_BW_8192F(__pTxDesc, __Value) \ 267 SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value) 268 #define SET_TX_DESC_DATA_LDPC_8192F(__pTxDesc, __Value) \ 269 SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value) 270 #define SET_TX_DESC_DATA_STBC_8192F(__pTxDesc, __Value) \ 271 SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value) 272 #define SET_TX_DESC_RTS_STBC_8192F(__pTxDesc, __Value) \ 273 SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value) 274 #define SET_TX_DESC_RTS_SHORT_8192F(__pTxDesc, __Value) \ 275 SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value) 276 #define SET_TX_DESC_RTS_SC_8192F(__pTxDesc, __Value) \ 277 SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value) 278 #define SET_TX_DESC_PORT_ID_8192F(__pTxDesc, __Value) \ 279 SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 21, 1, __Value) 280 #define SET_TX_DESC_DROP_ID_8192F(__pTxDesc, __Value) \ 281 SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 22, 2, __Value) 282 #define SET_TX_DESC_PATH_A_EN_8192F(__pTxDesc, __Value) \ 283 SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 1, __Value) 284 #define SET_TX_DESC_PATH_B_EN_8192F(__pTxDesc, __Value) \ 285 SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 25, 1, __Value) 286 #define SET_TX_DESC_TXPWR_OF_SET_8192F(__pTxDesc, __Value) \ 287 SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value) 288 289 /* Dword 6 */ 290 #define SET_TX_DESC_SW_DEFINE_8192F(__pTxDesc, __Value) \ 291 SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value) 292 #define SET_TX_DESC_MBSSID_8192F(__pTxDesc, __Value) \ 293 SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value) 294 #define SET_TX_DESC_RF_SEL_8192F(__pTxDesc, __Value) \ 295 SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value) 296 297 /* Dword 7 */ 298 #ifdef CONFIG_PCI_HCI 299 #define SET_TX_DESC_TX_BUFFER_SIZE_8192F(__pTxDesc, __Value) \ 300 SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) 301 #endif 302 303 #ifdef CONFIG_USB_HCI 304 #define SET_TX_DESC_TX_DESC_CHECKSUM_8192F(__pTxDesc, __Value) \ 305 SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) 306 #endif 307 308 #ifdef CONFIG_SDIO_HCI 309 #define SET_TX_DESC_TX_TIMESTAMP_8192F(__pTxDesc, __Value) \ 310 SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value) 311 #endif 312 313 #define SET_TX_DESC_USB_TXAGG_NUM_8192F(__pTxDesc, __Value) \ 314 SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) 315 316 /* Dword 8 */ 317 #define SET_TX_DESC_RTS_RC_8192F(__pTxDesc, __Value) \ 318 SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value) 319 #define SET_TX_DESC_BAR_RC_8192F(__pTxDesc, __Value) \ 320 SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value) 321 #define SET_TX_DESC_DATA_RC_8192F(__pTxDesc, __Value) \ 322 SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value) 323 #define SET_TX_DESC_HWSEQ_EN_8192F(__pTxDesc, __Value) \ 324 SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) 325 #define SET_TX_DESC_NEXTHEADPAGE_8192F(__pTxDesc, __Value) \ 326 SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value) 327 #define SET_TX_DESC_TAILPAGE_8192F(__pTxDesc, __Value) \ 328 SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value) 329 330 /* Dword 9 */ 331 #define SET_TX_DESC_PADDING_LEN_8192F(__pTxDesc, __Value) \ 332 SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value) 333 #define SET_TX_DESC_SEQ_8192F(__pTxDesc, __Value) \ 334 SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value) 335 #define SET_TX_DESC_FINAL_DATA_RATE_8192F(__pTxDesc, __Value) \ 336 SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value) 337 338 339 #define SET_EARLYMODE_PKTNUM_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value) 340 #define SET_EARLYMODE_LEN0_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value) 341 #define SET_EARLYMODE_LEN1_1_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value) 342 #define SET_EARLYMODE_LEN1_2_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value) 343 #define SET_EARLYMODE_LEN2_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value) 344 #define SET_EARLYMODE_LEN3_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value) 345 346 347 /*-----------------------------------------------------------------*/ 348 /* RTL8192F TX BUFFER DESC */ 349 /*-----------------------------------------------------------------*/ 350 #ifdef CONFIG_64BIT_DMA 351 #define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu) 352 #define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu) 353 #define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu) 354 #define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu) 355 #else 356 #define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu) 357 #define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu) 358 #define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu) 359 #define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) /* 64 BIT mode only */ 360 #endif 361 /* ********************************************************* */ 362 363 /* 64 bits -- 32 bits */ 364 /* ======= ======= */ 365 /* Dword 0 0 */ 366 #define SET_TX_BUFF_DESC_LEN_0_8192F(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu) 367 #define SET_TX_BUFF_DESC_PSB_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value) 368 #define SET_TX_BUFF_DESC_OWN_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) 369 370 /* Dword 1 1 */ 371 #define SET_TX_BUFF_DESC_ADDR_LOW_0_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value) 372 #define GET_TX_BUFF_DESC_ADDR_LOW_0_8192F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32) 373 /* Dword 2 NA */ 374 #define SET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 0, __Value) 375 #ifdef CONFIG_64BIT_DMA 376 #define GET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32) 377 #else 378 #define GET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc) 0 379 #endif 380 /* Dword 3 NA */ 381 /* RESERVED 0 */ 382 /* Dword 4 2 */ 383 #define SET_TX_BUFF_DESC_LEN_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 1, __Value) 384 #define SET_TX_BUFF_DESC_AMSDU_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 1, __Value) 385 /* Dword 5 3 */ 386 #define SET_TX_BUFF_DESC_ADDR_LOW_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 1, __Value) 387 /* Dword 6 NA */ 388 #define SET_TX_BUFF_DESC_ADDR_HIGH_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 1, __Value) 389 /* Dword 7 NA */ 390 /*RESERVED 0 */ 391 /* Dword 8 4 */ 392 #define SET_TX_BUFF_DESC_LEN_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 2, __Value) 393 #define SET_TX_BUFF_DESC_AMSDU_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 2, __Value) 394 /* Dword 9 5 */ 395 #define SET_TX_BUFF_DESC_ADDR_LOW_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 2, __Value) 396 /* Dword 10 NA */ 397 #define SET_TX_BUFF_DESC_ADDR_HIGH_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 2, __Value) 398 /* Dword 11 NA */ 399 /*RESERVED 0 */ 400 /* Dword 12 6 */ 401 #define SET_TX_BUFF_DESC_LEN_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 3, __Value) 402 #define SET_TX_BUFF_DESC_AMSDU_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 3, __Value) 403 /* Dword 13 7 */ 404 #define SET_TX_BUFF_DESC_ADDR_LOW_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 3, __Value) 405 /* Dword 14 NA */ 406 #define SET_TX_BUFF_DESC_ADDR_HIGH_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 3, __Value) 407 /* Dword 15 NA */ 408 /*RESERVED 0 */ 409 410 411 #endif 412 /* ----------------------------------------------------------- 413 * 414 * Rate 415 * 416 * ----------------------------------------------------------- 417 * CCK Rates, TxHT = 0 */ 418 #define DESC8192F_RATE1M 0x00 419 #define DESC8192F_RATE2M 0x01 420 #define DESC8192F_RATE5_5M 0x02 421 #define DESC8192F_RATE11M 0x03 422 423 /* OFDM Rates, TxHT = 0 */ 424 #define DESC8192F_RATE6M 0x04 425 #define DESC8192F_RATE9M 0x05 426 #define DESC8192F_RATE12M 0x06 427 #define DESC8192F_RATE18M 0x07 428 #define DESC8192F_RATE24M 0x08 429 #define DESC8192F_RATE36M 0x09 430 #define DESC8192F_RATE48M 0x0a 431 #define DESC8192F_RATE54M 0x0b 432 433 /* MCS Rates, TxHT = 1 */ 434 #define DESC8192F_RATEMCS0 0x0c 435 #define DESC8192F_RATEMCS1 0x0d 436 #define DESC8192F_RATEMCS2 0x0e 437 #define DESC8192F_RATEMCS3 0x0f 438 #define DESC8192F_RATEMCS4 0x10 439 #define DESC8192F_RATEMCS5 0x11 440 #define DESC8192F_RATEMCS6 0x12 441 #define DESC8192F_RATEMCS7 0x13 442 #define DESC8192F_RATEMCS8 0x14 443 #define DESC8192F_RATEMCS9 0x15 444 #define DESC8192F_RATEMCS10 0x16 445 #define DESC8192F_RATEMCS11 0x17 446 #define DESC8192F_RATEMCS12 0x18 447 #define DESC8192F_RATEMCS13 0x19 448 #define DESC8192F_RATEMCS14 0x1a 449 #define DESC8192F_RATEMCS15 0x1b 450 #define DESC8192F_RATEVHTSS1MCS0 0x2c 451 #define DESC8192F_RATEVHTSS1MCS1 0x2d 452 #define DESC8192F_RATEVHTSS1MCS2 0x2e 453 #define DESC8192F_RATEVHTSS1MCS3 0x2f 454 #define DESC8192F_RATEVHTSS1MCS4 0x30 455 #define DESC8192F_RATEVHTSS1MCS5 0x31 456 #define DESC8192F_RATEVHTSS1MCS6 0x32 457 #define DESC8192F_RATEVHTSS1MCS7 0x33 458 #define DESC8192F_RATEVHTSS1MCS8 0x34 459 #define DESC8192F_RATEVHTSS1MCS9 0x35 460 #define DESC8192F_RATEVHTSS2MCS0 0x36 461 #define DESC8192F_RATEVHTSS2MCS1 0x37 462 #define DESC8192F_RATEVHTSS2MCS2 0x38 463 #define DESC8192F_RATEVHTSS2MCS3 0x39 464 #define DESC8192F_RATEVHTSS2MCS4 0x3a 465 #define DESC8192F_RATEVHTSS2MCS5 0x3b 466 #define DESC8192F_RATEVHTSS2MCS6 0x3c 467 #define DESC8192F_RATEVHTSS2MCS7 0x3d 468 #define DESC8192F_RATEVHTSS2MCS8 0x3e 469 #define DESC8192F_RATEVHTSS2MCS9 0x3f 470 471 472 #define RX_HAL_IS_CCK_RATE_8192F(pDesc)\ 473 (GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE1M || \ 474 GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE2M || \ 475 GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE5_5M || \ 476 GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE11M) 477 478 #ifdef CONFIG_TRX_BD_ARCH 479 struct tx_desc; 480 #endif 481 482 void rtl8192f_cal_txdesc_chksum(struct tx_desc *ptxdesc); 483 void rtl8192f_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem); 484 void rtl8192f_fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc); 485 void rtl8192f_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc); 486 void rtl8192f_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc); 487 void rtl8192f_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); 488 489 void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); 490 void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc); 491 492 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) 493 s32 rtl8192fs_init_xmit_priv(PADAPTER padapter); 494 void rtl8192fs_free_xmit_priv(PADAPTER padapter); 495 s32 rtl8192fs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); 496 s32 rtl8192fs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); 497 #ifdef CONFIG_RTW_MGMT_QUEUE 498 s32 rtl8192fs_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); 499 #endif 500 s32 rtl8192fs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); 501 s32 rtl8192fs_xmit_buf_handler(PADAPTER padapter); 502 thread_return rtl8192fs_xmit_thread(thread_context context); 503 #define hal_xmit_handler rtl8192fs_xmit_buf_handler 504 #endif 505 506 #ifdef CONFIG_USB_HCI 507 s32 rtl8192fu_init_xmit_priv(PADAPTER padapter); 508 void rtl8192fu_free_xmit_priv(PADAPTER padapter); 509 s32 rtl8192fu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); 510 s32 rtl8192fu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); 511 #ifdef CONFIG_RTW_MGMT_QUEUE 512 s32 rtl8192fu_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); 513 #endif 514 s32 rtl8192fu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); 515 s32 rtl8192fu_xmit_buf_handler(PADAPTER padapter); 516 #define hal_xmit_handler rtl8192fu_xmit_buf_handler 517 void rtl8192fu_xmit_tasklet(void *priv); 518 s32 rtl8192fu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); 519 void _dbg_dump_tx_info(_adapter *padapter,int frame_tag,struct tx_desc *ptxdesc); 520 #endif 521 522 #ifdef CONFIG_PCI_HCI 523 s32 rtl8192fe_init_xmit_priv(PADAPTER padapter); 524 void rtl8192fe_free_xmit_priv(PADAPTER padapter); 525 struct xmit_buf *rtl8192fe_dequeue_xmitbuf(struct rtw_tx_ring *ring); 526 void rtl8192fe_xmitframe_resume(_adapter *padapter); 527 s32 rtl8192fe_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); 528 s32 rtl8192fe_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); 529 #ifdef CONFIG_RTW_MGMT_QUEUE 530 s32 rtl8192fe_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); 531 #endif 532 s32 rtl8192fe_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); 533 void rtl8192fe_xmit_tasklet(void *priv); 534 #endif 535 536 u8 BWMapping_8192F(PADAPTER Adapter, struct pkt_attrib *pattrib); 537 u8 SCMapping_8192F(PADAPTER Adapter, struct pkt_attrib *pattrib); 538 539 #endif 540