1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2017 Realtek Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 *****************************************************************************/ 16 #ifndef __RTL8192F_SPEC_H__ 17 #define __RTL8192F_SPEC_H__ 18 19 #include <drv_conf.h> 20 21 22 #define HAL_NAV_UPPER_UNIT_8192F 128 /* micro-second */ 23 24 /* ----------------------------------------------------- 25 * 26 * 0x0000h ~ 0x00FFh System Configuration 27 * 28 * ----------------------------------------------------- */ 29 #define REG_SYS_ISO_CTRL_8192F 0x0000 /* 2 Byte */ 30 #define REG_SYS_FUNC_EN_8192F 0x0002 /* 2 Byte */ 31 #define REG_APS_FSMCO_8192F 0x0004 /* 4 Byte */ 32 #define REG_SYS_CLKR_8192F 0x0008 /* 2 Byte */ 33 #define REG_9346CR_8192F 0x000A /* 2 Byte */ 34 #define REG_EE_VPD_8192F 0x000C /* 2 Byte */ 35 #define REG_AFE_MISC_8192F 0x0010 /* 1 Byte */ 36 #define REG_SPS0_CTRL_8192F 0x0011 /* 7 Byte */ 37 #define REG_SPS_OCP_CFG_8192F 0x0018 /* 4 Byte */ 38 #define REG_RSV_CTRL_8192F 0x001C /* 3 Byte */ 39 #define REG_RF_CTRL_8192F 0x001F /* 1 Byte */ 40 #define REG_LPLDO_CTRL_8192F 0x0023 /* 1 Byte */ 41 #define REG_AFE_XTAL_CTRL_8192F 0x0024 /* 4 Byte */ 42 #define REG_AFE_PLL_CTRL_8192F 0x0028 /* 4 Byte */ 43 #define REG_MAC_PLL_CTRL_EXT_8192F 0x002c /* 4 Byte */ 44 #define REG_EFUSE_CTRL_8192F 0x0030 45 #define REG_EFUSE_TEST_8192F 0x0034 46 #define REG_PWR_DATA_8192F 0x0038 47 #define REG_CAL_TIMER_8192F 0x003C 48 #define REG_ACLK_MON_8192F 0x003E 49 #define REG_GPIO_MUXCFG_8192F 0x0040 50 #define REG_GPIO_IO_SEL_8192F 0x0042 51 #define REG_MAC_PINMUX_CFG_8192F 0x0043 52 #define REG_GPIO_PIN_CTRL_8192F 0x0044 53 #define REG_GPIO_INTM_8192F 0x0048 54 #define REG_LEDCFG0_8192F 0x004C 55 #define REG_LEDCFG1_8192F 0x004D 56 #define REG_LEDCFG2_8192F 0x004E 57 #define REG_LEDCFG3_8192F 0x004F 58 #define REG_FSIMR_8192F 0x0050 59 #define REG_FSISR_8192F 0x0054 60 #define REG_HSIMR_8192F 0x0058 61 #define REG_HSISR_8192F 0x005c 62 #define REG_GPIO_EXT_CTRL 0x0060 63 #define REG_PAD_CTRL1_8192F 0x0064 64 #define REG_MULTI_FUNC_CTRL_8192F 0x0068 65 #define REG_GPIO_STATUS_8192F 0x006C 66 #define REG_SDIO_CTRL_8192F 0x0070 67 #define REG_OPT_CTRL_8192F 0x0074 68 #define REG_AFE_CTRL_4_8192F 0x0078 69 #define REG_MCUFWDL_8192F 0x0080 70 #define REG_8051FW_CTRL_8192F 0x0080 71 #define REG_HMEBOX_DBG_0_8192F 0x0088 72 #define REG_HMEBOX_DBG_1_8192F 0x008A 73 #define REG_HMEBOX_DBG_2_8192F 0x008C 74 #define REG_HMEBOX_DBG_3_8192F 0x008E 75 #define REG_WLLPS_CTRL 0x0090 76 #define REG_HIMR0_8192F 0x00B0 77 #define REG_HISR0_8192F 0x00B4 78 #define REG_HIMR1_8192F 0x00B8 79 #define REG_HISR1_8192F 0x00BC 80 #define REG_PMC_DBG_CTRL2_8192F 0x00CC 81 #define REG_EFUSE_BURN_GNT_8192F 0x00CF 82 #define REG_HPON_FSM_8192F 0x00EC 83 #define REG_SYS_CFG1_8192F 0x00F0 84 #define REG_SYS_CFG2_8192F 0x00FC 85 #define REG_ROM_VERSION 0x00FD 86 87 /* ----------------------------------------------------- 88 * 89 * 0x0100h ~ 0x01FFh MACTOP General Configuration 90 * 91 * ----------------------------------------------------- */ 92 #define REG_CR_8192F 0x0100 93 #define REG_PBP_8192F 0x0104 94 #define REG_PKT_BUFF_ACCESS_CTRL_8192F 0x0106 95 #define REG_TRXDMA_CTRL_8192F 0x010C 96 #define REG_TRXFF_BNDY_8192F 0x0114 97 #define REG_TRXFF_STATUS_8192F 0x0118 98 #define REG_RXFF_PTR_8192F 0x011C 99 #define REG_CPWM_8192F 0x012C 100 #define REG_FWIMR_8192F 0x0130 101 #define REG_FWISR_8192F 0x0134 102 #define REG_FTIMR_8192F 0x0138 103 #define REG_PKTBUF_DBG_CTRL_8192F 0x0140 104 #define REG_RXPKTBUF_CTRL_8192F 0x0142 105 #define REG_PKTBUF_DBG_DATA_L_8192F 0x0144 106 #define REG_PKTBUF_DBG_DATA_H_8192F 0x0148 107 108 #define REG_TC0_CTRL_8192F 0x0150 109 #define REG_TC1_CTRL_8192F 0x0154 110 #define REG_TC2_CTRL_8192F 0x0158 111 #define REG_TC3_CTRL_8192F 0x015C 112 #define REG_TC4_CTRL_8192F 0x0160 113 #define REG_TCUNIT_BASE_8192F 0x0164 114 #define REG_RSVD3_8192F 0x0168 115 #define REG_C2HEVT_CMD_ID_8192F 0x01A0 116 #define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 117 #define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 118 #define REG_C2HEVT_CMD_LEN_8192F 0x01AE 119 #define REG_C2HEVT_CLEAR_8192F 0x01AF 120 #define REG_TXBUF_WKCAM_OFFSET 0x01B1 /* RTL8192F */ 121 #define REG_MCUTST_1_8192F 0x01C0 122 #define REG_WOWLAN_WAKE_REASON 0x01C7 123 #define REG_FMETHR_8192F 0x01C8 124 #define REG_HMETFR_8192F 0x01CC 125 #define REG_HMEBOX_0_8192F 0x01D0 126 #define REG_HMEBOX_1_8192F 0x01D4 127 #define REG_HMEBOX_2_8192F 0x01D8 128 #define REG_HMEBOX_3_8192F 0x01DC 129 #define REG_LLT_INIT_8192F 0x01E0 130 #define REG_HMEBOX_EXT0_8192F 0x01F0 131 #define REG_HMEBOX_EXT1_8192F 0x01F4 132 #define REG_HMEBOX_EXT2_8192F 0x01F8 133 #define REG_HMEBOX_EXT3_8192F 0x01FC 134 135 /* ----------------------------------------------------- 136 * 137 * 0x0200h ~ 0x027Fh TXDMA Configuration 138 * 139 * ----------------------------------------------------- */ 140 #define REG_RQPN_8192F 0x0200 141 #define REG_FIFOPAGE_8192F 0x0204 142 #define REG_DWBCN0_CTRL_8192F REG_TDECTRL 143 #define REG_TXDMA_OFFSET_CHK_8192F 0x020C 144 #define REG_TXDMA_STATUS_8192F 0x0210 145 #define REG_RQPN_NPQ_8192F 0x0214 146 #define REG_DWBCN1_CTRL_8192F 0x0228 147 #define REG_RQPN_EXQ1_EXQ2 0x0230 148 #define REG_TQPNT3_V1_8192F 0x0234 149 150 /* ----------------------------------------------------- 151 * 152 * 0x0280h ~ 0x02FFh RXDMA Configuration 153 * 154 * ----------------------------------------------------- */ 155 #define REG_RXDMA_AGG_PG_TH_8192F 0x0280 156 #define REG_FW_UPD_RDPTR_8192F 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */ 157 #define REG_RXDMA_CONTROL_8192F 0x0286 /* Control the RX DMA. */ 158 #define REG_RXDMA_STATUS_8192F 0x0288 159 #define REG_RXDMA_MODE_CTRL_8192F 0x0290 160 #define REG_EARLY_MODE_CONTROL_8192F 0x02BC 161 #define REG_RSVD5_8192F 0x02F0 162 #define REG_RSVD6_8192F 0x02F4 163 164 /* ----------------------------------------------------- 165 * 166 * 0x0300h ~ 0x03FFh PCIe 167 * 168 * ----------------------------------------------------- */ 169 #define REG_PCIE_CTRL_REG_8192F 0x0300 170 #define REG_INT_MIG_8192F 0x0304 /* Interrupt Migration */ 171 #define REG_BCNQ_TXBD_DESA_8192F 0x0308 /* TX Beacon Descriptor Address */ 172 #define REG_MGQ_TXBD_DESA_8192F 0x0310 /* TX Manage Queue Descriptor Address */ 173 #define REG_VOQ_TXBD_DESA_8192F 0x0318 /* TX VO Queue Descriptor Address */ 174 #define REG_VIQ_TXBD_DESA_8192F 0x0320 /* TX VI Queue Descriptor Address */ 175 #define REG_BEQ_TXBD_DESA_8192F 0x0328 /* TX BE Queue Descriptor Address */ 176 #define REG_BKQ_TXBD_DESA_8192F 0x0330 /* TX BK Queue Descriptor Address */ 177 #define REG_RXQ_RXBD_DESA_8192F 0x0338 /* RX Queue Descriptor Address */ 178 #define REG_HI0Q_TXBD_DESA_8192F 0x0340 179 #define REG_HI1Q_TXBD_DESA_8192F 0x0348 180 #define REG_HI2Q_TXBD_DESA_8192F 0x0350 181 #define REG_HI3Q_TXBD_DESA_8192F 0x0358 182 #define REG_HI4Q_TXBD_DESA_8192F 0x0360 183 #define REG_HI5Q_TXBD_DESA_8192F 0x0368 184 #define REG_HI6Q_TXBD_DESA_8192F 0x0370 185 #define REG_HI7Q_TXBD_DESA_8192F 0x0378 186 #define REG_MGQ_TXBD_NUM_8192F 0x0380 187 #define REG_RX_RXBD_NUM_8192F 0x0382 188 #define REG_VOQ_TXBD_NUM_8192F 0x0384 189 #define REG_VIQ_TXBD_NUM_8192F 0x0386 190 #define REG_BEQ_TXBD_NUM_8192F 0x0388 191 #define REG_BKQ_TXBD_NUM_8192F 0x038A 192 #define REG_HI0Q_TXBD_NUM_8192F 0x038C 193 #define REG_HI1Q_TXBD_NUM_8192F 0x038E 194 #define REG_HI2Q_TXBD_NUM_8192F 0x0390 195 #define REG_HI3Q_TXBD_NUM_8192F 0x0392 196 #define REG_HI4Q_TXBD_NUM_8192F 0x0394 197 #define REG_HI5Q_TXBD_NUM_8192F 0x0396 198 #define REG_HI6Q_TXBD_NUM_8192F 0x0398 199 #define REG_HI7Q_TXBD_NUM_8192F 0x039A 200 #define REG_TSFTIMER_HCI_8192F 0x039C 201 #define REG_BD_RW_PTR_CLR_8192F 0x039C 202 203 /* Read Write Point */ 204 #define REG_VOQ_TXBD_IDX_8192F 0x03A0 205 #define REG_VIQ_TXBD_IDX_8192F 0x03A4 206 #define REG_BEQ_TXBD_IDX_8192F 0x03A8 207 #define REG_BKQ_TXBD_IDX_8192F 0x03AC 208 #define REG_MGQ_TXBD_IDX_8192F 0x03B0 209 #define REG_RXQ_TXBD_IDX_8192F 0x03B4 210 #define REG_HI0Q_TXBD_IDX_8192F 0x03B8 211 #define REG_HI1Q_TXBD_IDX_8192F 0x03BC 212 #define REG_HI2Q_TXBD_IDX_8192F 0x03C0 213 #define REG_HI3Q_TXBD_IDX_8192F 0x03C4 214 #define REG_HI4Q_TXBD_IDX_8192F 0x03C8 215 #define REG_HI5Q_TXBD_IDX_8192F 0x03CC 216 #define REG_HI6Q_TXBD_IDX_8192F 0x03D0 217 #define REG_HI7Q_TXBD_IDX_8192F 0x03D4 218 #define REG_DBI_WDATA_V1_8192F 0x03E8 219 #define REG_DBI_RDATA_V1_8192F 0x03EC 220 #define REG_DBI_FLAG_V1_8192F 0x03F0 221 #define REG_MDIO_V1_8192F 0x03F4 222 #define REG_HCI_MIX_CFG_8192F 0x03FC 223 #define REG_PCIE_HCPWM_8192FE 0x03D8 224 #define REG_PCIE_HRPWM_8192FE 0x03DC 225 #define REG_PCIE_MIX_CFG_8192F 0x03F8 226 227 /* ----------------------------------------------------- 228 * 229 * 0x0400h ~ 0x047Fh Protocol Configuration 230 * 231 * ----------------------------------------------------- */ 232 #define REG_QUEUELIST_INFO0_8192F 0x0400 233 #define REG_QUEUELIST_INFO1_8192F 0x0404 234 #define REG_QUEUELIST_INFO2_8192F 0x0414 235 #define REG_TXPKT_EMPTY_8192F 0x0418 236 237 #define REG_FWHW_TXQ_CTRL_8192F 0x0420 238 #define REG_HWSEQ_CTRL_8192F 0x0423 239 #define REG_TXPKTBUF_BCNQ_BDNY_8192F 0x0424 240 #define REG_TXPKTBUF_MGQ_BDNY_8192F 0x0425 241 #define REG_LIFECTRL_CTRL_8192F 0x0426 242 #define REG_MULTI_BCNQ_OFFSET_8192F 0x0427 243 #define REG_SPEC_SIFS_8192F 0x0428 244 #define REG_RL_8192F 0x042A 245 #define REG_TXBF_CTRL_8192F 0x042C 246 #define REG_DARFRC_8192F 0x0430 247 #define REG_RARFRC_8192F 0x0438 248 #define REG_RRSR_8192F 0x0440 249 #define REG_ARFR0_8192F 0x0444 250 #define REG_ARFR1_8192F 0x044C 251 #define REG_CCK_CHECK_8192F 0x0454 252 #define REG_AMPDU_MAX_TIME_8192F 0x0456 253 #define REG_TXPKTBUF_BCNQ_BDNY1_8192F 0x0457 254 255 #define REG_AMPDU_MAX_LENGTH_8192F 0x0458 256 #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8192F 0x045D 257 #define REG_NDPA_OPT_CTRL_8192F 0x045F 258 #define REG_FAST_EDCA_CTRL_8192F 0x0460 259 #define REG_RD_RESP_PKT_TH_8192F 0x0463 260 #define REG_DATA_SC_8192F 0x0483 261 #define REG_TXRPT_START_OFFSET 0x04AC 262 #define REG_POWER_STAGE1_8192F 0x04B4 263 #define REG_POWER_STAGE2_8192F 0x04B8 264 #define REG_AMPDU_BURST_MODE_8192F 0x04BC 265 #define REG_PKT_VO_VI_LIFE_TIME_8192F 0x04C0 266 #define REG_PKT_BE_BK_LIFE_TIME_8192F 0x04C2 267 #define REG_STBC_SETTING_8192F 0x04C4 268 #define REG_HT_SINGLE_AMPDU_8192F 0x04C7 269 #define REG_PROT_MODE_CTRL_8192F 0x04C8 270 #define REG_MAX_AGGR_NUM_8192F 0x04CA 271 #define REG_RTS_MAX_AGGR_NUM_8192F 0x04CB 272 #define REG_BAR_MODE_CTRL_8192F 0x04CC 273 #define REG_RA_TRY_RATE_AGG_LMT_8192F 0x04CF 274 #define REG_MACID_PKT_DROP0_8192F 0x04D0 275 #define REG_MACID_PKT_SLEEP_8192F 0x04D4 276 #define REG_PRECNT_CTRL_8192F 0x04E5 277 /* ----------------------------------------------------- 278 * 279 * 0x0500h ~ 0x05FFh EDCA Configuration 280 * 281 * ----------------------------------------------------- */ 282 #define REG_EDCA_VO_PARAM_8192F 0x0500 283 #define REG_EDCA_VI_PARAM_8192F 0x0504 284 #define REG_EDCA_BE_PARAM_8192F 0x0508 285 #define REG_EDCA_BK_PARAM_8192F 0x050C 286 #define REG_BCNTCFG_8192F 0x0510 287 #define REG_PIFS_8192F 0x0512 288 #define REG_RDG_PIFS_8192F 0x0513 289 #define REG_SIFS_CTX_8192F 0x0514 290 #define REG_SIFS_TRX_8192F 0x0516 291 #define REG_AGGR_BREAK_TIME_8192F 0x051A 292 #define REG_SLOT_8192F 0x051B 293 #define REG_TX_PTCL_CTRL_8192F 0x0520 294 #define REG_TXPAUSE_8192F 0x0522 295 #define REG_DIS_TXREQ_CLR_8192F 0x0523 296 #define REG_RD_CTRL_8192F 0x0524 297 /* 298 * Format for offset 540h-542h: 299 * [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. 300 * [7:4]: Reserved. 301 * [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. 302 * [23:20]: Reserved 303 * Description: 304 * | 305 * |<--Setup--|--Hold------------>| 306 * --------------|---------------------- 307 * | 308 * TBTT 309 * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. 310 * Described by Designer Tim and Bruce, 2011-01-14. 311 * */ 312 #define REG_TBTT_PROHIBIT_8192F 0x0540 313 #define REG_RD_NAV_NXT_8192F 0x0544 314 #define REG_NAV_PROT_LEN_8192F 0x0546 315 #define REG_BCN_CTRL_8192F 0x0550 316 #define REG_BCN_CTRL_1_8192F 0x0551 317 #define REG_MBID_NUM_8192F 0x0552 318 #define REG_DUAL_TSF_RST_8192F 0x0553 319 #define REG_BCN_INTERVAL_8192F 0x0554 320 #define REG_DRVERLYINT_8192F 0x0558 321 #define REG_BCNDMATIM_8192F 0x0559 322 #define REG_ATIMWND_8192F 0x055A 323 #define REG_USTIME_TSF_8192F 0x055C 324 #define REG_BCN_MAX_ERR_8192F 0x055D 325 #define REG_RXTSF_OFFSET_CCK_8192F 0x055E 326 #define REG_RXTSF_OFFSET_OFDM_8192F 0x055F 327 #define REG_TSFTR_8192F 0x0560 328 #define REG_CTWND_8192F 0x0572 329 #define REG_SECONDARY_CCA_CTRL_8192F 0x0577 330 #define REG_PSTIMER_8192F 0x0580 331 #define REG_TIMER0_8192F 0x0584 332 #define REG_TIMER1_8192F 0x0588 333 #define REG_ACMHWCTRL_8192F 0x05C0 334 #define REG_SCH_TXCMD_8192F 0x05F8 335 336 /* ----------------------------------------------------- 337 * 338 * 0x0600h ~ 0x07FFh WMAC Configuration 339 * 340 * ----------------------------------------------------- */ 341 #define REG_MAC_CR_8192F 0x0600 342 #define REG_TCR_8192F 0x0604 343 #define REG_RCR_8192F 0x0608 344 #define REG_RX_PKT_LIMIT_8192F 0x060C 345 #define REG_RX_DLK_TIME_8192F 0x060D 346 #define REG_RX_DRVINFO_SZ_8192F 0x060F 347 348 #define REG_MACID_8192F 0x0610 349 #define REG_BSSID_8192F 0x0618 350 #define REG_MAR_8192F 0x0620 351 #define REG_MBIDCAMCFG_8192F 0x0628 352 353 354 #define REG_USTIME_EDCA_8192F 0x0638 355 #define REG_MAC_SPEC_SIFS_8192F 0x063A 356 #define REG_RESP_SIFP_CCK_8192F 0x063C 357 #define REG_RESP_SIFS_OFDM_8192F 0x063E 358 #define REG_ACKTO_8192F 0x0640 359 #define REG_CTS2TO_8192F 0x0641 360 #define REG_EIFS_8192F 0x0642 361 362 #define REG_NAV_UPPER_8192F 0x0652 /* unit of 128*/ 363 #define REG_TRXPTCL_CTL_8192F 0x0668 364 365 /* Security*/ 366 #define REG_CAMCMD_8192F 0x0670 367 #define REG_CAMWRITE_8192F 0x0674 368 #define REG_CAMREAD_8192F 0x0678 369 #define REG_CAMDBG_8192F 0x067C 370 #define REG_SECCFG_8192F 0x0680 371 372 /* Power */ 373 #define REG_WOW_CTRL_8192F 0x0690 374 #define REG_PS_RX_INFO_8192F 0x0692 375 #define REG_UAPSD_TID_8192F 0x0693 376 #define REG_WKFMCAM_CMD_8192F 0x0698 377 #define REG_WKFMCAM_NUM_8192F 0x0698 378 #define REG_WKFMCAM_RWD_8192F 0x069C 379 #define REG_RXFLTMAP0_8192F 0x06A0 380 #define REG_RXFLTMAP1_8192F 0x06A2 381 #define REG_RXFLTMAP2_8192F 0x06A4 382 #define REG_BCN_PSR_RPT_8192F 0x06A8 383 #define REG_BT_COEX_TABLE_8192F 0x06C0 384 #define REG_BFMER0_INFO_8192F 0x06E4 385 #define REG_BFMER1_INFO_8192F 0x06EC 386 #define REG_CSI_RPT_PARAM_BW20_8192F 0x06F4 387 #define REG_CSI_RPT_PARAM_BW40_8192F 0x06F8 388 #define REG_CSI_RPT_PARAM_BW80_8192F 0x06FC 389 390 /* Hardware Port 2 */ 391 #define REG_MACID1_8192F 0x0700 392 #define REG_BSSID1_8192F 0x0708 393 #define REG_BFMEE_SEL_8192F 0x0714 394 #define REG_SND_PTCL_CTRL_8192F 0x0718 395 396 /* LTR */ 397 #define REG_LTR_CTRL_BASIC_8192F 0x07A4 398 #define REG_LTR_IDLE_LATENCY_V1_8192F 0x0798 399 #define REG_LTR_ACTIVE_LATENCY_V1_8192F 0x079C 400 401 /* GPIO Control */ 402 #define REG_SW_GPIO_SHARE_CTRL_8192F_0 0x1038 403 #define REG_SW_GPIO_SHARE_CTRL_8192F_1 0x103c 404 #define REG_SW_GPIO_A_OUT_8192F 0x1040 405 #define REG_SW_GPIO_A_OEN_8192F 0x1044 406 407 /* ************************************************************ 408 * SDIO Bus Specification 409 * ************************************************************ */ 410 411 /* ----------------------------------------------------- 412 * SDIO CMD Address Mapping 413 * ----------------------------------------------------- */ 414 415 /* ----------------------------------------------------- 416 * I/O bus domain (Host) 417 * ----------------------------------------------------- */ 418 /*SDIO Host Interrupt Mask Register */ 419 #define SDIO_HIMR_CRCERR_MSK BIT(31) 420 /* SDIO Host Interrupt Service Routine */ 421 #define SDIO_HISR_HEISR_IND_INT BIT(28) 422 #define SDIO_HISR_HSISR2_IND_INT BIT(29) 423 #define SDIO_HISR_HSISR3_IND_INT BIT(30) 424 #define SDIO_HISR_SDIO_CRCERR BIT(31) 425 /* ----------------------------------------------------- 426 * SDIO register 427 * ----------------------------------------------------- */ 428 #define SDIO_REG_HCPWM1_8192F 0x038/* HCI Current Power Mode 1 */ 429 #define SDIO_REG_FREE_TXPG1_8192F 0x0020 /* Free Tx Buffer Page1*/ 430 #define SDIO_REG_FREE_TXPG2_8192F 0x0024 /* Free Tx Buffer Page1*/ 431 #define SDIO_REG_FREE_TXPG3_8192F 0x0028 432 #define SDIO_REG_AC_OQT_FREEPG_8192F 0x002A 433 #define SDIO_REG_NOAC_OQT_FREEPG_8192F 0x002B 434 /* **************************************************************************** 435 * 8192F Regsiter Bit and Content definition 436 * **************************************************************************** */ 437 438 #define BIT_USB_RXDMA_AGG_EN BIT(31) 439 #define RXDMA_AGG_MODE_EN BIT(1) 440 441 #ifdef CONFIG_WOWLAN 442 #define RXPKT_RELEASE_POLL BIT(16) 443 #define RXDMA_IDLE BIT(17) 444 #define RW_RELEASE_EN BIT(18) 445 #endif 446 447 #ifdef CONFIG_AMPDU_PRETX_CD 448 /*#define BIT_ERRORHDL_INT BIT(2)*/ 449 /*#define BIT_MACTX_ERR_3 BIT(4)*/ 450 #define BIT_PRE_TX_CMD_8192F BIT(6) 451 #define BIT_EN_PRECNT_8192F BIT(11) 452 #endif 453 /* SDIO Host Interrupt Service Routine */ 454 #define SDIO_HISR_HEISR_IND_INT BIT(28) 455 #define SDIO_HISR_HSISR2_IND_INT BIT(29) 456 #define SDIO_HISR_HSISR3_IND_INT BIT(30) 457 #define SDIO_HISR_SDIO_CRCERR BIT(31) 458 459 /* PCIE Host Interrupt Mask Register (HIMR) */ 460 #ifdef CONFIG_PCI_HCI 461 /* ---------------------------------------------------------------------------- 462 * * 8192F IMR/ISR bits (offset 0xB0, 8bits) 463 * * ---------------------------------------------------------------------------- */ 464 465 #define IMR_DISABLED_8192F 0 466 /* IMR DW0(0x00B0-00B3) Bit 0-31 */ 467 #define IMR_TIMER2_8192F BIT(31) /* Timeout interrupt 2 */ 468 #define IMR_TIMER1_8192F BIT(30) /* Timeout interrupt 1 */ 469 #define IMR_PSTIMEOUT_8192F BIT(29) /* Power Save Time Out Interrupt */ 470 #define IMR_GTINT4_8192F BIT(28) /* When GTIMER4 expires, this bit is set to 1 */ 471 #define IMR_GTINT3_8192F BIT(27) /* When GTIMER3 expires, this bit is set to 1 */ 472 #define IMR_TXBCN0ERR_8192F BIT(26) /* Transmit Beacon0 Error */ 473 #define IMR_TXBCN0OK_8192F BIT(25) /* Transmit Beacon0 OK */ 474 #define IMR_TSF_BIT32_TOGGLE_8192F BIT(24) /* TSF Timer BIT32 toggle indication interrupt */ 475 #define IMR_BCNDMAINT0_8192F BIT(20) /* Beacon DMA Interrupt 0 */ 476 #define IMR_BCNDERR0_8192F BIT(16) /* Beacon Queue DMA OK0 */ 477 #define IMR_HSISR_IND_ON_INT_8192F BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ 478 #define IMR_BCNDMAINT_E_8192F BIT(14) /* Beacon DMA Interrupt Extension for Win7 */ 479 #define IMR_ATIMEND_8192F BIT(12) /* CTWidnow End or ATIM Window End */ 480 #define IMR_C2HCMD_8192F BIT(10) /* CPU to Host Command INT status, Write 1 clear */ 481 #define IMR_CPWM2_8192F BIT(9) /* CPU power mode exchange INT status, Write 1 clear */ 482 #define IMR_CPWM_8192F BIT(8) /* CPU power mode exchange INT status, Write 1 clear */ 483 #define IMR_HIGHDOK_8192F BIT(7) /* High Queue DMA OK */ 484 #define IMR_MGNTDOK_8192F BIT(6) /* Management Queue DMA OK */ 485 #define IMR_BKDOK_8192F BIT(5) /* AC_BK DMA OK */ 486 #define IMR_BEDOK_8192F BIT(4) /* AC_BE DMA OK */ 487 #define IMR_VIDOK_8192F BIT(3) /* AC_VI DMA OK */ 488 #define IMR_VODOK_8192F BIT(2) /* AC_VO DMA OK */ 489 #define IMR_RDU_8192F BIT(1) /* Rx Descriptor Unavailable */ 490 #define IMR_ROK_8192F BIT(0) /* Receive DMA OK */ 491 492 /* IMR DW1(0x00B4-00B7) Bit 0-31 */ 493 #define IMR_MCUERR_8192F BIT(28) 494 #define IMR_BCNDMAINT7_8192F BIT(27) /* Beacon DMA Interrupt 7 */ 495 #define IMR_BCNDMAINT6_8192F BIT(26) /* Beacon DMA Interrupt 6 */ 496 #define IMR_BCNDMAINT5_8192F BIT(25) /* Beacon DMA Interrupt 5 */ 497 #define IMR_BCNDMAINT4_8192F BIT(24) /* Beacon DMA Interrupt 4 */ 498 #define IMR_BCNDMAINT3_8192F BIT(23) /* Beacon DMA Interrupt 3 */ 499 #define IMR_BCNDMAINT2_8192F BIT(22) /* Beacon DMA Interrupt 2 */ 500 #define IMR_BCNDMAINT1_8192F BIT(21) /* Beacon DMA Interrupt 1 */ 501 #define IMR_BCNDOK7_8192F BIT(20) /* Beacon Queue DMA OK Interrup 7 */ 502 #define IMR_BCNDOK6_8192F BIT(19) /* Beacon Queue DMA OK Interrup 6 */ 503 #define IMR_BCNDOK5_8192F BIT(18) /* Beacon Queue DMA OK Interrup 5 */ 504 #define IMR_BCNDOK4_8192F BIT(17) /* Beacon Queue DMA OK Interrup 4 */ 505 #define IMR_BCNDOK3_8192F BIT(16) /* Beacon Queue DMA OK Interrup 3 */ 506 #define IMR_BCNDOK2_8192F BIT(15) /* Beacon Queue DMA OK Interrup 2 */ 507 #define IMR_BCNDOK1_8192F BIT(14) /* Beacon Queue DMA OK Interrup 1 */ 508 #define IMR_ATIMEND_E_8192F BIT(13) /* ATIM Window End Extension for Win7 */ 509 #define IMR_TXERR_8192F BIT(11) /* Tx Error Flag Interrupt status, write 1 clear. */ 510 #define IMR_RXERR_8192F BIT(10) /* Rx Error Flag INT status, Write 1 clear */ 511 #define IMR_TXFOVW_8192F BIT(9) /* Transmit FIFO Overflow */ 512 #define IMR_RXFOVW_8192F BIT(8) /* Receive FIFO Overflow */ 513 514 /* #define IMR_RX_MASK (IMR_ROK_8192F|IMR_RDU_8192F|IMR_RXFOVW_8192F) */ 515 #define IMR_TX_MASK (IMR_VODOK_8192F | IMR_VIDOK_8192F | IMR_BEDOK_8192F | IMR_BKDOK_8192F | IMR_MGNTDOK_8192F | IMR_HIGHDOK_8192F) 516 #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8192F | IMR_TXBCN0OK_8192F | IMR_TXBCN0ERR_8192F | IMR_BCNDERR0_8192F) 517 #define RT_AC_INT_MASKS (IMR_VIDOK_8192F | IMR_VODOK_8192F | IMR_BEDOK_8192F | IMR_BKDOK_8192F) 518 #endif /* CONFIG_PCI_HCI */ 519 520 /* 2 HSISR 521 * interrupt mask which needs to clear */ 522 #define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\ 523 HSISR_SPS_OCP_INT |\ 524 HSISR_RON_INT |\ 525 HSISR_PDNINT |\ 526 HSISR_GPIO9_INT) 527 528 #define _TXDMA_HIQ_MAP_8192F(x) (((x) & 0x7) << 19) 529 #define _TXDMA_MGQ_MAP_8192F(x) (((x) & 0x7) << 16) 530 #define _TXDMA_BKQ_MAP_8192F(x) (((x) & 0x7) << 13) 531 #define _TXDMA_BEQ_MAP_8192F(x) (((x) & 0x7) << 10) 532 #define _TXDMA_VIQ_MAP_8192F(x) (((x) & 0x7) << 7) 533 #define _TXDMA_VOQ_MAP_8192F(x) (((x) & 0x7) << 4) 534 535 /*mac queue info*/ 536 #define QUEUE_TOTAL_NUM 20/*reg414h : 0~f ac queue 0x10~0x13MGQ HIQ BCNQ CMDQ*/ 537 #define QUEUE_ACQ_NUM 16 538 #define QUEUE_INDEX_MGQ 0x10 539 #define QUEUE_INDEX_HIQ 0x11 540 #define QUEUE_INDEX_BCNQ 0x12 541 #define QUEUE_INDEX_CMDQ 0x13 542 #endif /* __RTL8192F_SPEC_H__ */ 543