1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2017 Realtek Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 *****************************************************************************/ 16 #ifndef __HAL_DATA_H__ 17 #define __HAL_DATA_H__ 18 19 #if 1/* def CONFIG_SINGLE_IMG */ 20 21 #include "../hal/phydm/phydm_precomp.h" 22 #ifdef CONFIG_BT_COEXIST 23 #include <hal_btcoex.h> 24 #endif 25 #include <hal_btcoex_wifionly.h> 26 27 #ifdef CONFIG_SDIO_HCI 28 #include <hal_sdio.h> 29 #endif 30 #ifdef CONFIG_GSPI_HCI 31 #include <hal_gspi.h> 32 #endif 33 34 #if defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR) 35 #include "../hal/hal_dm_acs.h" 36 #endif 37 38 /* 39 * <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. 40 * */ 41 typedef enum _RT_MULTI_FUNC { 42 RT_MULTI_FUNC_NONE = 0x00, 43 RT_MULTI_FUNC_WIFI = 0x01, 44 RT_MULTI_FUNC_BT = 0x02, 45 RT_MULTI_FUNC_GPS = 0x04, 46 } RT_MULTI_FUNC, *PRT_MULTI_FUNC; 47 /* 48 * <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. 49 * */ 50 typedef enum _RT_POLARITY_CTL { 51 RT_POLARITY_LOW_ACT = 0, 52 RT_POLARITY_HIGH_ACT = 1, 53 } RT_POLARITY_CTL, *PRT_POLARITY_CTL; 54 55 /* For RTL8723 regulator mode. by tynli. 2011.01.14. */ 56 typedef enum _RT_REGULATOR_MODE { 57 RT_SWITCHING_REGULATOR = 0, 58 RT_LDO_REGULATOR = 1, 59 } RT_REGULATOR_MODE, *PRT_REGULATOR_MODE; 60 61 /* 62 * Interface type. 63 * */ 64 typedef enum _INTERFACE_SELECT_PCIE { 65 INTF_SEL0_SOLO_MINICARD = 0, /* WiFi solo-mCard */ 66 INTF_SEL1_BT_COMBO_MINICARD = 1, /* WiFi+BT combo-mCard */ 67 INTF_SEL2_PCIe = 2, /* PCIe Card */ 68 } INTERFACE_SELECT_PCIE, *PINTERFACE_SELECT_PCIE; 69 70 71 typedef enum _INTERFACE_SELECT_USB { 72 INTF_SEL0_USB = 0, /* USB */ 73 INTF_SEL1_USB_High_Power = 1, /* USB with high power PA */ 74 INTF_SEL2_MINICARD = 2, /* Minicard */ 75 INTF_SEL3_USB_Solo = 3, /* USB solo-Slim module */ 76 INTF_SEL4_USB_Combo = 4, /* USB Combo-Slim module */ 77 INTF_SEL5_USB_Combo_MF = 5, /* USB WiFi+BT Multi-Function Combo, i.e., Proprietary layout(AS-VAU) which is the same as SDIO card */ 78 } INTERFACE_SELECT_USB, *PINTERFACE_SELECT_USB; 79 80 typedef enum _RT_AMPDU_BRUST_MODE { 81 RT_AMPDU_BRUST_NONE = 0, 82 RT_AMPDU_BRUST_92D = 1, 83 RT_AMPDU_BRUST_88E = 2, 84 RT_AMPDU_BRUST_8812_4 = 3, 85 RT_AMPDU_BRUST_8812_8 = 4, 86 RT_AMPDU_BRUST_8812_12 = 5, 87 RT_AMPDU_BRUST_8812_15 = 6, 88 RT_AMPDU_BRUST_8723B = 7, 89 } RT_AMPDU_BRUST, *PRT_AMPDU_BRUST_MODE; 90 91 /* Tx Power Limit Table Size */ 92 #define MAX_REGULATION_NUM 4 93 #define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE 4 94 #define MAX_2_4G_BANDWIDTH_NUM 2 95 #define MAX_RATE_SECTION_NUM 10 96 #define MAX_5G_BANDWIDTH_NUM 4 97 98 #define NUM_OF_TARGET_TXPWR_2G 10 /* CCK:1, OFDM:1, HT:4, VHT:4 */ 99 #define NUM_OF_TARGET_TXPWR_5G 9 /* OFDM:1, HT:4, VHT:4 */ 100 101 #ifdef RTW_RX_AGGREGATION 102 typedef enum _RX_AGG_MODE { 103 RX_AGG_DISABLE, 104 RX_AGG_DMA, 105 RX_AGG_USB, 106 RX_AGG_MIX 107 } RX_AGG_MODE; 108 109 /* #define MAX_RX_DMA_BUFFER_SIZE 10240 */ /* 10K for 8192C RX DMA buffer */ 110 111 #endif /* RTW_RX_AGGREGATION */ 112 113 /* E-Fuse */ 114 #ifdef CONFIG_RTL8188E 115 #define EFUSE_MAP_SIZE 512 116 #endif 117 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) 118 #define EFUSE_MAP_SIZE 512 119 #endif 120 #ifdef CONFIG_RTL8192E 121 #define EFUSE_MAP_SIZE 512 122 #endif 123 #ifdef CONFIG_RTL8723B 124 #define EFUSE_MAP_SIZE 512 125 #endif 126 #ifdef CONFIG_RTL8814A 127 #define EFUSE_MAP_SIZE 512 128 #endif 129 #ifdef CONFIG_RTL8703B 130 #define EFUSE_MAP_SIZE 512 131 #endif 132 #ifdef CONFIG_RTL8723D 133 #define EFUSE_MAP_SIZE 512 134 #endif 135 #ifdef CONFIG_RTL8188F 136 #define EFUSE_MAP_SIZE 512 137 #endif 138 #ifdef CONFIG_RTL8188GTV 139 #define EFUSE_MAP_SIZE 512 140 #endif 141 #ifdef CONFIG_RTL8710B 142 #define EFUSE_MAP_SIZE 512 143 #endif 144 #ifdef CONFIG_RTL8192F 145 #define EFUSE_MAP_SIZE 512 146 #endif 147 148 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8814B) 149 #define EFUSE_MAX_SIZE 1024 150 #elif defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8710B) 151 #define EFUSE_MAX_SIZE 256 152 #else 153 #define EFUSE_MAX_SIZE 512 154 #endif 155 /* end of E-Fuse */ 156 157 #define Mac_OFDM_OK 0x00000000 158 #define Mac_OFDM_Fail 0x10000000 159 #define Mac_OFDM_FasleAlarm 0x20000000 160 #define Mac_CCK_OK 0x30000000 161 #define Mac_CCK_Fail 0x40000000 162 #define Mac_CCK_FasleAlarm 0x50000000 163 #define Mac_HT_OK 0x60000000 164 #define Mac_HT_Fail 0x70000000 165 #define Mac_HT_FasleAlarm 0x90000000 166 #define Mac_DropPacket 0xA0000000 167 168 #ifdef CONFIG_RF_POWER_TRIM 169 #if defined(CONFIG_RTL8723B) 170 #define REG_RF_BB_GAIN_OFFSET 0x7f 171 #define RF_GAIN_OFFSET_MASK 0xfffff 172 #elif defined(CONFIG_RTL8188E) 173 #define REG_RF_BB_GAIN_OFFSET 0x55 174 #define RF_GAIN_OFFSET_MASK 0xfffff 175 #else 176 #define REG_RF_BB_GAIN_OFFSET 0x55 177 #define RF_GAIN_OFFSET_MASK 0xfffff 178 #endif /* CONFIG_RTL8723B */ 179 #endif /*CONFIG_RF_POWER_TRIM*/ 180 181 /* For store initial value of BB register */ 182 typedef struct _BB_INIT_REGISTER { 183 u16 offset; 184 u32 value; 185 186 } BB_INIT_REGISTER, *PBB_INIT_REGISTER; 187 188 #define PAGE_SIZE_128 128 189 #define PAGE_SIZE_256 256 190 #define PAGE_SIZE_512 512 191 192 #define HCI_SUS_ENTER 0 193 #define HCI_SUS_LEAVING 1 194 #define HCI_SUS_LEAVE 2 195 #define HCI_SUS_ENTERING 3 196 #define HCI_SUS_ERR 4 197 198 #define EFUSE_FILE_UNUSED 0 199 #define EFUSE_FILE_FAILED 1 200 #define EFUSE_FILE_LOADED 2 201 202 #define MACADDR_FILE_UNUSED 0 203 #define MACADDR_FILE_FAILED 1 204 #define MACADDR_FILE_LOADED 2 205 206 #define MAX_IQK_INFO_BACKUP_CHNL_NUM 5 207 #define MAX_IQK_INFO_BACKUP_REG_NUM 10 208 209 struct kfree_data_t { 210 u8 flag; 211 s8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX]; 212 213 #if CONFIG_IEEE80211_BAND_5GHZ 214 s8 pa_bias_5g[RF_PATH_MAX]; 215 s8 pad_bias_5g[RF_PATH_MAX]; 216 #endif 217 s8 thermal; 218 }; 219 220 bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data); 221 222 struct hal_spec_t { 223 char *ic_name; 224 u8 macid_num; 225 226 u8 sec_cam_ent_num; 227 u8 sec_cap; 228 u8 wow_cap; 229 u8 macid_cap; 230 u16 macid_txrpt; 231 u8 macid_txrpt_pgsz; 232 233 u8 rfpath_num_2g:4; /* used for tx power index path */ 234 u8 rfpath_num_5g:4; /* used for tx power index path */ 235 u8 rf_reg_path_num; 236 u8 rf_reg_path_avail_num; 237 u8 rf_reg_trx_path_bmp; /* [7:4]TX path bmp, [0:3]RX path bmp */ 238 u8 max_tx_cnt; 239 240 u8 tx_nss_num:4; 241 u8 rx_nss_num:4; 242 243 u8 band_cap; /* value of BAND_CAP_XXX */ 244 u8 bw_cap; /* value of BW_CAP_XXX */ 245 u8 port_num; 246 u8 proto_cap; /* value of PROTO_CAP_XXX */ 247 248 u8 txgi_max; /* maximum tx power gain index */ 249 u8 txgi_pdbm; /* tx power gain index per dBm */ 250 251 u8 wl_func; /* value of WL_FUNC_XXX */ 252 253 u8 tx_aclt_unit_factor; /* how many 32us */ 254 255 u8 rx_tsf_filter:1; 256 257 u8 pg_txpwr_saddr; /* starting address of PG tx power info */ 258 u8 pg_txgi_diff_factor; /* PG tx power gain index diff to tx power gain index */ 259 260 u8 hci_type; /* value of HCI Type */ 261 }; 262 263 #define HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) ((_spec)->rfpath_num_2g > (_path)) 264 #define HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) ((_spec)->rfpath_num_5g > (_path)) 265 #define HAL_SPEC_CHK_RF_PATH(_spec, _band, _path) ( \ 266 _band == BAND_ON_2_4G ? HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) : \ 267 _band == BAND_ON_5G ? HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) : 0) 268 269 #ifdef CONFIG_PHY_CAPABILITY_QUERY 270 struct phy_spec_t { 271 u32 trx_cap; 272 u32 stbc_cap; 273 u32 ldpc_cap; 274 u32 txbf_param; 275 u32 txbf_cap; 276 }; 277 #endif 278 struct hal_iqk_reg_backup { 279 u8 central_chnl; 280 u8 bw_mode; 281 u32 reg_backup[MAX_RF_PATH][MAX_IQK_INFO_BACKUP_REG_NUM]; 282 }; 283 284 285 typedef struct hal_p2p_ps_para { 286 /*DW0*/ 287 u8 offload_en:1; 288 u8 role:1; 289 u8 ctwindow_en:1; 290 u8 noa_en:1; 291 u8 noa_sel:1; 292 u8 all_sta_sleep:1; 293 u8 discovery:1; 294 u8 disable_close_rf:1; 295 u8 p2p_port_id; 296 u8 p2p_group; 297 u8 p2p_macid; 298 299 /*DW1*/ 300 u8 ctwindow_length; 301 u8 rsvd3; 302 u8 rsvd4; 303 u8 rsvd5; 304 305 /*DW2*/ 306 u32 noa_duration_para; 307 308 /*DW3*/ 309 u32 noa_interval_para; 310 311 /*DW4*/ 312 u32 noa_start_time_para; 313 314 /*DW5*/ 315 u32 noa_count_para; 316 } HAL_P2P_PS_PARA, *PHAL_P2P_PS_PARA; 317 318 #define TXPWR_LMT_RS_CCK 0 319 #define TXPWR_LMT_RS_OFDM 1 320 #define TXPWR_LMT_RS_HT 2 321 #define TXPWR_LMT_RS_VHT 3 322 #define TXPWR_LMT_RS_NUM 4 323 324 #define TXPWR_LMT_RS_NUM_2G 4 /* CCK, OFDM, HT, VHT */ 325 #define TXPWR_LMT_RS_NUM_5G 3 /* OFDM, HT, VHT */ 326 327 #if CONFIG_TXPWR_LIMIT 328 extern const char *const _txpwr_lmt_rs_str[]; 329 #define txpwr_lmt_rs_str(rs) (((rs) >= TXPWR_LMT_RS_NUM) ? _txpwr_lmt_rs_str[TXPWR_LMT_RS_NUM] : _txpwr_lmt_rs_str[(rs)]) 330 331 struct txpwr_lmt_ent { 332 _list list; 333 334 s8 lmt_2g[MAX_2_4G_BANDWIDTH_NUM] 335 [TXPWR_LMT_RS_NUM_2G] 336 [CENTER_CH_2G_NUM] 337 [MAX_TX_COUNT]; 338 339 #if CONFIG_IEEE80211_BAND_5GHZ 340 s8 lmt_5g[MAX_5G_BANDWIDTH_NUM] 341 [TXPWR_LMT_RS_NUM_5G] 342 [CENTER_CH_5G_ALL_NUM] 343 [MAX_TX_COUNT]; 344 #endif 345 346 char regd_name[0]; 347 }; 348 #endif /* CONFIG_TXPWR_LIMIT */ 349 350 typedef struct hal_com_data { 351 HAL_VERSION version_id; 352 RT_MULTI_FUNC MultiFunc; /* For multi-function consideration. */ 353 RT_POLARITY_CTL PolarityCtl; /* For Wifi PDn Polarity control. */ 354 RT_REGULATOR_MODE RegulatorMode; /* switching regulator or LDO */ 355 u8 hw_init_completed; 356 /****** FW related ******/ 357 u32 firmware_size; 358 u16 firmware_version; 359 u16 FirmwareVersionRev; 360 u16 firmware_sub_version; 361 u16 FirmwareSignature; 362 u8 RegFWOffload; 363 u8 bFWReady; 364 u8 bBTFWReady; 365 u8 fw_ractrl; 366 u8 LastHMEBoxNum; /* H2C - for host message to fw */ 367 #ifdef CONFIG_LPS_1T1R 368 u8 lps_1t1r; 369 #endif 370 371 /****** current WIFI_PHY values ******/ 372 WIRELESS_MODE CurrentWirelessMode; 373 enum channel_width current_channel_bw; 374 BAND_TYPE current_band_type; /* 0:2.4G, 1:5G */ 375 u8 current_channel; 376 u8 cch_20; 377 u8 cch_40; 378 u8 cch_80; 379 u8 CurrentCenterFrequencyIndex1; 380 u8 nCur40MhzPrimeSC; /* Control channel sub-carrier */ 381 u8 nCur80MhzPrimeSC; /* used for primary 40MHz of 80MHz mode */ 382 BOOLEAN bSwChnlAndSetBWInProgress; 383 u8 bDisableSWChannelPlan; /* flag of disable software change channel plan */ 384 u16 BasicRateSet; 385 u32 ReceiveConfig; 386 #ifdef CONFIG_WIFI_MONITOR 387 struct mon_reg_backup mon_backup; /* used for switching back from monitor mode */ 388 #endif /* CONFIG_WIFI_MONITOR */ 389 u8 rx_tsf_addr_filter_config; /* for 8822B/8821C USE */ 390 BOOLEAN bSwChnl; 391 BOOLEAN bSetChnlBW; 392 BOOLEAN bSWToBW40M; 393 BOOLEAN bSWToBW80M; 394 BOOLEAN bChnlBWInitialized; 395 396 #ifdef CONFIG_RTW_ACS 397 struct auto_chan_sel acs; 398 #endif 399 #ifdef CONFIG_BCN_RECOVERY 400 u8 issue_bcn_fail; 401 #endif /*CONFIG_BCN_RECOVERY*/ 402 403 /****** rf_ctrl *****/ 404 u8 rf_chip; 405 406 u8 trx_path_bmp; /* [7:4]TX path bmp, [0:3]RX path bmp */ 407 u8 rf_type; /*enum rf_type , is RF_PATH - GET_HAL_RFPATH*/ 408 u8 NumTotalRFPath; /*GET_HAL_RFPATH_NUM*/ 409 u8 max_tx_cnt; 410 u8 tx_nss; /*tx Spatial Streams - GET_HAL_TX_NSS*/ 411 u8 rx_nss; /*rx Spatial Streams - GET_HAL_RX_NSS*/ 412 u8 txpath_cap_num_nss[4]; /* capable path num for NSS TX, [0] for 1SS, [3] for 4SS */ 413 414 u8 PackageType; 415 u8 antenna_test; 416 417 /* runtime TRX path setting */ 418 enum bb_path txpath; /* TX path bmp */ 419 enum bb_path rxpath; /* RX path bmp */ 420 enum bb_path txpath_nss[4]; /* path bmp for NSS TX, [0] for 1SS, [3] for 4SS */ 421 u8 txpath_num_nss[4]; /* path num for NSS TX, [0] for 1SS, [3] for 4SS */ 422 423 /****** Debug ******/ 424 u16 ForcedDataRate; /* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */ 425 u8 bDumpRxPkt; 426 u8 bDumpTxPkt; 427 u8 dis_turboedca; /* 1: disable turboedca, 428 2: disable turboedca and setting EDCA parameter based on the input parameter*/ 429 u32 edca_param_mode; 430 431 /****** EEPROM setting.******/ 432 u8 bautoload_fail_flag; 433 u8 efuse_file_status; 434 u8 macaddr_file_status; 435 u8 EepromOrEfuse; 436 u8 efuse_eeprom_data[EEPROM_MAX_SIZE]; /*92C:256bytes, 88E:512bytes, we use union set (512bytes)*/ 437 u8 InterfaceSel; /* board type kept in eFuse */ 438 u16 CustomerID; 439 440 u16 EEPROMVID; 441 u16 EEPROMSVID; 442 #ifdef CONFIG_USB_HCI 443 u8 EEPROMUsbSwitch; 444 u16 EEPROMPID; 445 u16 EEPROMSDID; 446 #endif 447 #ifdef CONFIG_PCI_HCI 448 u16 EEPROMDID; 449 u16 EEPROMSMID; 450 #endif 451 452 u8 EEPROMCustomerID; 453 u8 EEPROMSubCustomerID; 454 u8 EEPROMVersion; 455 u8 EEPROMRegulatory; 456 u8 eeprom_thermal_meter; 457 u8 EEPROMBluetoothCoexist; 458 u8 EEPROMBluetoothType; 459 u8 EEPROMBluetoothAntNum; 460 u8 EEPROMBluetoothAntIsolation; 461 u8 EEPROMBluetoothRadioShared; 462 u8 EEPROMMACAddr[ETH_ALEN]; 463 464 u8 eeprom_trx_path_bmp; /* [7:4]TX path bmp, [0:3]RX path bmp. 0x00:not specified */ 465 u8 eeprom_max_tx_cnt; /* 0: not specified */ 466 467 u8 tx_bbswing_24G; 468 u8 tx_bbswing_5G; 469 u8 efuse0x3d7; /* efuse[0x3D7] */ 470 u8 efuse0x3d8; /* efuse[0x3D8] */ 471 472 #ifdef CONFIG_RF_POWER_TRIM 473 u8 EEPROMRFGainOffset; 474 u8 EEPROMRFGainVal; 475 struct kfree_data_t kfree_data; 476 #endif /*CONFIG_RF_POWER_TRIM*/ 477 478 #ifdef CONFIG_RTL8814A 479 u32 BackUp_BB_REG_4_2nd_CCA[3]; 480 #endif 481 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || \ 482 defined(CONFIG_RTL8723D) || \ 483 defined(CONFIG_RTL8192F) 484 485 u8 adjuseVoltageVal; 486 u8 need_restore; 487 #endif 488 u8 EfuseUsedPercentage; 489 u16 EfuseUsedBytes; 490 /*u8 EfuseMap[2][HWSET_MAX_SIZE_JAGUAR];*/ 491 EFUSE_HAL EfuseHal; 492 493 u8 txpwr_pg_mode; /* enum txpwr_pg_mode */ 494 495 /*---------------------------------------------------------------------------------*/ 496 #ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX 497 /* 2.4G TX power info for target TX power*/ 498 u8 Index24G_CCK_Base[MAX_RF_PATH][CENTER_CH_2G_NUM]; 499 u8 Index24G_BW40_Base[MAX_RF_PATH][CENTER_CH_2G_NUM]; 500 s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 501 s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 502 s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 503 s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 504 505 /* 5G TX power info for target TX power*/ 506 #if CONFIG_IEEE80211_BAND_5GHZ 507 u8 Index5G_BW40_Base[MAX_RF_PATH][CENTER_CH_5G_ALL_NUM]; 508 u8 Index5G_BW80_Base[MAX_RF_PATH][CENTER_CH_5G_80M_NUM]; 509 s8 OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 510 s8 BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 511 s8 BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 512 s8 BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 513 #endif 514 #endif /* CONFIG_TXPWR_PG_WITH_PWR_IDX */ 515 516 u8 txpwr_by_rate_undefined_band_path[TX_PWR_BY_RATE_NUM_BAND] 517 [TX_PWR_BY_RATE_NUM_RF]; 518 519 s8 TxPwrByRate[TX_PWR_BY_RATE_NUM_BAND] 520 [TX_PWR_BY_RATE_NUM_RF] 521 [TX_PWR_BY_RATE_NUM_RATE]; 522 523 /* Store the target power for each rate section and rf path */ 524 u8 target_txpwr_2g[TX_PWR_BY_RATE_NUM_RF] 525 [NUM_OF_TARGET_TXPWR_2G]; 526 u8 target_txpwr_5g[TX_PWR_BY_RATE_NUM_RF] 527 [NUM_OF_TARGET_TXPWR_5G]; 528 529 bool set_entire_txpwr; 530 531 #if defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B) \ 532 || defined(CONFIG_RTL8723F) 533 u32 txagc_set_buf; 534 #endif 535 536 #ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX 537 u8 txpwr_idx_offload_buf[3]; /* for CCK, OFDM, HT1SS */ 538 struct submit_ctx txpwr_idx_offload_sctx; 539 #endif 540 541 u8 txpwr_by_rate_loaded:1; 542 u8 txpwr_by_rate_from_file:1; 543 u8 txpwr_limit_loaded:1; 544 u8 txpwr_limit_from_file:1; 545 546 /* Read/write are allow for following hardware information variables */ 547 u8 crystal_cap; 548 549 u8 PAType_2G; 550 u8 PAType_5G; 551 u8 LNAType_2G; 552 u8 LNAType_5G; 553 u8 ExternalPA_2G; 554 u8 ExternalLNA_2G; 555 u8 external_pa_5g; 556 u8 external_lna_5g; 557 u16 TypeGLNA; 558 u16 TypeGPA; 559 u16 TypeALNA; 560 u16 TypeAPA; 561 u16 rfe_type; 562 563 u8 bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */ 564 u32 ac_param_be; /* Original parameter for BE, use for EDCA turbo. */ 565 u8 is_turbo_edca; 566 u8 prv_traffic_idx; 567 BB_REGISTER_DEFINITION_T PHYRegDef[MAX_RF_PATH]; /* Radio A/B/C/D */ 568 569 u32 RfRegChnlVal[MAX_RF_PATH]; 570 571 /* RDG enable */ 572 BOOLEAN bRDGEnable; 573 574 #if defined (CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) 575 u32 RegRRSR; 576 #endif 577 578 /****** antenna diversity ******/ 579 u8 AntDivCfg; 580 u8 with_extenal_ant_switch; 581 u8 b_fix_tx_ant; 582 u8 AntDetection; 583 u8 TRxAntDivType; 584 u8 ant_path; /* for 8723B s0/s1 selection */ 585 u32 antenna_tx_path; /* Antenna path Tx */ 586 u32 AntennaRxPath; /* Antenna path Rx */ 587 u8 sw_antdiv_bl_state; 588 589 /******** PHY DM & DM Section **********/ 590 _lock IQKSpinLock; 591 u8 INIDATA_RATE[MACID_NUM_SW_LIMIT]; 592 593 struct dm_struct odmpriv; 594 u64 bk_rf_ability; 595 u8 bIQKInitialized; 596 u8 bNeedIQK; 597 u8 neediqk_24g; 598 u8 IQK_MP_Switch; 599 u8 bScanInProcess; 600 u8 phydm_init_result; /*BB and RF para match or not*/ 601 /******** PHY DM & DM Section **********/ 602 603 604 605 /* 2010/08/09 MH Add CU power down mode. */ 606 BOOLEAN pwrdown; 607 608 #ifdef CONFIG_P2P 609 #ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP 610 u16 p2p_ps_offload; 611 #else 612 u8 p2p_ps_offload; 613 #endif 614 #endif 615 /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */ 616 u8 bMacPwrCtrlOn; 617 u8 hci_sus_state; 618 619 u8 RegIQKFWOffload; 620 struct submit_ctx iqk_sctx; 621 u8 ch_switch_offload; 622 struct submit_ctx chsw_sctx; 623 624 RT_AMPDU_BRUST AMPDUBurstMode; /* 92C maybe not use, but for compile successfully */ 625 626 u8 OutEpQueueSel; 627 u8 OutEpNumber; 628 629 #ifdef RTW_RX_AGGREGATION 630 RX_AGG_MODE rxagg_mode; 631 632 /* For RX Aggregation DMA Mode */ 633 u8 rxagg_dma_size; 634 u8 rxagg_dma_timeout; 635 #endif /* RTW_RX_AGGREGATION */ 636 637 bool intf_start; 638 639 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) 640 /* */ 641 /* For SDIO Interface HAL related */ 642 /* */ 643 644 /* */ 645 /* SDIO ISR Related */ 646 /* 647 * u32 IntrMask[1]; 648 * u32 IntrMaskToSet[1]; 649 * LOG_INTERRUPT InterruptLog; */ 650 u32 sdio_himr; 651 u32 sdio_hisr; 652 #ifndef RTW_HALMAC 653 /* */ 654 /* SDIO Tx FIFO related. */ 655 /* */ 656 /* HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg */ 657 #ifdef CONFIG_RTL8192F 658 u16 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE]; 659 #else 660 u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE]; 661 #endif/*CONFIG_RTL8192F*/ 662 #ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT 663 u8 sdio_avail_int_en_q; 664 #endif 665 _lock SdioTxFIFOFreePageLock; 666 u8 SdioTxOQTMaxFreeSpace; 667 u8 SdioTxOQTFreeSpace; 668 #else /* RTW_HALMAC */ 669 u16 SdioTxOQTFreeSpace; 670 #endif /* RTW_HALMAC */ 671 672 /* */ 673 /* SDIO Rx FIFO related. */ 674 /* */ 675 u8 SdioRxFIFOCnt; 676 #if defined (CONFIG_RTL8822C) || defined (CONFIG_RTL8192F) 677 u32 SdioRxFIFOSize; 678 #else 679 u16 SdioRxFIFOSize; 680 #endif 681 682 #ifndef RTW_HALMAC 683 u32 sdio_tx_max_len[SDIO_MAX_TX_QUEUE];/* H, N, L, used for sdio tx aggregation max length per queue */ 684 #else 685 #ifdef CONFIG_RTL8821C 686 u16 tx_high_page; 687 u16 tx_low_page; 688 u16 tx_normal_page; 689 u16 tx_extra_page; 690 u16 tx_pub_page; 691 u8 max_oqt_size; 692 #ifdef XMIT_BUF_SIZE 693 u32 max_xmit_size_vovi; 694 u32 max_xmit_size_bebk; 695 #endif /*XMIT_BUF_SIZE*/ 696 u16 max_xmit_page; 697 u16 max_xmit_page_vo; 698 u16 max_xmit_page_vi; 699 u16 max_xmit_page_be; 700 u16 max_xmit_page_bk; 701 702 #endif /*#ifdef CONFIG_RTL8821C*/ 703 #endif /* !RTW_HALMAC */ 704 #endif /* CONFIG_SDIO_HCI */ 705 706 #ifdef CONFIG_USB_HCI 707 708 /* 2010/12/10 MH Add for USB aggreation mode dynamic shceme. */ 709 BOOLEAN UsbRxHighSpeedMode; 710 BOOLEAN UsbTxVeryHighSpeedMode; 711 u32 UsbBulkOutSize; 712 BOOLEAN bSupportUSB3; 713 u8 usb_intf_start; 714 715 /* Interrupt relatd register information. */ 716 u32 IntArray[3];/* HISR0,HISR1,HSISR */ 717 u32 IntrMask[3]; 718 #ifdef CONFIG_USB_TX_AGGREGATION 719 u8 UsbTxAggMode; 720 u8 UsbTxAggDescNum; 721 #endif /* CONFIG_USB_TX_AGGREGATION */ 722 723 #ifdef CONFIG_USB_RX_AGGREGATION 724 u16 HwRxPageSize; /* Hardware setting */ 725 726 /* For RX Aggregation USB Mode */ 727 u8 rxagg_usb_size; 728 u8 rxagg_usb_timeout; 729 #endif/* CONFIG_USB_RX_AGGREGATION */ 730 #endif /* CONFIG_USB_HCI */ 731 732 733 #ifdef CONFIG_PCI_HCI 734 /* */ 735 /* EEPROM setting. */ 736 /* */ 737 u32 TransmitConfig; 738 u32 IntrMaskToSet[2]; 739 u32 IntArray[4]; 740 u32 IntrMask[4]; 741 u32 SysIntArray[1]; 742 u32 SysIntrMask[1]; 743 u32 IntrMaskReg[2]; 744 u32 IntrMaskDefault[4]; 745 746 u32 pci_backdoor_ctrl; 747 748 u8 bDefaultAntenna; 749 750 u8 bInterruptMigration; 751 u8 bDisableTxInt; 752 753 u16 RxTag; 754 #endif /* CONFIG_PCI_HCI */ 755 756 757 #ifdef DBG_CONFIG_ERROR_DETECT 758 struct sreset_priv srestpriv; 759 #endif /* #ifdef DBG_CONFIG_ERROR_DETECT */ 760 761 #ifdef CONFIG_BT_COEXIST 762 /* For bluetooth co-existance */ 763 BT_COEXIST bt_coexist; 764 #endif /* CONFIG_BT_COEXIST */ 765 766 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) \ 767 || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D)|| defined(CONFIG_RTL8192F) 768 #ifndef CONFIG_PCI_HCI /* mutual exclusive with PCI -- so they're SDIO and GSPI */ 769 /* Interrupt relatd register information. */ 770 u32 SysIntrStatus; 771 u32 SysIntrMask; 772 #endif 773 #endif /*endif CONFIG_RTL8723B */ 774 775 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE 776 char para_file_buf[MAX_PARA_FILE_BUF_LEN]; 777 char *mac_reg; 778 u32 mac_reg_len; 779 char *bb_phy_reg; 780 u32 bb_phy_reg_len; 781 char *bb_agc_tab; 782 u32 bb_agc_tab_len; 783 char *bb_phy_reg_pg; 784 u32 bb_phy_reg_pg_len; 785 char *bb_phy_reg_mp; 786 u32 bb_phy_reg_mp_len; 787 char *rf_radio_a; 788 u32 rf_radio_a_len; 789 char *rf_radio_b; 790 u32 rf_radio_b_len; 791 char *rf_tx_pwr_track; 792 u32 rf_tx_pwr_track_len; 793 char *rf_tx_pwr_lmt; 794 u32 rf_tx_pwr_lmt_len; 795 #endif 796 797 #ifdef CONFIG_BACKGROUND_NOISE_MONITOR 798 struct noise_monitor nm; 799 #endif 800 801 struct hal_spec_t hal_spec; 802 #ifdef CONFIG_PHY_CAPABILITY_QUERY 803 struct phy_spec_t phy_spec; 804 #endif 805 u8 RfKFreeEnable; 806 u8 RfKFree_ch_group; 807 BOOLEAN bCCKinCH14; 808 BB_INIT_REGISTER RegForRecover[5]; 809 810 #if defined(CONFIG_PCI_HCI) && defined(RTL8814AE_SW_BCN) 811 BOOLEAN bCorrectBCN; 812 #endif 813 #ifdef CONFIG_RTL8814A 814 u32 RxGainOffset[4]; /*{2G, 5G_Low, 5G_Middle, G_High}*/ 815 u8 BackUp_IG_REG_4_Chnl_Section[4]; /*{A,B,C,D}*/ 816 #endif 817 struct hal_iqk_reg_backup iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM]; 818 819 #ifdef RTW_HALMAC 820 u16 drv_rsvd_page_number; 821 #endif 822 823 #ifdef CONFIG_BEAMFORMING 824 u8 backup_snd_ptcl_ctrl; 825 #ifdef RTW_BEAMFORMING_VERSION_2 826 struct beamforming_info beamforming_info; 827 #endif /* RTW_BEAMFORMING_VERSION_2 */ 828 #endif /* CONFIG_BEAMFORMING */ 829 830 u8 not_xmitframe_fw_dl; /*not use xmitframe to download fw*/ 831 u8 phydm_op_mode; 832 833 u8 in_cta_test; 834 835 #ifdef CONFIG_RTW_LED 836 struct led_priv led; 837 #endif 838 /* for multi channel case (ex: MCC/TDLS) */ 839 u8 multi_ch_switch_mode; 840 841 #ifdef CONFIG_RTL8814B 842 u8 dma_ch_map[32]; /* TXDESC qsel maximum size */ 843 #endif 844 845 } HAL_DATA_COMMON, *PHAL_DATA_COMMON; 846 847 typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE; 848 #define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)(((struct _ADAPTER*)__pAdapter)->HalData)) 849 #define GET_HAL_SPEC(__pAdapter) (&(GET_HAL_DATA((__pAdapter))->hal_spec)) 850 #define adapter_to_led(adapter) (&(GET_HAL_DATA(adapter)->led)) 851 852 #define RT_GetInterfaceSelection(_Adapter) (GET_HAL_DATA(_Adapter)->InterfaceSel) 853 854 #define GET_KFREE_DATA(_adapter) (&(GET_HAL_DATA((_adapter))->kfree_data)) 855 856 #define SUPPORT_HW_RADIO_DETECT(Adapter) (RT_GetInterfaceSelection(Adapter) == INTF_SEL2_MINICARD || \ 857 RT_GetInterfaceSelection(Adapter) == INTF_SEL3_USB_Solo || \ 858 RT_GetInterfaceSelection(Adapter) == INTF_SEL4_USB_Combo) 859 860 #define get_hal_mac_addr(adapter) (GET_HAL_DATA(adapter)->EEPROMMACAddr) 861 #define is_boot_from_eeprom(adapter) (GET_HAL_DATA(adapter)->EepromOrEfuse) 862 #define rtw_get_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed) 863 #define rtw_set_hw_init_completed(adapter, cmp) (GET_HAL_DATA(adapter)->hw_init_completed = cmp) 864 #define rtw_is_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed == _TRUE) 865 866 /* refer to (hal_data->version_id.RFType / registrypriv->rf_path / 8814a from efuse or registrypriv)*/ 867 #define GET_HAL_RFPATH(adapter) (GET_HAL_DATA(adapter)->rf_type) 868 #define GET_HAL_RFPATH_NUM(adapter) (GET_HAL_DATA(adapter)->NumTotalRFPath) 869 #define GET_HAL_TX_PATH_BMP(adapter) ((GET_HAL_DATA(adapter)->trx_path_bmp & 0xF0) >> 4) 870 #define GET_HAL_RX_PATH_BMP(adapter) (GET_HAL_DATA(adapter)->trx_path_bmp & 0x0F) 871 872 /* refer to (registrypriv-> tx_nss,rx_nss / hal_spec->tx_nss_num,rx_nss_num)*/ 873 #define GET_HAL_TX_NSS(adapter) (GET_HAL_DATA(adapter)->tx_nss) 874 #define GET_HAL_RX_NSS(adapter) (GET_HAL_DATA(adapter)->rx_nss) 875 876 #endif 877 878 #ifdef RTW_HALMAC 879 int rtw_halmac_deinit_adapter(struct dvobj_priv *); 880 #endif /* RTW_HALMAC */ 881 882 #endif /* __HAL_DATA_H__ */ 883