1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2017 Realtek Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * The full GNU General Public License is included in this distribution in the
16 * file called LICENSE.
17 *
18 * Contact Information:
19 * wlanfae <wlanfae@realtek.com>
20 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
21 * Hsinchu 300, Taiwan.
22 *
23 * Larry Finger <Larry.Finger@lwfinger.net>
24 *
25 *****************************************************************************/
26
27 /*@************************************************************
28 * include files
29 ************************************************************/
30
31 #include "mp_precomp.h"
32 #include "phydm_precomp.h"
33
34 const u16 phy_rate_table[] = {
35 /*@20M*/
36 1, 2, 5, 11,
37 6, 9, 12, 18, 24, 36, 48, 54,
38 6, 13, 19, 26, 39, 52, 58, 65, /*@MCS0~7*/
39 13, 26, 39, 52, 78, 104, 117, 130, /*@MCS8~15*/
40 19, 39, 58, 78, 117, 156, 175, 195, /*@MCS16~23*/
41 26, 52, 78, 104, 156, 208, 234, 260, /*@MCS24~31*/
42 6, 13, 19, 26, 39, 52, 58, 65, 78, 90, /*@1ss MCS0~9*/
43 13, 26, 39, 52, 78, 104, 117, 130, 156, 180, /*@2ss MCS0~9*/
44 19, 39, 58, 78, 117, 156, 175, 195, 234, 260, /*@3ss MCS0~9*/
45 26, 52, 78, 104, 156, 208, 234, 260, 312, 360 /*@4ss MCS0~9*/
46 };
47
phydm_traffic_load_decision(void * dm_void)48 void phydm_traffic_load_decision(void *dm_void)
49 {
50 struct dm_struct *dm = (struct dm_struct *)dm_void;
51 u8 shift = 0;
52
53 /*@---TP & Trafic-load calculation---*/
54
55 if (dm->last_tx_ok_cnt > *dm->num_tx_bytes_unicast)
56 dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
57
58 if (dm->last_rx_ok_cnt > *dm->num_rx_bytes_unicast)
59 dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
60
61 dm->cur_tx_ok_cnt = *dm->num_tx_bytes_unicast - dm->last_tx_ok_cnt;
62 dm->cur_rx_ok_cnt = *dm->num_rx_bytes_unicast - dm->last_rx_ok_cnt;
63 dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
64 dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
65
66 /*@AP: <<3(8bit), >>20(10^6,M), >>0(1sec)*/
67 shift = 17 + (PHYDM_WATCH_DOG_PERIOD - 1);
68 /*@WIN&CE: <<3(8bit), >>20(10^6,M), >>1(2sec)*/
69
70 dm->tx_tp = (dm->tx_tp >> 1) + (u32)((dm->cur_tx_ok_cnt >> shift) >> 1);
71 dm->rx_tp = (dm->rx_tp >> 1) + (u32)((dm->cur_rx_ok_cnt >> shift) >> 1);
72
73 dm->total_tp = dm->tx_tp + dm->rx_tp;
74
75 /*@[Calculate TX/RX state]*/
76 if (dm->tx_tp > (dm->rx_tp << 1))
77 dm->txrx_state_all = TX_STATE;
78 else if (dm->rx_tp > (dm->tx_tp << 1))
79 dm->txrx_state_all = RX_STATE;
80 else
81 dm->txrx_state_all = BI_DIRECTION_STATE;
82
83 /*@[Traffic load decision]*/
84 dm->pre_traffic_load = dm->traffic_load;
85
86 if (dm->cur_tx_ok_cnt > 1875000 || dm->cur_rx_ok_cnt > 1875000) {
87 /* @( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/
88 dm->traffic_load = TRAFFIC_HIGH;
89 } else if (dm->cur_tx_ok_cnt > 500000 || dm->cur_rx_ok_cnt > 500000) {
90 /*@( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/
91 dm->traffic_load = TRAFFIC_MID;
92 } else if (dm->cur_tx_ok_cnt > 100000 || dm->cur_rx_ok_cnt > 100000) {
93 /*@( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/
94 dm->traffic_load = TRAFFIC_LOW;
95 } else if (dm->cur_tx_ok_cnt > 25000 || dm->cur_rx_ok_cnt > 25000) {
96 /*@( 0.025M * 8bit ) / 2sec = 0.1M bits /sec )*/
97 dm->traffic_load = TRAFFIC_ULTRA_LOW;
98 } else {
99 dm->traffic_load = TRAFFIC_NO_TP;
100 }
101
102 /*@[Calculate consecutive idlel time]*/
103 if (dm->traffic_load == 0)
104 dm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD;
105 else
106 dm->consecutive_idlel_time = 0;
107
108 #if 0
109 PHYDM_DBG(dm, DBG_COMMON_FLOW,
110 "cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n",
111 dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt, dm->last_tx_ok_cnt,
112 dm->last_rx_ok_cnt);
113
114 PHYDM_DBG(dm, DBG_COMMON_FLOW, "tx_tp = %d, rx_tp = %d\n", dm->tx_tp,
115 dm->rx_tp);
116 #endif
117 }
118
phydm_cck_new_agc_chk(struct dm_struct * dm)119 void phydm_cck_new_agc_chk(struct dm_struct *dm)
120 {
121 u32 new_agc_addr = 0x0;
122
123 dm->cck_new_agc = false;
124 #if (RTL8723D_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT ||\
125 RTL8197F_SUPPORT || RTL8710B_SUPPORT || RTL8192F_SUPPORT ||\
126 RTL8195B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\
127 RTL8721D_SUPPORT || RTL8710C_SUPPORT)
128 if (dm->support_ic_type & (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8821C |
129 ODM_RTL8197F | ODM_RTL8710B | ODM_RTL8192F | ODM_RTL8195B |
130 ODM_RTL8721D | ODM_RTL8710C)) {
131 new_agc_addr = R_0xa9c;
132 } else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C |
133 ODM_RTL8814B | ODM_RTL8197G)) {
134 new_agc_addr = R_0x1a9c;
135 }
136
137 /*@1: new agc 0: old agc*/
138 dm->cck_new_agc = (boolean)odm_get_bb_reg(dm, new_agc_addr, BIT(17));
139 #endif
140 #if (RTL8723F_SUPPORT)
141 if (dm->support_ic_type & (ODM_RTL8723F))
142 dm->cck_new_agc = true;
143 #endif
144 }
145
146 /*select 3 or 4 bit LNA */
phydm_cck_lna_bit_num_chk(struct dm_struct * dm)147 void phydm_cck_lna_bit_num_chk(struct dm_struct *dm)
148 {
149 boolean report_type = 0;
150 #if (RTL8192E_SUPPORT)
151 u32 value_824, value_82c;
152 #endif
153
154 #if (RTL8192E_SUPPORT)
155 if (dm->support_ic_type & (ODM_RTL8192E)) {
156 /* @0x824[9] = 0x82C[9] = 0xA80[7] those registers setting
157 * should be equal or CCK RSSI report may be incorrect
158 */
159 value_824 = odm_get_bb_reg(dm, R_0x824, BIT(9));
160 value_82c = odm_get_bb_reg(dm, R_0x82c, BIT(9));
161
162 if (value_824 != value_82c)
163 odm_set_bb_reg(dm, R_0x82c, BIT(9), value_824);
164 odm_set_bb_reg(dm, R_0xa80, BIT(7), value_824);
165 report_type = (boolean)value_824;
166 }
167 #endif
168
169 #if (RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8710B_SUPPORT)
170 if (dm->support_ic_type &
171 (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
172 report_type = (boolean)odm_get_bb_reg(dm, R_0x950, BIT(11));
173
174 if (report_type != 1)
175 pr_debug("[Warning] CCK should be 4bit LNA\n");
176 }
177 #endif
178
179 #if (RTL8821C_SUPPORT)
180 if (dm->support_ic_type & ODM_RTL8821C) {
181 if (dm->default_rf_set_8821c == SWITCH_TO_BTG)
182 report_type = 1;
183 }
184 #endif
185
186 dm->cck_agc_report_type = report_type;
187
188 PHYDM_DBG(dm, ODM_COMP_INIT, "cck_agc_report_type=((%d))\n",
189 dm->cck_agc_report_type);
190 }
191
phydm_init_cck_setting(struct dm_struct * dm)192 void phydm_init_cck_setting(struct dm_struct *dm)
193 {
194 u32 reg_tmp = 0;
195 u32 mask_tmp = 0;
196
197 phydm_cck_new_agc_chk(dm);
198
199 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
200 return;
201
202 reg_tmp = ODM_REG(CCK_RPT_FORMAT, dm);
203 mask_tmp = ODM_BIT(CCK_RPT_FORMAT, dm);
204 dm->is_cck_high_power = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
205
206 PHYDM_DBG(dm, ODM_COMP_INIT, "ext_lna_gain=((%d))\n", dm->ext_lna_gain);
207
208 phydm_config_cck_rx_antenna_init(dm);
209
210 if (dm->support_ic_type & ODM_RTL8192F)
211 phydm_config_cck_rx_path(dm, BB_PATH_AB);
212 else if (dm->valid_path_set == BB_PATH_A)
213 phydm_config_cck_rx_path(dm, BB_PATH_A);
214 else if (dm->valid_path_set == BB_PATH_B)
215 phydm_config_cck_rx_path(dm, BB_PATH_B);
216
217 phydm_cck_lna_bit_num_chk(dm);
218 phydm_get_cck_rssi_table_from_reg(dm);
219 }
220
221 #ifdef CONFIG_RFE_BY_HW_INFO
phydm_init_hw_info_by_rfe(struct dm_struct * dm)222 void phydm_init_hw_info_by_rfe(struct dm_struct *dm)
223 {
224 #if (RTL8821C_SUPPORT)
225 if (dm->support_ic_type & ODM_RTL8821C)
226 phydm_init_hw_info_by_rfe_type_8821c(dm);
227 #endif
228 #if (RTL8197F_SUPPORT)
229 if (dm->support_ic_type & ODM_RTL8197F)
230 phydm_init_hw_info_by_rfe_type_8197f(dm);
231 #endif
232 #if (RTL8197G_SUPPORT)
233 if (dm->support_ic_type & ODM_RTL8197G)
234 phydm_init_hw_info_by_rfe_type_8197g(dm);
235 #endif
236 }
237 #endif
238
phydm_common_info_self_init(struct dm_struct * dm)239 void phydm_common_info_self_init(struct dm_struct *dm)
240 {
241 u32 reg_tmp = 0;
242 u32 mask_tmp = 0;
243
244 dm->run_in_drv_fw = RUN_IN_DRIVER;
245
246 /*@BB IP Generation*/
247 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
248 dm->ic_ip_series = PHYDM_IC_JGR3;
249 else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
250 dm->ic_ip_series = PHYDM_IC_AC;
251 else if (dm->support_ic_type & ODM_IC_11N_SERIES)
252 dm->ic_ip_series = PHYDM_IC_N;
253
254 /*@BB phy-status Generation*/
255 if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC)
256 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_3;
257 else if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC)
258 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_2;
259 else
260 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_1;
261
262 phydm_init_cck_setting(dm);
263
264 reg_tmp = ODM_REG(BB_RX_PATH, dm);
265 mask_tmp = ODM_BIT(BB_RX_PATH, dm);
266 dm->rf_path_rx_enable = (u8)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
267 #if (DM_ODM_SUPPORT_TYPE != ODM_CE)
268 dm->is_net_closed = &dm->BOOLEAN_temp;
269
270 phydm_init_debug_setting(dm);
271 #endif
272 phydm_init_soft_ml_setting(dm);
273
274 dm->phydm_sys_up_time = 0;
275
276 if (dm->support_ic_type & ODM_IC_1SS)
277 dm->num_rf_path = 1;
278 else if (dm->support_ic_type & ODM_IC_2SS)
279 dm->num_rf_path = 2;
280 #if 0
281 /* @RTK do not has IC which is equipped with 3 RF paths,
282 * so ODM_IC_3SS is an enpty macro and result in coverity check errors
283 */
284 else if (dm->support_ic_type & ODM_IC_3SS)
285 dm->num_rf_path = 3;
286 #endif
287 else if (dm->support_ic_type & ODM_IC_4SS)
288 dm->num_rf_path = 4;
289 else
290 dm->num_rf_path = 1;
291
292 phydm_trx_antenna_setting_init(dm, dm->num_rf_path);
293
294 dm->tx_rate = 0xFF;
295 dm->rssi_min_by_path = 0xFF;
296
297 dm->number_linked_client = 0;
298 dm->pre_number_linked_client = 0;
299 dm->number_active_client = 0;
300 dm->pre_number_active_client = 0;
301
302 dm->last_tx_ok_cnt = 0;
303 dm->last_rx_ok_cnt = 0;
304 dm->tx_tp = 0;
305 dm->rx_tp = 0;
306 dm->total_tp = 0;
307 dm->traffic_load = TRAFFIC_LOW;
308
309 dm->nbi_set_result = 0;
310 dm->is_init_hw_info_by_rfe = false;
311 dm->pre_dbg_priority = DBGPORT_RELEASE;
312 dm->tp_active_th = 5;
313 dm->disable_phydm_watchdog = 0;
314
315 dm->u8_dummy = 0xf;
316 dm->u16_dummy = 0xffff;
317 dm->u32_dummy = 0xffffffff;
318 #if (RTL8814B_SUPPORT)
319 /*@------------For spur detection Default Mode------------@*/
320 dm->dsde_sel = DET_CSI;
321 dm->csi_wgt = 4;
322 /*@-------------------------------------------------------@*/
323 #endif
324 dm->pre_is_linked = false;
325 dm->is_linked = false;
326 /*dym bw thre and it can config by registry*/
327 if (dm->en_auto_bw_th == 0)
328 dm->en_auto_bw_th = 20;
329
330 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
331 if (!(dm->is_fcs_mode_enable)) {
332 dm->is_fcs_mode_enable = &dm->boolean_dummy;
333 pr_debug("[Warning] is_fcs_mode_enable=NULL\n");
334 }
335 #endif
336 /*init IOT table*/
337 odm_memory_set(dm, &dm->iot_table, 0, sizeof(struct phydm_iot_center));
338 }
339
phydm_iot_patch_id_update(void * dm_void,u32 iot_idx,boolean en)340 void phydm_iot_patch_id_update(void *dm_void, u32 iot_idx, boolean en)
341 {
342 struct dm_struct *dm = (struct dm_struct *)dm_void;
343 struct phydm_iot_center *iot_table = &dm->iot_table;
344
345 PHYDM_DBG(dm, DBG_CMN, "[IOT] 0x%x = %d\n", iot_idx, en);
346 switch (iot_idx) {
347 case 0x100f0401:
348 iot_table->patch_id_100f0401 = en;
349 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_100f0401 = %d\n",
350 iot_table->patch_id_100f0401);
351 break;
352 case 0x10120200:
353 iot_table->patch_id_10120200 = en;
354 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_10120200 = %d\n",
355 iot_table->patch_id_10120200);
356 break;
357 case 0x40010700:
358 iot_table->patch_id_40010700 = en;
359 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_40010700 = %d\n",
360 iot_table->patch_id_40010700);
361 break;
362 case 0x021f0800:
363 iot_table->patch_id_021f0800 = en;
364 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_021f0800 = %d\n",
365 iot_table->patch_id_021f0800);
366 break;
367 case 0x011f0500:
368 iot_table->patch_id_011f0500 = en;
369 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_011f0500 = %d\n",
370 iot_table->patch_id_011f0500);
371 break;
372 default:
373 pr_debug("[%s] warning!\n", __func__);
374 break;
375 }
376 }
377
phydm_cmn_sta_info_update(void * dm_void,u8 macid)378 void phydm_cmn_sta_info_update(void *dm_void, u8 macid)
379 {
380 struct dm_struct *dm = (struct dm_struct *)dm_void;
381 struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
382 struct ra_sta_info *ra = NULL;
383
384 if (is_sta_active(sta)) {
385 ra = &sta->ra_info;
386 } else {
387 PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid sta_info\n",
388 __func__);
389 return;
390 }
391
392 PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
393 PHYDM_DBG(dm, DBG_RA_MASK, "MACID=%d\n", sta->mac_id);
394
395 /*@[Calculate TX/RX state]*/
396 if (sta->tx_moving_average_tp > (sta->rx_moving_average_tp << 1))
397 ra->txrx_state = TX_STATE;
398 else if (sta->rx_moving_average_tp > (sta->tx_moving_average_tp << 1))
399 ra->txrx_state = RX_STATE;
400 else
401 ra->txrx_state = BI_DIRECTION_STATE;
402
403 ra->is_noisy = dm->noisy_decision;
404 }
405
phydm_common_info_self_update(struct dm_struct * dm)406 void phydm_common_info_self_update(struct dm_struct *dm)
407 {
408 u8 sta_cnt = 0, num_active_client = 0;
409 u32 i, one_entry_macid = 0;
410 u32 ma_rx_tp = 0;
411 u32 tp_diff = 0;
412 struct cmn_sta_info *sta;
413 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
414 PADAPTER adapter = (PADAPTER)dm->adapter;
415 PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
416
417 sta = dm->phydm_sta_info[0];
418
419 /* STA mode is linked to AP */
420 if (is_sta_active(sta) && !ACTING_AS_AP(adapter))
421 dm->bsta_state = true;
422 else
423 dm->bsta_state = false;
424 #endif
425
426 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
427 sta = dm->phydm_sta_info[i];
428 if (is_sta_active(sta)) {
429 sta_cnt++;
430
431 if (sta_cnt == 1)
432 one_entry_macid = i;
433
434 phydm_cmn_sta_info_update(dm, (u8)i);
435 #ifdef PHYDM_BEAMFORMING_SUPPORT
436 /*@phydm_get_txbf_device_num(dm, (u8)i);*/
437 #endif
438
439 ma_rx_tp = sta->rx_moving_average_tp +
440 sta->tx_moving_average_tp;
441
442 PHYDM_DBG(dm, DBG_COMMON_FLOW,
443 "TP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp);
444
445 if (ma_rx_tp > ACTIVE_TP_THRESHOLD)
446 num_active_client++;
447 }
448 }
449
450 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
451 dm->is_linked = (sta_cnt != 0) ? true : false;
452 #endif
453
454 if (sta_cnt == 1) {
455 dm->is_one_entry_only = true;
456 dm->one_entry_macid = one_entry_macid;
457 dm->one_entry_tp = ma_rx_tp;
458
459 dm->tp_active_occur = 0;
460
461 PHYDM_DBG(dm, DBG_COMMON_FLOW,
462 "one_entry_tp=((%d)), pre_one_entry_tp=((%d))\n",
463 dm->one_entry_tp, dm->pre_one_entry_tp);
464
465 if (dm->one_entry_tp > dm->pre_one_entry_tp &&
466 dm->pre_one_entry_tp <= 2) {
467 tp_diff = dm->one_entry_tp - dm->pre_one_entry_tp;
468
469 if (tp_diff > dm->tp_active_th)
470 dm->tp_active_occur = 1;
471 }
472 dm->pre_one_entry_tp = dm->one_entry_tp;
473 } else {
474 dm->is_one_entry_only = false;
475 }
476
477 dm->pre_number_linked_client = dm->number_linked_client;
478 dm->pre_number_active_client = dm->number_active_client;
479
480 dm->number_linked_client = sta_cnt;
481 dm->number_active_client = num_active_client;
482
483 /*Traffic load information update*/
484 phydm_traffic_load_decision(dm);
485
486 dm->phydm_sys_up_time += PHYDM_WATCH_DOG_PERIOD;
487
488 dm->is_dfs_band = phydm_is_dfs_band(dm);
489 dm->phy_dbg_info.show_phy_sts_cnt = 0;
490
491 /*[Link Status Check]*/
492 dm->first_connect = dm->is_linked && !dm->pre_is_linked;
493 dm->first_disconnect = !dm->is_linked && dm->pre_is_linked;
494 dm->pre_is_linked = dm->is_linked;
495 }
496
phydm_common_info_self_reset(struct dm_struct * dm)497 void phydm_common_info_self_reset(struct dm_struct *dm)
498 {
499 struct odm_phy_dbg_info *dbg_t = &dm->phy_dbg_info;
500
501 dbg_t->beacon_cnt_in_period = dbg_t->num_qry_beacon_pkt;
502 dbg_t->num_qry_beacon_pkt = 0;
503
504 dm->rxsc_l = 0xff;
505 dm->rxsc_20 = 0xff;
506 dm->rxsc_40 = 0xff;
507 dm->rxsc_80 = 0xff;
508 }
509
510 void *
phydm_get_structure(struct dm_struct * dm,u8 structure_type)511 phydm_get_structure(struct dm_struct *dm, u8 structure_type)
512
513 {
514 void *structure = NULL;
515
516 switch (structure_type) {
517 case PHYDM_FALSEALMCNT:
518 structure = &dm->false_alm_cnt;
519 break;
520
521 case PHYDM_CFOTRACK:
522 structure = &dm->dm_cfo_track;
523 break;
524
525 case PHYDM_ADAPTIVITY:
526 structure = &dm->adaptivity;
527 break;
528 #ifdef CONFIG_PHYDM_DFS_MASTER
529 case PHYDM_DFS:
530 structure = &dm->dfs;
531 break;
532 #endif
533 default:
534 break;
535 }
536
537 return structure;
538 }
539
phydm_phy_info_update(struct dm_struct * dm)540 void phydm_phy_info_update(struct dm_struct *dm)
541 {
542 #if (RTL8822B_SUPPORT)
543 if (dm->support_ic_type == ODM_RTL8822B)
544 dm->phy_dbg_info.condi_num = phydm_get_condi_num_8822b(dm);
545 #endif
546 }
547
phydm_hw_setting(struct dm_struct * dm)548 void phydm_hw_setting(struct dm_struct *dm)
549 {
550 #if (RTL8821A_SUPPORT)
551 if (dm->support_ic_type & ODM_RTL8821)
552 odm_hw_setting_8821a(dm);
553 #endif
554
555 #if (RTL8814A_SUPPORT)
556 if (dm->support_ic_type & ODM_RTL8814A)
557 phydm_hwsetting_8814a(dm);
558 #endif
559
560 #if (RTL8822B_SUPPORT)
561 if (dm->support_ic_type & ODM_RTL8822B)
562 phydm_hwsetting_8822b(dm);
563 #endif
564
565 #if (RTL8812A_SUPPORT)
566 if (dm->support_ic_type & ODM_RTL8812)
567 phydm_hwsetting_8812a(dm);
568 #endif
569
570 #if (RTL8197F_SUPPORT)
571 if (dm->support_ic_type & ODM_RTL8197F)
572 phydm_hwsetting_8197f(dm);
573 #endif
574
575 #if (RTL8192F_SUPPORT)
576 if (dm->support_ic_type & ODM_RTL8192F)
577 phydm_hwsetting_8192f(dm);
578 #endif
579
580 #if (RTL8822C_SUPPORT)
581 if (dm->support_ic_type & ODM_RTL8822C)
582 phydm_hwsetting_8822c(dm);
583 #endif
584
585 #if (RTL8197G_SUPPORT)
586 if (dm->support_ic_type & ODM_RTL8197G)
587 phydm_hwsetting_8197g(dm);
588 #endif
589
590 #if (RTL8723F_SUPPORT)
591 if (dm->support_ic_type & ODM_RTL8723F)
592 phydm_hwsetting_8723f(dm);
593 #endif
594
595 #if (RTL8821C_SUPPORT)
596 if (dm->support_ic_type & ODM_RTL8821C)
597 phydm_hwsetting_8821c(dm);
598 #endif
599
600 #if (RTL8812F_SUPPORT)
601 if (dm->support_ic_type & ODM_RTL8812F)
602 phydm_hwsetting_8812f(dm);
603 #endif
604
605 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
606 phydm_cck_rx_pathdiv_watchdog(dm);
607 #endif
608 }
609
610 __odm_func__
phydm_chk_bb_rf_pkg_set_valid(struct dm_struct * dm)611 boolean phydm_chk_bb_rf_pkg_set_valid(struct dm_struct *dm)
612 {
613 boolean valid = true;
614
615 if (dm->support_ic_type == ODM_RTL8822C) {
616 #if (RTL8822C_SUPPORT)
617 valid = phydm_chk_pkg_set_valid_8822c(dm,
618 RELEASE_VERSION_8822C,
619 RF_RELEASE_VERSION_8822C);
620 #else
621 valid = true; /*@Just for preventing compile warnings*/
622 #endif
623 #if (RTL8812F_SUPPORT)
624 } else if (dm->support_ic_type == ODM_RTL8812F) {
625 valid = phydm_chk_pkg_set_valid_8812f(dm,
626 RELEASE_VERSION_8812F,
627 RF_RELEASE_VERSION_8812F);
628 #endif
629 #if (RTL8197G_SUPPORT)
630 } else if (dm->support_ic_type == ODM_RTL8197G) {
631 valid = phydm_chk_pkg_set_valid_8197g(dm,
632 RELEASE_VERSION_8197G,
633 RF_RELEASE_VERSION_8197G);
634 #endif
635 #if (RTL8812F_SUPPORT)
636 } else if (dm->support_ic_type == ODM_RTL8812F) {
637 valid = phydm_chk_pkg_set_valid_8812f(dm,
638 RELEASE_VERSION_8812F,
639 RF_RELEASE_VERSION_8812F);
640 #endif
641 #if (RTL8198F_SUPPORT)
642 } else if (dm->support_ic_type == ODM_RTL8198F) {
643 valid = phydm_chk_pkg_set_valid_8198f(dm,
644 RELEASE_VERSION_8198F,
645 RF_RELEASE_VERSION_8198F);
646 #endif
647 #if (RTL8814B_SUPPORT)
648 } else if (dm->support_ic_type == ODM_RTL8814B) {
649 valid = phydm_chk_pkg_set_valid_8814b(dm,
650 RELEASE_VERSION_8814B,
651 RF_RELEASE_VERSION_8814B);
652 #endif
653 #if (RTL8723F_SUPPORT)
654 } else if (dm->support_ic_type == ODM_RTL8723F) {
655 valid = phydm_chk_pkg_set_valid_8723f(dm,
656 RELEASE_VERSION_8723F,
657 RF_RELEASE_VERSION_8723F);
658 #endif
659 }
660
661 return valid;
662 }
663
664 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
phydm_supportability_init_win(void * dm_void)665 u64 phydm_supportability_init_win(
666 void *dm_void)
667 {
668 struct dm_struct *dm = (struct dm_struct *)dm_void;
669 u64 support_ability = 0;
670
671 switch (dm->support_ic_type) {
672 /*@---------------N Series--------------------*/
673 #if (RTL8188E_SUPPORT)
674 case ODM_RTL8188E:
675 support_ability |=
676 ODM_BB_DIG |
677 ODM_BB_RA_MASK |
678 /*ODM_BB_DYNAMIC_TXPWR |*/
679 ODM_BB_FA_CNT |
680 ODM_BB_RSSI_MONITOR |
681 ODM_BB_CCK_PD |
682 /*ODM_BB_PWR_TRAIN |*/
683 ODM_BB_RATE_ADAPTIVE |
684 ODM_BB_ADAPTIVITY |
685 ODM_BB_CFO_TRACKING |
686 ODM_BB_ENV_MONITOR |
687 ODM_BB_PRIMARY_CCA;
688 break;
689 #endif
690
691 #if (RTL8192E_SUPPORT)
692 case ODM_RTL8192E:
693 support_ability |=
694 ODM_BB_DIG |
695 ODM_BB_RA_MASK |
696 /*ODM_BB_DYNAMIC_TXPWR |*/
697 ODM_BB_FA_CNT |
698 ODM_BB_RSSI_MONITOR |
699 ODM_BB_CCK_PD |
700 /*ODM_BB_PWR_TRAIN |*/
701 ODM_BB_RATE_ADAPTIVE |
702 ODM_BB_ADAPTIVITY |
703 ODM_BB_CFO_TRACKING |
704 ODM_BB_ENV_MONITOR |
705 ODM_BB_PRIMARY_CCA;
706 break;
707 #endif
708
709 #if (RTL8723B_SUPPORT)
710 case ODM_RTL8723B:
711 support_ability |=
712 ODM_BB_DIG |
713 ODM_BB_RA_MASK |
714 /*ODM_BB_DYNAMIC_TXPWR |*/
715 ODM_BB_FA_CNT |
716 ODM_BB_RSSI_MONITOR |
717 ODM_BB_CCK_PD |
718 /*ODM_BB_PWR_TRAIN |*/
719 ODM_BB_RATE_ADAPTIVE |
720 ODM_BB_ADAPTIVITY |
721 ODM_BB_CFO_TRACKING |
722 ODM_BB_ENV_MONITOR |
723 ODM_BB_PRIMARY_CCA;
724 break;
725 #endif
726
727 #if (RTL8703B_SUPPORT)
728 case ODM_RTL8703B:
729 support_ability |=
730 ODM_BB_DIG |
731 ODM_BB_RA_MASK |
732 /*ODM_BB_DYNAMIC_TXPWR |*/
733 ODM_BB_FA_CNT |
734 ODM_BB_RSSI_MONITOR |
735 ODM_BB_CCK_PD |
736 /*ODM_BB_PWR_TRAIN |*/
737 ODM_BB_RATE_ADAPTIVE |
738 ODM_BB_ADAPTIVITY |
739 ODM_BB_CFO_TRACKING |
740 ODM_BB_ENV_MONITOR;
741 break;
742 #endif
743
744 #if (RTL8723D_SUPPORT)
745 case ODM_RTL8723D:
746 support_ability |=
747 ODM_BB_DIG |
748 ODM_BB_RA_MASK |
749 /*ODM_BB_DYNAMIC_TXPWR |*/
750 ODM_BB_FA_CNT |
751 ODM_BB_RSSI_MONITOR |
752 ODM_BB_CCK_PD |
753 ODM_BB_PWR_TRAIN |
754 ODM_BB_RATE_ADAPTIVE |
755 ODM_BB_ADAPTIVITY |
756 ODM_BB_CFO_TRACKING |
757 ODM_BB_ENV_MONITOR;
758 break;
759 #endif
760
761 #if (RTL8710B_SUPPORT)
762 case ODM_RTL8710B:
763 support_ability |=
764 ODM_BB_DIG |
765 ODM_BB_RA_MASK |
766 /*ODM_BB_DYNAMIC_TXPWR |*/
767 ODM_BB_FA_CNT |
768 ODM_BB_RSSI_MONITOR |
769 ODM_BB_CCK_PD |
770 ODM_BB_PWR_TRAIN |
771 ODM_BB_RATE_ADAPTIVE |
772 ODM_BB_ADAPTIVITY |
773 ODM_BB_CFO_TRACKING |
774 ODM_BB_ENV_MONITOR;
775 break;
776 #endif
777
778 #if (RTL8188F_SUPPORT)
779 case ODM_RTL8188F:
780 support_ability |=
781 ODM_BB_DIG |
782 ODM_BB_RA_MASK |
783 /*ODM_BB_DYNAMIC_TXPWR |*/
784 ODM_BB_FA_CNT |
785 ODM_BB_RSSI_MONITOR |
786 ODM_BB_CCK_PD |
787 /*ODM_BB_PWR_TRAIN |*/
788 ODM_BB_RATE_ADAPTIVE |
789 ODM_BB_ADAPTIVITY |
790 ODM_BB_CFO_TRACKING |
791 ODM_BB_ENV_MONITOR;
792 break;
793 #endif
794
795 #if (RTL8192F_SUPPORT)
796 case ODM_RTL8192F:
797 support_ability |=
798 ODM_BB_DIG |
799 ODM_BB_RA_MASK |
800 ODM_BB_FA_CNT |
801 ODM_BB_RSSI_MONITOR |
802 ODM_BB_CCK_PD |
803 ODM_BB_PWR_TRAIN |
804 ODM_BB_RATE_ADAPTIVE |
805 /*ODM_BB_PATH_DIV |*/
806 ODM_BB_ADAPTIVITY |
807 ODM_BB_CFO_TRACKING |
808 ODM_BB_ADAPTIVE_SOML |
809 ODM_BB_ENV_MONITOR;
810 /*ODM_BB_LNA_SAT_CHK |*/
811 /*ODM_BB_PRIMARY_CCA*/
812
813 break;
814 #endif
815
816 /*@---------------AC Series-------------------*/
817
818 #if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
819 case ODM_RTL8812:
820 case ODM_RTL8821:
821 support_ability |=
822 ODM_BB_DIG |
823 ODM_BB_RA_MASK |
824 ODM_BB_DYNAMIC_TXPWR |
825 ODM_BB_FA_CNT |
826 ODM_BB_RSSI_MONITOR |
827 ODM_BB_CCK_PD |
828 /*ODM_BB_PWR_TRAIN |*/
829 ODM_BB_RATE_ADAPTIVE |
830 ODM_BB_ADAPTIVITY |
831 ODM_BB_CFO_TRACKING |
832 ODM_BB_ENV_MONITOR;
833 break;
834 #endif
835
836 #if (RTL8814A_SUPPORT)
837 case ODM_RTL8814A:
838 support_ability |=
839 ODM_BB_DIG |
840 ODM_BB_RA_MASK |
841 ODM_BB_DYNAMIC_TXPWR |
842 ODM_BB_FA_CNT |
843 ODM_BB_RSSI_MONITOR |
844 ODM_BB_CCK_PD |
845 /*ODM_BB_PWR_TRAIN |*/
846 ODM_BB_RATE_ADAPTIVE |
847 ODM_BB_ADAPTIVITY |
848 ODM_BB_CFO_TRACKING |
849 ODM_BB_ENV_MONITOR;
850 break;
851 #endif
852
853 #if (RTL8822B_SUPPORT)
854 case ODM_RTL8822B:
855 support_ability |=
856 ODM_BB_DIG |
857 ODM_BB_RA_MASK |
858 /*ODM_BB_DYNAMIC_TXPWR |*/
859 ODM_BB_FA_CNT |
860 ODM_BB_RSSI_MONITOR |
861 ODM_BB_CCK_PD |
862 /*ODM_BB_PWR_TRAIN |*/
863 /*ODM_BB_ADAPTIVE_SOML |*/
864 ODM_BB_RATE_ADAPTIVE |
865 /*ODM_BB_PATH_DIV |*/
866 ODM_BB_ADAPTIVITY |
867 ODM_BB_CFO_TRACKING |
868 ODM_BB_ENV_MONITOR;
869 break;
870 #endif
871
872 #if (RTL8821C_SUPPORT)
873 case ODM_RTL8821C:
874 support_ability |=
875 ODM_BB_DIG |
876 ODM_BB_RA_MASK |
877 /*ODM_BB_DYNAMIC_TXPWR |*/
878 ODM_BB_FA_CNT |
879 ODM_BB_RSSI_MONITOR |
880 ODM_BB_CCK_PD |
881 /*ODM_BB_PWR_TRAIN |*/
882 ODM_BB_RATE_ADAPTIVE |
883 ODM_BB_ADAPTIVITY |
884 ODM_BB_CFO_TRACKING |
885 ODM_BB_ENV_MONITOR;
886 break;
887 #endif
888
889 /*@---------------JGR3 Series-------------------*/
890
891 #if (RTL8822C_SUPPORT)
892 case ODM_RTL8822C:
893 support_ability |=
894 ODM_BB_DIG |
895 ODM_BB_RA_MASK |
896 ODM_BB_DYNAMIC_TXPWR |
897 ODM_BB_FA_CNT |
898 ODM_BB_RSSI_MONITOR |
899 ODM_BB_CCK_PD |
900 ODM_BB_RATE_ADAPTIVE |
901 ODM_BB_PATH_DIV |
902 ODM_BB_ADAPTIVITY |
903 ODM_BB_CFO_TRACKING |
904 ODM_BB_ENV_MONITOR;
905 break;
906 #endif
907
908 #if (RTL8814B_SUPPORT)
909 case ODM_RTL8814B:
910 support_ability |=
911 ODM_BB_DIG |
912 ODM_BB_RA_MASK |
913 /*ODM_BB_DYNAMIC_TXPWR |*/
914 ODM_BB_FA_CNT |
915 ODM_BB_RSSI_MONITOR |
916 ODM_BB_CCK_PD |
917 /*ODM_BB_PWR_TRAIN |*/
918 ODM_BB_RATE_ADAPTIVE |
919 ODM_BB_ADAPTIVITY |
920 ODM_BB_CFO_TRACKING;
921 /*ODM_BB_ENV_MONITOR;*/
922 break;
923 #endif
924
925 #if (RTL8723F_SUPPORT)
926 case ODM_RTL8723F:
927 support_ability |=
928 ODM_BB_DIG |
929 ODM_BB_RA_MASK |
930 /* ODM_BB_DYNAMIC_TXPWR |*/
931 ODM_BB_FA_CNT |
932 ODM_BB_RSSI_MONITOR |
933 ODM_BB_CCK_PD |
934 /*ODM_BB_PWR_TRAIN |*/
935 ODM_BB_RATE_ADAPTIVE |
936 ODM_BB_ADAPTIVITY |
937 ODM_BB_CFO_TRACKING |
938 ODM_BB_ENV_MONITOR;
939 break;
940 #endif
941 default:
942 support_ability |=
943 ODM_BB_DIG |
944 ODM_BB_RA_MASK |
945 /*ODM_BB_DYNAMIC_TXPWR |*/
946 ODM_BB_FA_CNT |
947 ODM_BB_RSSI_MONITOR |
948 ODM_BB_CCK_PD |
949 /*ODM_BB_PWR_TRAIN |*/
950 ODM_BB_RATE_ADAPTIVE |
951 ODM_BB_ADAPTIVITY |
952 ODM_BB_CFO_TRACKING |
953 ODM_BB_ENV_MONITOR;
954
955 pr_debug("[Warning] Supportability Init Warning !!!\n");
956 break;
957 }
958
959 return support_ability;
960 }
961 #endif
962
963 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
phydm_supportability_init_ce(void * dm_void)964 u64 phydm_supportability_init_ce(void *dm_void)
965 {
966 struct dm_struct *dm = (struct dm_struct *)dm_void;
967 u64 support_ability = 0;
968
969 switch (dm->support_ic_type) {
970 /*@---------------N Series--------------------*/
971 #if (RTL8188E_SUPPORT)
972 case ODM_RTL8188E:
973 support_ability |=
974 ODM_BB_DIG |
975 ODM_BB_RA_MASK |
976 /*@ODM_BB_DYNAMIC_TXPWR |*/
977 ODM_BB_FA_CNT |
978 ODM_BB_RSSI_MONITOR |
979 ODM_BB_CCK_PD |
980 /*@ODM_BB_PWR_TRAIN |*/
981 ODM_BB_RATE_ADAPTIVE |
982 ODM_BB_ADAPTIVITY |
983 ODM_BB_CFO_TRACKING |
984 ODM_BB_ENV_MONITOR |
985 ODM_BB_PRIMARY_CCA;
986 break;
987 #endif
988
989 #if (RTL8192E_SUPPORT)
990 case ODM_RTL8192E:
991 support_ability |=
992 ODM_BB_DIG |
993 ODM_BB_RA_MASK |
994 /*@ODM_BB_DYNAMIC_TXPWR |*/
995 ODM_BB_FA_CNT |
996 ODM_BB_RSSI_MONITOR |
997 ODM_BB_CCK_PD |
998 /*@ODM_BB_PWR_TRAIN |*/
999 ODM_BB_RATE_ADAPTIVE |
1000 ODM_BB_ADAPTIVITY |
1001 ODM_BB_CFO_TRACKING |
1002 ODM_BB_ENV_MONITOR |
1003 ODM_BB_PRIMARY_CCA;
1004 break;
1005 #endif
1006
1007 #if (RTL8723B_SUPPORT)
1008 case ODM_RTL8723B:
1009 support_ability |=
1010 ODM_BB_DIG |
1011 ODM_BB_RA_MASK |
1012 /*@ODM_BB_DYNAMIC_TXPWR |*/
1013 ODM_BB_FA_CNT |
1014 ODM_BB_RSSI_MONITOR |
1015 ODM_BB_CCK_PD |
1016 /*@ODM_BB_PWR_TRAIN |*/
1017 ODM_BB_RATE_ADAPTIVE |
1018 ODM_BB_ADAPTIVITY |
1019 ODM_BB_CFO_TRACKING |
1020 ODM_BB_ENV_MONITOR |
1021 ODM_BB_PRIMARY_CCA;
1022 break;
1023 #endif
1024
1025 #if (RTL8703B_SUPPORT)
1026 case ODM_RTL8703B:
1027 support_ability |=
1028 ODM_BB_DIG |
1029 ODM_BB_RA_MASK |
1030 /*@ODM_BB_DYNAMIC_TXPWR |*/
1031 ODM_BB_FA_CNT |
1032 ODM_BB_RSSI_MONITOR |
1033 ODM_BB_CCK_PD |
1034 /*@ODM_BB_PWR_TRAIN |*/
1035 ODM_BB_RATE_ADAPTIVE |
1036 ODM_BB_ADAPTIVITY |
1037 ODM_BB_CFO_TRACKING |
1038 ODM_BB_ENV_MONITOR;
1039 break;
1040 #endif
1041
1042 #if (RTL8723D_SUPPORT)
1043 case ODM_RTL8723D:
1044 support_ability |=
1045 ODM_BB_DIG |
1046 ODM_BB_RA_MASK |
1047 /*@ODM_BB_DYNAMIC_TXPWR |*/
1048 ODM_BB_FA_CNT |
1049 ODM_BB_RSSI_MONITOR |
1050 ODM_BB_CCK_PD |
1051 ODM_BB_PWR_TRAIN |
1052 ODM_BB_RATE_ADAPTIVE |
1053 ODM_BB_ADAPTIVITY |
1054 ODM_BB_CFO_TRACKING |
1055 ODM_BB_ENV_MONITOR;
1056 break;
1057 #endif
1058
1059 #if (RTL8710B_SUPPORT)
1060 case ODM_RTL8710B:
1061 support_ability |=
1062 ODM_BB_DIG |
1063 ODM_BB_RA_MASK |
1064 /*@ODM_BB_DYNAMIC_TXPWR |*/
1065 ODM_BB_FA_CNT |
1066 ODM_BB_RSSI_MONITOR |
1067 ODM_BB_CCK_PD |
1068 /*@ODM_BB_PWR_TRAIN |*/
1069 ODM_BB_RATE_ADAPTIVE |
1070 ODM_BB_ADAPTIVITY |
1071 ODM_BB_CFO_TRACKING |
1072 ODM_BB_ENV_MONITOR;
1073 break;
1074 #endif
1075
1076 #if (RTL8188F_SUPPORT)
1077 case ODM_RTL8188F:
1078 support_ability |=
1079 ODM_BB_DIG |
1080 ODM_BB_RA_MASK |
1081 /*@ODM_BB_DYNAMIC_TXPWR |*/
1082 ODM_BB_FA_CNT |
1083 ODM_BB_RSSI_MONITOR |
1084 ODM_BB_CCK_PD |
1085 /*@ODM_BB_PWR_TRAIN |*/
1086 ODM_BB_RATE_ADAPTIVE |
1087 ODM_BB_ADAPTIVITY |
1088 ODM_BB_CFO_TRACKING |
1089 ODM_BB_ENV_MONITOR;
1090 break;
1091 #endif
1092
1093 #if (RTL8192F_SUPPORT)
1094 case ODM_RTL8192F:
1095 support_ability |=
1096 ODM_BB_DIG |
1097 ODM_BB_RA_MASK |
1098 ODM_BB_FA_CNT |
1099 ODM_BB_RSSI_MONITOR |
1100 ODM_BB_CCK_PD |
1101 ODM_BB_PWR_TRAIN |
1102 ODM_BB_RATE_ADAPTIVE |
1103 /*ODM_BB_PATH_DIV |*/
1104 ODM_BB_ADAPTIVITY |
1105 ODM_BB_CFO_TRACKING |
1106 /*@ODM_BB_ADAPTIVE_SOML |*/
1107 ODM_BB_ENV_MONITOR;
1108 /*@ODM_BB_LNA_SAT_CHK |*/
1109 /*@ODM_BB_PRIMARY_CCA*/
1110 break;
1111 #endif
1112 /*@---------------AC Series-------------------*/
1113
1114 #if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
1115 case ODM_RTL8812:
1116 case ODM_RTL8821:
1117 support_ability |=
1118 ODM_BB_DIG |
1119 ODM_BB_RA_MASK |
1120 /*@ODM_BB_DYNAMIC_TXPWR |*/
1121 ODM_BB_FA_CNT |
1122 ODM_BB_RSSI_MONITOR |
1123 ODM_BB_CCK_PD |
1124 /*@ODM_BB_PWR_TRAIN |*/
1125 ODM_BB_RATE_ADAPTIVE |
1126 ODM_BB_ADAPTIVITY |
1127 ODM_BB_CFO_TRACKING |
1128 ODM_BB_ENV_MONITOR;
1129 break;
1130 #endif
1131
1132 #if (RTL8814A_SUPPORT)
1133 case ODM_RTL8814A:
1134 support_ability |=
1135 ODM_BB_DIG |
1136 ODM_BB_RA_MASK |
1137 /*@ODM_BB_DYNAMIC_TXPWR |*/
1138 ODM_BB_FA_CNT |
1139 ODM_BB_RSSI_MONITOR |
1140 ODM_BB_CCK_PD |
1141 /*@ODM_BB_PWR_TRAIN |*/
1142 ODM_BB_RATE_ADAPTIVE |
1143 ODM_BB_ADAPTIVITY |
1144 ODM_BB_CFO_TRACKING |
1145 ODM_BB_ENV_MONITOR;
1146 break;
1147 #endif
1148
1149 #if (RTL8822B_SUPPORT)
1150 case ODM_RTL8822B:
1151 support_ability |=
1152 ODM_BB_DIG |
1153 ODM_BB_RA_MASK |
1154 ODM_BB_DYNAMIC_TXPWR |
1155 ODM_BB_FA_CNT |
1156 ODM_BB_RSSI_MONITOR |
1157 ODM_BB_CCK_PD |
1158 /*@ODM_BB_PWR_TRAIN |*/
1159 ODM_BB_RATE_ADAPTIVE |
1160 /*ODM_BB_PATH_DIV |*/
1161 ODM_BB_ADAPTIVITY |
1162 ODM_BB_CFO_TRACKING |
1163 ODM_BB_ENV_MONITOR;
1164 break;
1165 #endif
1166
1167 #if (RTL8821C_SUPPORT)
1168 case ODM_RTL8821C:
1169 support_ability |=
1170 ODM_BB_DIG |
1171 ODM_BB_RA_MASK |
1172 ODM_BB_DYNAMIC_TXPWR |
1173 ODM_BB_FA_CNT |
1174 ODM_BB_RSSI_MONITOR |
1175 ODM_BB_CCK_PD |
1176 /*@ODM_BB_PWR_TRAIN |*/
1177 ODM_BB_RATE_ADAPTIVE |
1178 ODM_BB_ADAPTIVITY |
1179 ODM_BB_CFO_TRACKING |
1180 ODM_BB_ENV_MONITOR;
1181 break;
1182 #endif
1183
1184 /*@---------------JGR3 Series-------------------*/
1185
1186 #if (RTL8822C_SUPPORT)
1187 case ODM_RTL8822C:
1188 support_ability |=
1189 ODM_BB_DIG |
1190 ODM_BB_RA_MASK |
1191 ODM_BB_DYNAMIC_TXPWR |
1192 ODM_BB_FA_CNT |
1193 ODM_BB_RSSI_MONITOR |
1194 ODM_BB_CCK_PD |
1195 ODM_BB_RATE_ADAPTIVE |
1196 /* ODM_BB_PATH_DIV | */
1197 ODM_BB_ADAPTIVITY |
1198 ODM_BB_CFO_TRACKING |
1199 ODM_BB_ENV_MONITOR;
1200 break;
1201 #endif
1202
1203 #if (RTL8814B_SUPPORT)
1204 case ODM_RTL8814B:
1205 support_ability |=
1206 ODM_BB_DIG |
1207 ODM_BB_RA_MASK |
1208 /*@ODM_BB_DYNAMIC_TXPWR |*/
1209 ODM_BB_FA_CNT |
1210 ODM_BB_RSSI_MONITOR |
1211 ODM_BB_CCK_PD |
1212 /*@ODM_BB_PWR_TRAIN |*/
1213 /*ODM_BB_RATE_ADAPTIVE |*/
1214 ODM_BB_ADAPTIVITY |
1215 ODM_BB_CFO_TRACKING;
1216 /*ODM_BB_ENV_MONITOR;*/
1217 break;
1218 #endif
1219 #if (RTL8723F_SUPPORT)
1220 case ODM_RTL8723F:
1221 support_ability |=
1222 ODM_BB_DIG |
1223 ODM_BB_RA_MASK |
1224 ODM_BB_DYNAMIC_TXPWR |
1225 ODM_BB_FA_CNT |
1226 ODM_BB_RSSI_MONITOR |
1227 ODM_BB_CCK_PD |
1228 ODM_BB_RATE_ADAPTIVE |
1229 /* ODM_BB_PATH_DIV | */
1230 ODM_BB_ADAPTIVITY |
1231 ODM_BB_CFO_TRACKING |
1232 ODM_BB_ENV_MONITOR;
1233 break;
1234 #endif
1235 default:
1236 support_ability |=
1237 ODM_BB_DIG |
1238 ODM_BB_RA_MASK |
1239 /*@ODM_BB_DYNAMIC_TXPWR |*/
1240 ODM_BB_FA_CNT |
1241 ODM_BB_RSSI_MONITOR |
1242 ODM_BB_CCK_PD |
1243 /*@ODM_BB_PWR_TRAIN |*/
1244 ODM_BB_RATE_ADAPTIVE |
1245 ODM_BB_ADAPTIVITY |
1246 ODM_BB_CFO_TRACKING |
1247 ODM_BB_ENV_MONITOR;
1248
1249 pr_debug("[Warning] Supportability Init Warning !!!\n");
1250 break;
1251 }
1252
1253 return support_ability;
1254 }
1255 #endif
1256
1257 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
phydm_supportability_init_ap(void * dm_void)1258 u64 phydm_supportability_init_ap(
1259 void *dm_void)
1260 {
1261 struct dm_struct *dm = (struct dm_struct *)dm_void;
1262 u64 support_ability = 0;
1263
1264 switch (dm->support_ic_type) {
1265 /*@---------------N Series--------------------*/
1266 #if (RTL8188E_SUPPORT)
1267 case ODM_RTL8188E:
1268 support_ability |=
1269 ODM_BB_DIG |
1270 ODM_BB_RA_MASK |
1271 ODM_BB_FA_CNT |
1272 ODM_BB_RSSI_MONITOR |
1273 ODM_BB_CCK_PD |
1274 /*ODM_BB_PWR_TRAIN |*/
1275 ODM_BB_RATE_ADAPTIVE |
1276 ODM_BB_ADAPTIVITY |
1277 ODM_BB_CFO_TRACKING |
1278 ODM_BB_ENV_MONITOR |
1279 ODM_BB_PRIMARY_CCA;
1280 break;
1281 #endif
1282
1283 #if (RTL8192E_SUPPORT)
1284 case ODM_RTL8192E:
1285 support_ability |=
1286 ODM_BB_DIG |
1287 ODM_BB_RA_MASK |
1288 ODM_BB_FA_CNT |
1289 ODM_BB_RSSI_MONITOR |
1290 ODM_BB_CCK_PD |
1291 /*ODM_BB_PWR_TRAIN |*/
1292 ODM_BB_RATE_ADAPTIVE |
1293 ODM_BB_ADAPTIVITY |
1294 ODM_BB_CFO_TRACKING |
1295 ODM_BB_ENV_MONITOR |
1296 ODM_BB_PRIMARY_CCA;
1297 break;
1298 #endif
1299
1300 #if (RTL8723B_SUPPORT)
1301 case ODM_RTL8723B:
1302 support_ability |=
1303 ODM_BB_DIG |
1304 ODM_BB_RA_MASK |
1305 ODM_BB_FA_CNT |
1306 ODM_BB_RSSI_MONITOR |
1307 ODM_BB_CCK_PD |
1308 /*ODM_BB_PWR_TRAIN |*/
1309 ODM_BB_RATE_ADAPTIVE |
1310 ODM_BB_ADAPTIVITY |
1311 ODM_BB_CFO_TRACKING |
1312 ODM_BB_ENV_MONITOR;
1313 break;
1314 #endif
1315
1316 #if (RTL8198F_SUPPORT || RTL8197F_SUPPORT)
1317 case ODM_RTL8198F:
1318 support_ability |=
1319 ODM_BB_DIG |
1320 ODM_BB_RA_MASK |
1321 ODM_BB_FA_CNT |
1322 ODM_BB_RSSI_MONITOR |
1323 ODM_BB_CCK_PD |
1324 /*ODM_BB_PWR_TRAIN |*/
1325 /*ODM_BB_RATE_ADAPTIVE |*/
1326 ODM_BB_ADAPTIVITY |
1327 ODM_BB_CFO_TRACKING;
1328 /*ODM_BB_ADAPTIVE_SOML |*/
1329 /*ODM_BB_ENV_MONITOR |*/
1330 /*ODM_BB_LNA_SAT_CHK |*/
1331 /*ODM_BB_PRIMARY_CCA;*/
1332 break;
1333 case ODM_RTL8197F:
1334 support_ability |=
1335 ODM_BB_DIG |
1336 ODM_BB_RA_MASK |
1337 ODM_BB_FA_CNT |
1338 ODM_BB_RSSI_MONITOR |
1339 ODM_BB_CCK_PD |
1340 /*ODM_BB_PWR_TRAIN |*/
1341 ODM_BB_RATE_ADAPTIVE |
1342 ODM_BB_ADAPTIVITY |
1343 ODM_BB_CFO_TRACKING |
1344 ODM_BB_ADAPTIVE_SOML |
1345 ODM_BB_ENV_MONITOR |
1346 ODM_BB_LNA_SAT_CHK |
1347 ODM_BB_PRIMARY_CCA;
1348 break;
1349 #endif
1350
1351 #if (RTL8192F_SUPPORT)
1352 case ODM_RTL8192F:
1353 support_ability |=
1354 ODM_BB_DIG |
1355 ODM_BB_RA_MASK |
1356 ODM_BB_FA_CNT |
1357 ODM_BB_RSSI_MONITOR |
1358 ODM_BB_CCK_PD |
1359 /*ODM_BB_PWR_TRAIN |*/
1360 ODM_BB_RATE_ADAPTIVE |
1361 ODM_BB_ADAPTIVITY |
1362 /*ODM_BB_CFO_TRACKING |*/
1363 ODM_BB_ADAPTIVE_SOML |
1364 /*ODM_BB_PATH_DIV |*/
1365 ODM_BB_ENV_MONITOR |
1366 /*ODM_BB_LNA_SAT_CHK |*/
1367 /*ODM_BB_PRIMARY_CCA |*/
1368 0;
1369 break;
1370 #endif
1371
1372 /*@---------------AC Series-------------------*/
1373
1374 #if (RTL8881A_SUPPORT)
1375 case ODM_RTL8881A:
1376 support_ability |=
1377 ODM_BB_DIG |
1378 ODM_BB_RA_MASK |
1379 ODM_BB_FA_CNT |
1380 ODM_BB_RSSI_MONITOR |
1381 ODM_BB_CCK_PD |
1382 /*ODM_BB_PWR_TRAIN |*/
1383 ODM_BB_RATE_ADAPTIVE |
1384 ODM_BB_ADAPTIVITY |
1385 ODM_BB_CFO_TRACKING |
1386 ODM_BB_ENV_MONITOR;
1387 break;
1388 #endif
1389
1390 #if (RTL8814A_SUPPORT)
1391 case ODM_RTL8814A:
1392 support_ability |=
1393 ODM_BB_DIG |
1394 ODM_BB_RA_MASK |
1395 ODM_BB_FA_CNT |
1396 ODM_BB_RSSI_MONITOR |
1397 ODM_BB_CCK_PD |
1398 /*ODM_BB_PWR_TRAIN |*/
1399 ODM_BB_RATE_ADAPTIVE |
1400 ODM_BB_ADAPTIVITY |
1401 ODM_BB_CFO_TRACKING |
1402 ODM_BB_ENV_MONITOR;
1403 break;
1404 #endif
1405
1406 #if (RTL8822B_SUPPORT)
1407 case ODM_RTL8822B:
1408 support_ability |=
1409 ODM_BB_DIG |
1410 ODM_BB_RA_MASK |
1411 ODM_BB_FA_CNT |
1412 ODM_BB_RSSI_MONITOR |
1413 ODM_BB_CCK_PD |
1414 /*ODM_BB_PWR_TRAIN |*/
1415 /*ODM_BB_ADAPTIVE_SOML |*/
1416 ODM_BB_RATE_ADAPTIVE |
1417 ODM_BB_ADAPTIVITY |
1418 ODM_BB_CFO_TRACKING |
1419 ODM_BB_ENV_MONITOR;
1420 break;
1421 #endif
1422
1423 #if (RTL8821C_SUPPORT)
1424 case ODM_RTL8821C:
1425 support_ability |=
1426 ODM_BB_DIG |
1427 ODM_BB_RA_MASK |
1428 ODM_BB_FA_CNT |
1429 ODM_BB_RSSI_MONITOR |
1430 ODM_BB_CCK_PD |
1431 /*ODM_BB_PWR_TRAIN |*/
1432 ODM_BB_RATE_ADAPTIVE |
1433 ODM_BB_ADAPTIVITY |
1434 ODM_BB_CFO_TRACKING |
1435 ODM_BB_ENV_MONITOR;
1436
1437 break;
1438 #endif
1439
1440 /*@---------------JGR3 Series-------------------*/
1441
1442 #if (RTL8814B_SUPPORT)
1443 case ODM_RTL8814B:
1444 support_ability |=
1445 ODM_BB_DIG |
1446 ODM_BB_RA_MASK |
1447 ODM_BB_FA_CNT |
1448 ODM_BB_RSSI_MONITOR |
1449 ODM_BB_CCK_PD |
1450 /*ODM_BB_PWR_TRAIN |*/
1451 /*ODM_BB_RATE_ADAPTIVE |*/
1452 ODM_BB_ADAPTIVITY |
1453 ODM_BB_CFO_TRACKING |
1454 ODM_BB_ENV_MONITOR;
1455 break;
1456 #endif
1457
1458 #if (RTL8197G_SUPPORT)
1459 case ODM_RTL8197G:
1460 support_ability |=
1461 ODM_BB_DIG |
1462 ODM_BB_RA_MASK |
1463 ODM_BB_FA_CNT |
1464 ODM_BB_RSSI_MONITOR |
1465 ODM_BB_CCK_PD |
1466 /*ODM_BB_PWR_TRAIN |*/
1467 ODM_BB_RATE_ADAPTIVE |
1468 ODM_BB_ADAPTIVITY |
1469 ODM_BB_CFO_TRACKING |
1470 ODM_BB_ENV_MONITOR;
1471 break;
1472 #endif
1473
1474 #if (RTL8812F_SUPPORT)
1475 case ODM_RTL8812F:
1476 support_ability |=
1477 ODM_BB_DIG |
1478 ODM_BB_RA_MASK |
1479 ODM_BB_DYNAMIC_TXPWR |
1480 ODM_BB_FA_CNT |
1481 ODM_BB_RSSI_MONITOR |
1482 /*ODM_BB_CCK_PD |*/
1483 /*ODM_BB_PWR_TRAIN |*/
1484 ODM_BB_RATE_ADAPTIVE |
1485 ODM_BB_ADAPTIVITY |
1486 ODM_BB_CFO_TRACKING |
1487 ODM_BB_ENV_MONITOR;
1488 break;
1489 #endif
1490
1491 #if (RTL8723F_SUPPORT)
1492 case ODM_RTL8723F:
1493 support_ability |=
1494 ODM_BB_DIG |
1495 ODM_BB_RA_MASK |
1496 ODM_BB_FA_CNT |
1497 ODM_BB_RSSI_MONITOR |
1498 ODM_BB_CCK_PD |
1499 /*ODM_BB_PWR_TRAIN |*/
1500 ODM_BB_RATE_ADAPTIVE |
1501 ODM_BB_ADAPTIVITY |
1502 ODM_BB_CFO_TRACKING |
1503 ODM_BB_ENV_MONITOR;
1504 break;
1505 #endif
1506 default:
1507 support_ability |=
1508 ODM_BB_DIG |
1509 ODM_BB_RA_MASK |
1510 ODM_BB_FA_CNT |
1511 ODM_BB_RSSI_MONITOR |
1512 ODM_BB_CCK_PD |
1513 /*ODM_BB_PWR_TRAIN |*/
1514 ODM_BB_RATE_ADAPTIVE |
1515 ODM_BB_ADAPTIVITY |
1516 ODM_BB_CFO_TRACKING |
1517 ODM_BB_ENV_MONITOR;
1518
1519 pr_debug("[Warning] Supportability Init Warning !!!\n");
1520 break;
1521 }
1522
1523 return support_ability;
1524 }
1525 #endif
1526
1527 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
phydm_supportability_init_iot(void * dm_void)1528 u64 phydm_supportability_init_iot(
1529 void *dm_void)
1530 {
1531 struct dm_struct *dm = (struct dm_struct *)dm_void;
1532 u64 support_ability = 0;
1533
1534 switch (dm->support_ic_type) {
1535 #if (RTL8710B_SUPPORT)
1536 case ODM_RTL8710B:
1537 support_ability |=
1538 ODM_BB_DIG |
1539 ODM_BB_RA_MASK |
1540 /*ODM_BB_DYNAMIC_TXPWR |*/
1541 ODM_BB_FA_CNT |
1542 ODM_BB_RSSI_MONITOR |
1543 ODM_BB_CCK_PD |
1544 /*ODM_BB_PWR_TRAIN |*/
1545 ODM_BB_RATE_ADAPTIVE |
1546 ODM_BB_CFO_TRACKING |
1547 ODM_BB_ENV_MONITOR;
1548 break;
1549 #endif
1550
1551 #if (RTL8195A_SUPPORT)
1552 case ODM_RTL8195A:
1553 support_ability |=
1554 ODM_BB_DIG |
1555 ODM_BB_RA_MASK |
1556 /*ODM_BB_DYNAMIC_TXPWR |*/
1557 ODM_BB_FA_CNT |
1558 ODM_BB_RSSI_MONITOR |
1559 ODM_BB_CCK_PD |
1560 /*ODM_BB_PWR_TRAIN |*/
1561 ODM_BB_RATE_ADAPTIVE |
1562 ODM_BB_CFO_TRACKING |
1563 ODM_BB_ENV_MONITOR;
1564 break;
1565 #endif
1566
1567 #if (RTL8195B_SUPPORT)
1568 case ODM_RTL8195B:
1569 support_ability |=
1570 ODM_BB_DIG |
1571 ODM_BB_RA_MASK |
1572 /*ODM_BB_DYNAMIC_TXPWR |*/
1573 ODM_BB_FA_CNT |
1574 ODM_BB_RSSI_MONITOR |
1575 ODM_BB_CCK_PD |
1576 /*ODM_BB_PWR_TRAIN |*/
1577 ODM_BB_RATE_ADAPTIVE |
1578 ODM_BB_ADAPTIVITY |
1579 ODM_BB_CFO_TRACKING |
1580 ODM_BB_ENV_MONITOR;
1581 break;
1582 #endif
1583
1584 #if (RTL8721D_SUPPORT)
1585 case ODM_RTL8721D:
1586 support_ability |=
1587 ODM_BB_DIG |
1588 ODM_BB_RA_MASK |
1589 /*ODM_BB_DYNAMIC_TXPWR |*/
1590 ODM_BB_FA_CNT |
1591 ODM_BB_RSSI_MONITOR |
1592 ODM_BB_CCK_PD |
1593 /*ODM_BB_PWR_TRAIN |*/
1594 ODM_BB_RATE_ADAPTIVE |
1595 ODM_BB_ADAPTIVITY |
1596 ODM_BB_CFO_TRACKING |
1597 ODM_BB_ENV_MONITOR;
1598 break;
1599 #endif
1600
1601 #if (RTL8710C_SUPPORT)
1602 case ODM_RTL8710C:
1603 support_ability |=
1604 ODM_BB_DIG |
1605 ODM_BB_RA_MASK |
1606 /*ODM_BB_DYNAMIC_TXPWR |*/
1607 ODM_BB_FA_CNT |
1608 ODM_BB_RSSI_MONITOR |
1609 ODM_BB_CCK_PD |
1610 /*ODM_BB_PWR_TRAIN |*/
1611 ODM_BB_RATE_ADAPTIVE |
1612 ODM_BB_ADAPTIVITY |
1613 ODM_BB_CFO_TRACKING |
1614 ODM_BB_ENV_MONITOR;
1615 break;
1616 #endif
1617 default:
1618 support_ability |=
1619 ODM_BB_DIG |
1620 ODM_BB_RA_MASK |
1621 /*ODM_BB_DYNAMIC_TXPWR |*/
1622 ODM_BB_FA_CNT |
1623 ODM_BB_RSSI_MONITOR |
1624 ODM_BB_CCK_PD |
1625 /*ODM_BB_PWR_TRAIN |*/
1626 ODM_BB_RATE_ADAPTIVE |
1627 ODM_BB_CFO_TRACKING |
1628 ODM_BB_ENV_MONITOR;
1629
1630 pr_debug("[Warning] Supportability Init Warning !!!\n");
1631 break;
1632 }
1633
1634 return support_ability;
1635 }
1636 #endif
1637
phydm_fwoffload_ability_init(struct dm_struct * dm,enum phydm_offload_ability offload_ability)1638 void phydm_fwoffload_ability_init(struct dm_struct *dm,
1639 enum phydm_offload_ability offload_ability)
1640 {
1641 switch (offload_ability) {
1642 case PHYDM_PHY_PARAM_OFFLOAD:
1643 if (dm->support_ic_type & PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD)
1644 dm->fw_offload_ability |= PHYDM_PHY_PARAM_OFFLOAD;
1645 break;
1646
1647 case PHYDM_RF_IQK_OFFLOAD:
1648 dm->fw_offload_ability |= PHYDM_RF_IQK_OFFLOAD;
1649 break;
1650
1651 case PHYDM_RF_DPK_OFFLOAD:
1652 dm->fw_offload_ability |= PHYDM_RF_DPK_OFFLOAD;
1653 break;
1654
1655 default:
1656 PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
1657 break;
1658 }
1659
1660 PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
1661 dm->fw_offload_ability);
1662 }
1663
phydm_fwoffload_ability_clear(struct dm_struct * dm,enum phydm_offload_ability offload_ability)1664 void phydm_fwoffload_ability_clear(struct dm_struct *dm,
1665 enum phydm_offload_ability offload_ability)
1666 {
1667 switch (offload_ability) {
1668 case PHYDM_PHY_PARAM_OFFLOAD:
1669 if (dm->support_ic_type & PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD)
1670 dm->fw_offload_ability &= (~PHYDM_PHY_PARAM_OFFLOAD);
1671 break;
1672
1673 case PHYDM_RF_IQK_OFFLOAD:
1674 dm->fw_offload_ability &= (~PHYDM_RF_IQK_OFFLOAD);
1675 break;
1676
1677 case PHYDM_RF_DPK_OFFLOAD:
1678 dm->fw_offload_ability &= (~PHYDM_RF_DPK_OFFLOAD);
1679 break;
1680
1681 default:
1682 PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
1683 break;
1684 }
1685
1686 PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
1687 dm->fw_offload_ability);
1688 }
1689
phydm_supportability_init(void * dm_void)1690 void phydm_supportability_init(void *dm_void)
1691 {
1692 struct dm_struct *dm = (struct dm_struct *)dm_void;
1693 u64 support_ability;
1694
1695 if (dm->manual_supportability &&
1696 *dm->manual_supportability != 0xffffffff) {
1697 support_ability = *dm->manual_supportability;
1698 } else if (*dm->mp_mode) {
1699 support_ability = 0;
1700 } else {
1701 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1702 support_ability = phydm_supportability_init_win(dm);
1703 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1704 support_ability = phydm_supportability_init_ap(dm);
1705 #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
1706 support_ability = phydm_supportability_init_ce(dm);
1707 #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
1708 support_ability = phydm_supportability_init_iot(dm);
1709 #endif
1710
1711 /*@[Config Antenna Diversity]*/
1712 if (IS_FUNC_EN(dm->enable_antdiv))
1713 support_ability |= ODM_BB_ANT_DIV;
1714
1715 /*@[Config TXpath Diversity]*/
1716 if (IS_FUNC_EN(dm->enable_pathdiv))
1717 support_ability |= ODM_BB_PATH_DIV;
1718
1719 /*@[Config Adaptive SOML]*/
1720 if (IS_FUNC_EN(dm->en_adap_soml))
1721 support_ability |= ODM_BB_ADAPTIVE_SOML;
1722
1723 /*@[DYNAMIC_TXPWR and TSSI cannot coexist]*/
1724 if(IS_FUNC_EN(&dm->en_tssi_mode) &&
1725 (dm->support_ic_type & ODM_RTL8822C))
1726 support_ability &= ~ODM_BB_DYNAMIC_TXPWR;
1727
1728 }
1729 dm->support_ability = support_ability;
1730 PHYDM_DBG(dm, ODM_COMP_INIT, "IC=0x%x, mp=%d, Supportability=0x%llx\n",
1731 dm->support_ic_type, *dm->mp_mode, dm->support_ability);
1732 }
1733
phydm_rfe_init(void * dm_void)1734 void phydm_rfe_init(void *dm_void)
1735 {
1736 struct dm_struct *dm = (struct dm_struct *)dm_void;
1737
1738 PHYDM_DBG(dm, ODM_COMP_INIT, "RFE_Init\n");
1739 #if (RTL8822B_SUPPORT == 1)
1740 if (dm->support_ic_type == ODM_RTL8822B)
1741 phydm_rfe_8822b_init(dm);
1742 #endif
1743 }
1744
1745 #ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
phydm_tx_collsion_th_init(void * dm_void)1746 void phydm_tx_collsion_th_init(void *dm_void)
1747 {
1748
1749 struct dm_struct *dm = (struct dm_struct *)dm_void;
1750
1751 #if (RTL8197G_SUPPORT)
1752 if (dm->support_ic_type & ODM_RTL8197G)
1753 phydm_tx_collsion_th_init_8197g(dm);
1754 #endif
1755
1756 #if (RTL8812F_SUPPORT)
1757 if (dm->support_ic_type & ODM_RTL8812F)
1758 phydm_tx_collsion_th_init_8812f(dm);
1759 #endif
1760
1761 }
1762
phydm_tx_collsion_th_set(void * dm_void,u8 val_r2t,u8 val_t2r)1763 void phydm_tx_collsion_th_set(void *dm_void, u8 val_r2t, u8 val_t2r)
1764 {
1765 struct dm_struct *dm = (struct dm_struct *)dm_void;
1766
1767 #if (RTL8197G_SUPPORT)
1768 if (dm->support_ic_type & ODM_RTL8197G)
1769 phydm_tx_collsion_th_set_8197g(dm, val_r2t, val_t2r);
1770 #endif
1771
1772 #if (RTL8812F_SUPPORT)
1773 if (dm->support_ic_type & ODM_RTL8812F)
1774 phydm_tx_collsion_th_set_8812f(dm, val_r2t, val_t2r);
1775 #endif
1776
1777 }
1778 #endif
1779
phydm_dm_early_init(struct dm_struct * dm)1780 void phydm_dm_early_init(struct dm_struct *dm)
1781 {
1782 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1783 phydm_init_debug_setting(dm);
1784 #endif
1785 }
1786
odm_dm_init(struct dm_struct * dm)1787 enum phydm_init_result odm_dm_init(struct dm_struct *dm)
1788 {
1789 enum phydm_init_result result = PHYDM_INIT_SUCCESS;
1790
1791 if (!phydm_chk_bb_rf_pkg_set_valid(dm)) {
1792 pr_debug("[Warning][%s] Init fail\n", __func__);
1793 return PHYDM_INIT_FAIL_BBRF_REG_INVALID;
1794 }
1795
1796 halrf_init(dm);
1797 phydm_supportability_init(dm);
1798 phydm_pause_func_init(dm);
1799 phydm_rfe_init(dm);
1800 phydm_common_info_self_init(dm);
1801 phydm_rx_phy_status_init(dm);
1802 #ifdef PHYDM_AUTO_DEGBUG
1803 phydm_auto_dbg_engine_init(dm);
1804 #endif
1805 phydm_dig_init(dm);
1806 #ifdef PHYDM_SUPPORT_CCKPD
1807 #ifdef PHYDM_DCC_ENHANCE
1808 phydm_dig_cckpd_coex_init(dm);
1809 #endif
1810 phydm_cck_pd_init(dm);
1811 #endif
1812 phydm_env_monitor_init(dm);
1813 phydm_enhance_monitor_init(dm);
1814 phydm_adaptivity_init(dm);
1815 phydm_ra_info_init(dm);
1816 phydm_rssi_monitor_init(dm);
1817 phydm_cfo_tracking_init(dm);
1818 phydm_rf_init(dm);
1819 phydm_dc_cancellation(dm);
1820 #ifdef PHYDM_TXA_CALIBRATION
1821 phydm_txcurrentcalibration(dm);
1822 phydm_get_pa_bias_offset(dm);
1823 #endif
1824 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1825 odm_antenna_diversity_init(dm);
1826 #endif
1827 #ifdef CONFIG_ADAPTIVE_SOML
1828 phydm_adaptive_soml_init(dm);
1829 #endif
1830 #ifdef CONFIG_PATH_DIVERSITY
1831 phydm_tx_path_diversity_init(dm);
1832 #endif
1833 #ifdef CONFIG_DYNAMIC_TX_TWR
1834 phydm_dynamic_tx_power_init(dm);
1835 #endif
1836 #if (PHYDM_LA_MODE_SUPPORT)
1837 phydm_la_init(dm);
1838 #endif
1839
1840 #ifdef PHYDM_BEAMFORMING_VERSION1
1841 phydm_beamforming_init(dm);
1842 #endif
1843
1844 #if (RTL8188E_SUPPORT)
1845 odm_ra_info_init_all(dm);
1846 #endif
1847 #ifdef PHYDM_PRIMARY_CCA
1848 phydm_primary_cca_init(dm);
1849 #endif
1850 #ifdef CONFIG_PSD_TOOL
1851 phydm_psd_init(dm);
1852 #endif
1853
1854 #ifdef CONFIG_SMART_ANTENNA
1855 phydm_smt_ant_init(dm);
1856 #endif
1857 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
1858 phydm_lna_sat_check_init(dm);
1859 #endif
1860 #ifdef CONFIG_MCC_DM
1861 phydm_mcc_init(dm);
1862 #endif
1863
1864 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
1865 phydm_cck_rx_pathdiv_init(dm);
1866 #endif
1867
1868 #ifdef CONFIG_MU_RSOML
1869 phydm_mu_rsoml_init(dm);
1870 #endif
1871
1872 #ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
1873 phydm_tx_collsion_th_init(dm);
1874 #endif
1875
1876 return result;
1877 }
1878
odm_dm_reset(struct dm_struct * dm)1879 void odm_dm_reset(struct dm_struct *dm)
1880 {
1881 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1882 odm_ant_div_reset(dm);
1883 #endif
1884 phydm_set_edcca_threshold_api(dm);
1885 }
1886
phydm_supportability_en(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)1887 void phydm_supportability_en(void *dm_void, char input[][16], u32 *_used,
1888 char *output, u32 *_out_len)
1889 {
1890 struct dm_struct *dm = (struct dm_struct *)dm_void;
1891 u32 dm_value[10] = {0};
1892 u64 pre_support_ability, one = 1;
1893 u64 comp = 0;
1894 u32 used = *_used;
1895 u32 out_len = *_out_len;
1896 u8 i;
1897
1898 for (i = 0; i < 5; i++) {
1899 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);
1900 }
1901
1902 pre_support_ability = dm->support_ability;
1903 comp = dm->support_ability;
1904
1905 PDM_SNPF(out_len, used, output + used, out_len - used,
1906 "\n================================\n");
1907
1908 if (dm_value[0] == 100) {
1909 PDM_SNPF(out_len, used, output + used, out_len - used,
1910 "[Supportability] PhyDM Selection\n");
1911 PDM_SNPF(out_len, used, output + used, out_len - used,
1912 "================================\n");
1913 PDM_SNPF(out_len, used, output + used, out_len - used,
1914 "00. (( %s ))DIG\n",
1915 ((comp & ODM_BB_DIG) ? ("V") : (".")));
1916 PDM_SNPF(out_len, used, output + used, out_len - used,
1917 "01. (( %s ))RA_MASK\n",
1918 ((comp & ODM_BB_RA_MASK) ? ("V") : (".")));
1919 PDM_SNPF(out_len, used, output + used, out_len - used,
1920 "02. (( %s ))DYN_TXPWR\n",
1921 ((comp & ODM_BB_DYNAMIC_TXPWR) ? ("V") : (".")));
1922 PDM_SNPF(out_len, used, output + used, out_len - used,
1923 "03. (( %s ))FA_CNT\n",
1924 ((comp & ODM_BB_FA_CNT) ? ("V") : (".")));
1925 PDM_SNPF(out_len, used, output + used, out_len - used,
1926 "04. (( %s ))RSSI_MNTR\n",
1927 ((comp & ODM_BB_RSSI_MONITOR) ? ("V") : (".")));
1928 PDM_SNPF(out_len, used, output + used, out_len - used,
1929 "05. (( %s ))CCK_PD\n",
1930 ((comp & ODM_BB_CCK_PD) ? ("V") : (".")));
1931 PDM_SNPF(out_len, used, output + used, out_len - used,
1932 "06. (( %s ))ANT_DIV\n",
1933 ((comp & ODM_BB_ANT_DIV) ? ("V") : (".")));
1934 PDM_SNPF(out_len, used, output + used, out_len - used,
1935 "07. (( %s ))SMT_ANT\n",
1936 ((comp & ODM_BB_SMT_ANT) ? ("V") : (".")));
1937 PDM_SNPF(out_len, used, output + used, out_len - used,
1938 "08. (( %s ))PWR_TRAIN\n",
1939 ((comp & ODM_BB_PWR_TRAIN) ? ("V") : (".")));
1940 PDM_SNPF(out_len, used, output + used, out_len - used,
1941 "09. (( %s ))RA\n",
1942 ((comp & ODM_BB_RATE_ADAPTIVE) ? ("V") : (".")));
1943 PDM_SNPF(out_len, used, output + used, out_len - used,
1944 "10. (( %s ))PATH_DIV\n",
1945 ((comp & ODM_BB_PATH_DIV) ? ("V") : (".")));
1946 PDM_SNPF(out_len, used, output + used, out_len - used,
1947 "11. (( %s ))DFS\n",
1948 ((comp & ODM_BB_DFS) ? ("V") : (".")));
1949 PDM_SNPF(out_len, used, output + used, out_len - used,
1950 "12. (( %s ))DYN_ARFR\n",
1951 ((comp & ODM_BB_DYNAMIC_ARFR) ? ("V") : (".")));
1952 PDM_SNPF(out_len, used, output + used, out_len - used,
1953 "13. (( %s ))ADAPTIVITY\n",
1954 ((comp & ODM_BB_ADAPTIVITY) ? ("V") : (".")));
1955 PDM_SNPF(out_len, used, output + used, out_len - used,
1956 "14. (( %s ))CFO_TRACK\n",
1957 ((comp & ODM_BB_CFO_TRACKING) ? ("V") : (".")));
1958 PDM_SNPF(out_len, used, output + used, out_len - used,
1959 "15. (( %s ))ENV_MONITOR\n",
1960 ((comp & ODM_BB_ENV_MONITOR) ? ("V") : (".")));
1961 PDM_SNPF(out_len, used, output + used, out_len - used,
1962 "16. (( %s ))PRI_CCA\n",
1963 ((comp & ODM_BB_PRIMARY_CCA) ? ("V") : (".")));
1964 PDM_SNPF(out_len, used, output + used, out_len - used,
1965 "17. (( %s ))ADPTV_SOML\n",
1966 ((comp & ODM_BB_ADAPTIVE_SOML) ? ("V") : (".")));
1967 PDM_SNPF(out_len, used, output + used, out_len - used,
1968 "18. (( %s ))LNA_SAT_CHK\n",
1969 ((comp & ODM_BB_LNA_SAT_CHK) ? ("V") : (".")));
1970 PDM_SNPF(out_len, used, output + used, out_len - used,
1971 "================================\n");
1972 PDM_SNPF(out_len, used, output + used, out_len - used,
1973 "[Supportability] PhyDM offload ability\n");
1974 PDM_SNPF(out_len, used, output + used, out_len - used,
1975 "================================\n");
1976
1977 PDM_SNPF(out_len, used, output + used, out_len - used,
1978 "00. (( %s ))PHY PARAM OFFLOAD\n",
1979 ((dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) ?
1980 ("V") : (".")));
1981 PDM_SNPF(out_len, used, output + used, out_len - used,
1982 "01. (( %s ))RF IQK OFFLOAD\n",
1983 ((dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ?
1984 ("V") : (".")));
1985 PDM_SNPF(out_len, used, output + used, out_len - used,
1986 "================================\n");
1987
1988 } else if (dm_value[0] == 101) {
1989 dm->support_ability = 0;
1990 PDM_SNPF(out_len, used, output + used, out_len - used,
1991 "Disable all support_ability components\n");
1992 } else {
1993 if (dm_value[1] == 1) { /* @enable */
1994 dm->support_ability |= (one << dm_value[0]);
1995 } else if (dm_value[1] == 2) {/* @disable */
1996 dm->support_ability &= ~(one << dm_value[0]);
1997 } else {
1998 PDM_SNPF(out_len, used, output + used, out_len - used,
1999 "[Warning!!!] 1:enable, 2:disable\n");
2000 }
2001 }
2002 PDM_SNPF(out_len, used, output + used, out_len - used,
2003 "pre-supportability = 0x%llx\n", pre_support_ability);
2004 PDM_SNPF(out_len, used, output + used, out_len - used,
2005 "Cur-supportability = 0x%llx\n", dm->support_ability);
2006 PDM_SNPF(out_len, used, output + used, out_len - used,
2007 "================================\n");
2008
2009 *_used = used;
2010 *_out_len = out_len;
2011 }
2012
phydm_watchdog_lps_32k(struct dm_struct * dm)2013 void phydm_watchdog_lps_32k(struct dm_struct *dm)
2014 {
2015 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
2016
2017 phydm_common_info_self_update(dm);
2018 phydm_rssi_monitor_check(dm);
2019 phydm_dig_lps_32k(dm);
2020 phydm_common_info_self_reset(dm);
2021 }
2022
phydm_watchdog_lps(struct dm_struct * dm)2023 void phydm_watchdog_lps(struct dm_struct *dm)
2024 {
2025 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
2026 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
2027
2028 phydm_common_info_self_update(dm);
2029 phydm_rssi_monitor_check(dm);
2030 phydm_basic_dbg_message(dm);
2031 phydm_receiver_blocking(dm);
2032 phydm_false_alarm_counter_statistics(dm);
2033 phydm_dig_by_rssi_lps(dm);
2034 #ifdef PHYDM_SUPPORT_CCKPD
2035 phydm_cck_pd_th(dm);
2036 #endif
2037 phydm_adaptivity(dm);
2038 #ifdef CONFIG_BW_INDICATION
2039 phydm_dyn_bw_indication(dm);
2040 #endif
2041 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
2042 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2043 /*@enable AntDiv in PS mode, request from SD4 Jeff*/
2044 odm_antenna_diversity(dm);
2045 #endif
2046 #endif
2047 phydm_common_info_self_reset(dm);
2048 #endif
2049 }
2050
phydm_watchdog_mp(struct dm_struct * dm)2051 void phydm_watchdog_mp(struct dm_struct *dm)
2052 {
2053 }
2054
phydm_pause_dm_watchdog(void * dm_void,enum phydm_pause_type pause_type)2055 void phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type)
2056 {
2057 struct dm_struct *dm = (struct dm_struct *)dm_void;
2058
2059 if (pause_type == PHYDM_PAUSE) {
2060 dm->disable_phydm_watchdog = 1;
2061 PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Stop\n");
2062 } else {
2063 dm->disable_phydm_watchdog = 0;
2064 PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Start\n");
2065 }
2066 }
2067
phydm_pause_func_init(void * dm_void)2068 void phydm_pause_func_init(void *dm_void)
2069 {
2070 struct dm_struct *dm = (struct dm_struct *)dm_void;
2071
2072 dm->pause_lv_table.lv_cckpd = PHYDM_PAUSE_RELEASE;
2073 dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
2074 dm->pause_lv_table.lv_antdiv = PHYDM_PAUSE_RELEASE;
2075 dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
2076 dm->pause_lv_table.lv_adapt = PHYDM_PAUSE_RELEASE;
2077 dm->pause_lv_table.lv_adsl = PHYDM_PAUSE_RELEASE;
2078 }
2079
phydm_pause_func(void * dm_void,enum phydm_func_idx pause_func,enum phydm_pause_type pause_type,enum phydm_pause_level pause_lv,u8 val_lehgth,u32 * val_buf)2080 u8 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func,
2081 enum phydm_pause_type pause_type,
2082 enum phydm_pause_level pause_lv, u8 val_lehgth,
2083 u32 *val_buf)
2084 {
2085 struct dm_struct *dm = (struct dm_struct *)dm_void;
2086 struct phydm_func_poiner *func_t = &dm->phydm_func_handler;
2087 s8 *pause_lv_pre = &dm->s8_dummy;
2088 u32 *bkp_val = &dm->u32_dummy;
2089 u32 ori_val[5] = {0};
2090 u64 pause_func_bitmap = (u64)BIT(pause_func);
2091 u8 i = 0;
2092 u8 en_2rcca = 0;
2093 u8 en_bw40m = 0;
2094 u8 pause_result = PAUSE_FAIL;
2095
2096 PHYDM_DBG(dm, ODM_COMP_API, "\n");
2097 PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] LV=%d, Len=%d\n", __func__,
2098 ((pause_type == PHYDM_PAUSE) ? "Pause" :
2099 ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
2100 pause_lv, val_lehgth);
2101
2102 if (pause_lv >= PHYDM_PAUSE_MAX_NUM) {
2103 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING]Wrong LV=%d\n", pause_lv);
2104 return PAUSE_FAIL;
2105 }
2106
2107 if (pause_func == F00_DIG) {
2108 PHYDM_DBG(dm, ODM_COMP_API, "[DIG]\n");
2109
2110 if (val_lehgth != 1) {
2111 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
2112 return PAUSE_FAIL;
2113 }
2114
2115 ori_val[0] = (u32)(dm->dm_dig_table.cur_ig_value);
2116 pause_lv_pre = &dm->pause_lv_table.lv_dig;
2117 bkp_val = (u32 *)(&dm->dm_dig_table.rvrt_val);
2118 /*@function pointer hook*/
2119 func_t->pause_phydm_handler = phydm_set_dig_val;
2120
2121 #ifdef PHYDM_SUPPORT_CCKPD
2122 } else if (pause_func == F05_CCK_PD) {
2123 PHYDM_DBG(dm, ODM_COMP_API, "[CCK_PD]\n");
2124
2125 if (val_lehgth != 1) {
2126 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
2127 return PAUSE_FAIL;
2128 }
2129
2130 ori_val[0] = (u32)dm->dm_cckpd_table.cck_pd_lv;
2131 pause_lv_pre = &dm->pause_lv_table.lv_cckpd;
2132 bkp_val = (u32 *)(&dm->dm_cckpd_table.rvrt_val);
2133 /*@function pointer hook*/
2134 func_t->pause_phydm_handler = phydm_set_cckpd_val;
2135 #endif
2136
2137 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2138 } else if (pause_func == F06_ANT_DIV) {
2139 PHYDM_DBG(dm, ODM_COMP_API, "[AntDiv]\n");
2140
2141 if (val_lehgth != 1) {
2142 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
2143 return PAUSE_FAIL;
2144 }
2145 /*@default antenna*/
2146 ori_val[0] = (u32)(dm->dm_fat_table.rx_idle_ant);
2147 pause_lv_pre = &dm->pause_lv_table.lv_antdiv;
2148 bkp_val = (u32 *)(&dm->dm_fat_table.rvrt_val);
2149 /*@function pointer hook*/
2150 func_t->pause_phydm_handler = phydm_set_antdiv_val;
2151
2152 #endif
2153 #ifdef PHYDM_SUPPORT_ADAPTIVITY
2154 } else if (pause_func == F13_ADPTVTY) {
2155 PHYDM_DBG(dm, ODM_COMP_API, "[Adaptivity]\n");
2156
2157 if (val_lehgth != 2) {
2158 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 2\n");
2159 return PAUSE_FAIL;
2160 }
2161
2162 ori_val[0] = (u32)(dm->adaptivity.th_l2h); /*th_l2h*/
2163 ori_val[1] = (u32)(dm->adaptivity.th_h2l); /*th_h2l*/
2164 pause_lv_pre = &dm->pause_lv_table.lv_adapt;
2165 bkp_val = (u32 *)(&dm->adaptivity.rvrt_val);
2166 /*@function pointer hook*/
2167 func_t->pause_phydm_handler = phydm_set_edcca_val;
2168
2169 #endif
2170 #ifdef CONFIG_ADAPTIVE_SOML
2171 } else if (pause_func == F17_ADPTV_SOML) {
2172 PHYDM_DBG(dm, ODM_COMP_API, "[AD-SOML]\n");
2173
2174 if (val_lehgth != 1) {
2175 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
2176 return PAUSE_FAIL;
2177 }
2178 /*SOML_ON/OFF*/
2179 ori_val[0] = (u32)(dm->dm_soml_table.soml_on_off);
2180
2181 pause_lv_pre = &dm->pause_lv_table.lv_adsl;
2182 bkp_val = (u32 *)(&dm->dm_soml_table.rvrt_val);
2183 /*@function pointer hook*/
2184 func_t->pause_phydm_handler = phydm_set_adsl_val;
2185
2186 #endif
2187 } else {
2188 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error func idx\n");
2189 return PAUSE_FAIL;
2190 }
2191
2192 PHYDM_DBG(dm, ODM_COMP_API, "Pause_LV{new , pre} = {%d ,%d}\n",
2193 pause_lv, *pause_lv_pre);
2194
2195 if (pause_type == PHYDM_PAUSE || pause_type == PHYDM_PAUSE_NO_SET) {
2196 if (pause_lv <= *pause_lv_pre) {
2197 PHYDM_DBG(dm, ODM_COMP_API,
2198 "[PAUSE FAIL] Pre_LV >= Curr_LV\n");
2199 return PAUSE_FAIL;
2200 }
2201
2202 if (!(dm->pause_ability & pause_func_bitmap)) {
2203 for (i = 0; i < val_lehgth; i++)
2204 bkp_val[i] = ori_val[i];
2205 }
2206
2207 dm->pause_ability |= pause_func_bitmap;
2208 PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
2209 dm->pause_ability);
2210
2211 if (pause_type == PHYDM_PAUSE) {
2212 for (i = 0; i < val_lehgth; i++)
2213 PHYDM_DBG(dm, ODM_COMP_API,
2214 "[PAUSE SUCCESS] val_idx[%d]{New, Ori}={0x%x, 0x%x}\n",
2215 i, val_buf[i], bkp_val[i]);
2216 func_t->pause_phydm_handler(dm, val_buf, val_lehgth);
2217 } else {
2218 for (i = 0; i < val_lehgth; i++)
2219 PHYDM_DBG(dm, ODM_COMP_API,
2220 "[PAUSE NO Set: SUCCESS] val_idx[%d]{Ori}={0x%x}\n",
2221 i, bkp_val[i]);
2222 }
2223
2224 *pause_lv_pre = pause_lv;
2225 pause_result = PAUSE_SUCCESS;
2226
2227 } else if (pause_type == PHYDM_RESUME) {
2228 if (pause_lv < *pause_lv_pre) {
2229 PHYDM_DBG(dm, ODM_COMP_API,
2230 "[Resume FAIL] Pre_LV >= Curr_LV\n");
2231 return PAUSE_FAIL;
2232 }
2233
2234 if ((dm->pause_ability & pause_func_bitmap) == 0) {
2235 PHYDM_DBG(dm, ODM_COMP_API,
2236 "[RESUME] No Need to Revert\n");
2237 return PAUSE_SUCCESS;
2238 }
2239
2240 dm->pause_ability &= ~pause_func_bitmap;
2241 PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
2242 dm->pause_ability);
2243
2244 *pause_lv_pre = PHYDM_PAUSE_RELEASE;
2245
2246 for (i = 0; i < val_lehgth; i++) {
2247 PHYDM_DBG(dm, ODM_COMP_API,
2248 "[RESUME] val_idx[%d]={0x%x}\n", i,
2249 bkp_val[i]);
2250 }
2251
2252 func_t->pause_phydm_handler(dm, bkp_val, val_lehgth);
2253
2254 pause_result = PAUSE_SUCCESS;
2255 } else {
2256 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error pause_type\n");
2257 pause_result = PAUSE_FAIL;
2258 }
2259 return pause_result;
2260 }
2261
phydm_pause_func_console(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)2262 void phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used,
2263 char *output, u32 *_out_len)
2264 {
2265 struct dm_struct *dm = (struct dm_struct *)dm_void;
2266 char help[] = "-h";
2267 u32 var1[10] = {0};
2268 u32 used = *_used;
2269 u32 out_len = *_out_len;
2270 u32 i;
2271 u8 length = 0;
2272 u32 buf[5] = {0};
2273 u8 set_result = 0;
2274 enum phydm_func_idx func = 0;
2275 enum phydm_pause_type type = 0;
2276 enum phydm_pause_level lv = 0;
2277
2278 if ((strcmp(input[1], help) == 0)) {
2279 PDM_SNPF(out_len, used, output + used, out_len - used,
2280 "{Func} {1:pause,2:pause no set 3:Resume} {lv:0~3} Val[5:0]\n");
2281
2282 goto out;
2283 }
2284
2285 for (i = 0; i < 10; i++) {
2286 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
2287 }
2288
2289 func = (enum phydm_func_idx)var1[0];
2290 type = (enum phydm_pause_type)var1[1];
2291 lv = (enum phydm_pause_level)var1[2];
2292
2293 for (i = 0; i < 5; i++)
2294 buf[i] = var1[3 + i];
2295
2296 if (func == F00_DIG) {
2297 PDM_SNPF(out_len, used, output + used, out_len - used,
2298 "[DIG]\n");
2299 length = 1;
2300
2301 } else if (func == F05_CCK_PD) {
2302 PDM_SNPF(out_len, used, output + used, out_len - used,
2303 "[CCK_PD]\n");
2304 length = 1;
2305 } else if (func == F06_ANT_DIV) {
2306 PDM_SNPF(out_len, used, output + used, out_len - used,
2307 "[Ant_Div]\n");
2308 length = 1;
2309 } else if (func == F13_ADPTVTY) {
2310 PDM_SNPF(out_len, used, output + used, out_len - used,
2311 "[Adaptivity]\n");
2312 length = 2;
2313 } else if (func == F17_ADPTV_SOML) {
2314 PDM_SNPF(out_len, used, output + used, out_len - used,
2315 "[ADSL]\n");
2316 length = 1;
2317 } else {
2318 PDM_SNPF(out_len, used, output + used, out_len - used,
2319 "[Set Function Error]\n");
2320 length = 0;
2321 }
2322
2323 if (length != 0) {
2324 PDM_SNPF(out_len, used, output + used, out_len - used,
2325 "{%s, lv=%d} val = %d, %d}\n",
2326 ((type == PHYDM_PAUSE) ? "Pause" :
2327 ((type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
2328 lv, var1[3], var1[4]);
2329
2330 set_result = phydm_pause_func(dm, func, type, lv, length, buf);
2331 }
2332
2333 PDM_SNPF(out_len, used, output + used, out_len - used,
2334 "set_result = %d\n", set_result);
2335
2336 out:
2337 *_used = used;
2338 *_out_len = out_len;
2339 }
2340
phydm_pause_dm_by_asso_pkt(struct dm_struct * dm,enum phydm_pause_type pause_type,u8 rssi)2341 void phydm_pause_dm_by_asso_pkt(struct dm_struct *dm,
2342 enum phydm_pause_type pause_type, u8 rssi)
2343 {
2344 u32 igi_val = rssi + 10;
2345 u32 th_buf[2];
2346
2347 PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] rssi=%d\n", __func__,
2348 ((pause_type == PHYDM_PAUSE) ? "Pause" :
2349 ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
2350 rssi);
2351
2352 if (pause_type == PHYDM_RESUME) {
2353 phydm_pause_func(dm, F00_DIG, PHYDM_RESUME,
2354 PHYDM_PAUSE_LEVEL_1, 1, &igi_val);
2355
2356 phydm_pause_func(dm, F13_ADPTVTY, PHYDM_RESUME,
2357 PHYDM_PAUSE_LEVEL_1, 2, th_buf);
2358 } else {
2359 odm_write_dig(dm, (u8)igi_val);
2360 phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE,
2361 PHYDM_PAUSE_LEVEL_1, 1, &igi_val);
2362
2363 th_buf[0] = 0xff;
2364 th_buf[1] = 0xff;
2365
2366 phydm_pause_func(dm, F13_ADPTVTY, PHYDM_PAUSE,
2367 PHYDM_PAUSE_LEVEL_1, 2, th_buf);
2368 }
2369 }
2370
phydm_stop_dm_watchdog_check(void * dm_void)2371 u8 phydm_stop_dm_watchdog_check(void *dm_void)
2372 {
2373 struct dm_struct *dm = (struct dm_struct *)dm_void;
2374
2375 if (dm->disable_phydm_watchdog == 1) {
2376 PHYDM_DBG(dm, DBG_COMMON_FLOW, "Disable phydm\n");
2377 return true;
2378 } else {
2379 return false;
2380 }
2381 }
2382
phydm_watchdog(struct dm_struct * dm)2383 void phydm_watchdog(struct dm_struct *dm)
2384 {
2385 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
2386
2387 phydm_common_info_self_update(dm);
2388 phydm_phy_info_update(dm);
2389 phydm_rssi_monitor_check(dm);
2390 phydm_basic_dbg_message(dm);
2391 phydm_dm_summary(dm, FIRST_MACID);
2392 #ifdef PHYDM_AUTO_DEGBUG
2393 phydm_auto_dbg_engine(dm);
2394 #endif
2395 phydm_receiver_blocking(dm);
2396
2397 if (phydm_stop_dm_watchdog_check(dm) == true)
2398 return;
2399
2400 phydm_hw_setting(dm);
2401
2402 #ifdef PHYDM_TDMA_DIG_SUPPORT
2403 if (dm->original_dig_restore == 0) {
2404 phydm_tdma_dig_timer_check(dm);
2405 } else
2406 #endif
2407 {
2408 phydm_false_alarm_counter_statistics(dm);
2409 #if (ODM_IC_11N_SERIES_SUPPORT || ODM_IC_11AC_SERIES_SUPPORT)
2410 if (dm->support_ic_type & (ODM_IC_11N_SERIES |
2411 ODM_IC_11AC_SERIES))
2412 phydm_noisy_detection(dm);
2413 #endif
2414
2415 #if defined(PHYDM_DCC_ENHANCE) && defined(PHYDM_SUPPORT_CCKPD)
2416 phydm_dig_cckpd_coex(dm);
2417 #else
2418 phydm_dig(dm);
2419 #ifdef PHYDM_SUPPORT_CCKPD
2420 phydm_cck_pd_th(dm);
2421 #endif
2422 #endif
2423 }
2424
2425 #ifdef PHYDM_HW_IGI
2426 phydm_hwigi(dm);
2427 #endif
2428 #ifdef PHYDM_POWER_TRAINING_SUPPORT
2429 phydm_update_power_training_state(dm);
2430 #endif
2431 phydm_adaptivity(dm);
2432 phydm_ra_info_watchdog(dm);
2433 #ifdef CONFIG_PATH_DIVERSITY
2434 phydm_tx_path_diversity(dm);
2435 #endif
2436 phydm_cfo_tracking(dm);
2437 #ifdef CONFIG_DYNAMIC_TX_TWR
2438 phydm_dynamic_tx_power(dm);
2439 #endif
2440 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2441 odm_antenna_diversity(dm);
2442 #endif
2443 #ifdef CONFIG_ADAPTIVE_SOML
2444 phydm_adaptive_soml(dm);
2445 #endif
2446
2447 #ifdef PHYDM_BEAMFORMING_VERSION1
2448 phydm_beamforming_watchdog(dm);
2449 #endif
2450
2451 halrf_watchdog(dm);
2452 #ifdef PHYDM_PRIMARY_CCA
2453 phydm_primary_cca(dm);
2454 #endif
2455 #ifdef CONFIG_BW_INDICATION
2456 phydm_dyn_bw_indication(dm);
2457 #endif
2458 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2459 odm_dtc(dm);
2460 #endif
2461
2462 phydm_env_mntr_watchdog(dm);
2463 phydm_enhance_mntr_watchdog(dm);
2464
2465 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
2466 phydm_lna_sat_chk_watchdog(dm);
2467 #endif
2468
2469 #ifdef CONFIG_MCC_DM
2470 phydm_mcc_switch(dm);
2471 #endif
2472
2473 #ifdef CONFIG_MU_RSOML
2474 phydm_mu_rsoml_decision(dm);
2475 #endif
2476
2477 phydm_common_info_self_reset(dm);
2478 }
2479
phydm_fw_dm_ctrl_en(void * dm_void,enum phydm_func_idx fun_idx,boolean enable)2480 void phydm_fw_dm_ctrl_en(void *dm_void, enum phydm_func_idx fun_idx,
2481 boolean enable)
2482 {
2483 struct dm_struct *dm = (struct dm_struct *)dm_void;
2484 u8 h2c_val[H2C_MAX_LENGTH] = {0};
2485 u8 para4[4]; /*4 bit*/
2486 u8 para8[4]; /*8 bit*/
2487 u8 i = 0;
2488
2489 for (i = 0; i < 4; i++) {
2490 para4[i] = 0;
2491 para8[i] = 0;
2492 }
2493
2494 switch (fun_idx) {
2495 case F00_DIG:
2496 phydm_fill_fw_dig_info(dm, &enable, para4, para8);
2497 break;
2498 default:
2499 pr_debug("[Warning] %s\n", __func__);
2500 return;
2501 }
2502
2503 h2c_val[0] = (u8)((fun_idx & 0x3f) | (enable << 6));
2504 h2c_val[1] = para8[0];
2505 h2c_val[2] = para8[1];
2506 h2c_val[3] = para8[2];
2507 h2c_val[4] = para8[3];
2508 h2c_val[5] = (para4[0] & 0xf) | ((para4[1] & 0xf) << 3);
2509 h2c_val[6] = (para4[2] & 0xf) | ((para4[3] & 0xf) << 3);
2510
2511 PHYDM_DBG(dm, DBG_FW_DM,
2512 "H2C[0x59] fun_idx=%d,en=%d,para8={%x %x %x %x},para4={%x %x %x %x}\n",
2513 fun_idx, enable,
2514 para8[0], para8[1], para8[2], para8[3],
2515 para4[0], para4[1], para4[2], para4[3]);
2516
2517 odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_DM_CTRL, H2C_MAX_LENGTH, h2c_val);
2518 }
2519
2520 /*@
2521 * Init /.. Fixed HW value. Only init time.
2522 */
odm_cmn_info_init(struct dm_struct * dm,enum odm_cmninfo cmn_info,u64 value)2523 void odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info,
2524 u64 value)
2525 {
2526 /* This section is used for init value */
2527 switch (cmn_info) {
2528 /* @Fixed ODM value. */
2529 case ODM_CMNINFO_ABILITY:
2530 dm->support_ability = (u64)value;
2531 break;
2532
2533 case ODM_CMNINFO_RF_TYPE:
2534 dm->rf_type = (u8)value;
2535 break;
2536
2537 case ODM_CMNINFO_PLATFORM:
2538 dm->support_platform = (u8)value;
2539 break;
2540
2541 case ODM_CMNINFO_INTERFACE:
2542 dm->support_interface = (u8)value;
2543 break;
2544
2545 case ODM_CMNINFO_MP_TEST_CHIP:
2546 dm->is_mp_chip = (u8)value;
2547 break;
2548
2549 case ODM_CMNINFO_IC_TYPE:
2550 dm->support_ic_type = (u32)value;
2551 break;
2552
2553 case ODM_CMNINFO_CUT_VER:
2554 dm->cut_version = (u8)value;
2555 break;
2556
2557 case ODM_CMNINFO_FAB_VER:
2558 dm->fab_version = (u8)value;
2559 break;
2560 case ODM_CMNINFO_FW_VER:
2561 dm->fw_version = (u8)value;
2562 break;
2563 case ODM_CMNINFO_FW_SUB_VER:
2564 dm->fw_sub_version = (u8)value;
2565 break;
2566 case ODM_CMNINFO_RFE_TYPE:
2567 #if (RTL8821C_SUPPORT)
2568 if (dm->support_ic_type & ODM_RTL8821C)
2569 dm->rfe_type_expand = (u8)value;
2570 else
2571 #endif
2572 dm->rfe_type = (u8)value;
2573
2574 #ifdef CONFIG_RFE_BY_HW_INFO
2575 phydm_init_hw_info_by_rfe(dm);
2576 #endif
2577 break;
2578
2579 case ODM_CMNINFO_RF_ANTENNA_TYPE:
2580 dm->ant_div_type = (u8)value;
2581 break;
2582
2583 case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH:
2584 dm->with_extenal_ant_switch = (u8)value;
2585 break;
2586
2587 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2588 case ODM_CMNINFO_BE_FIX_TX_ANT:
2589 dm->dm_fat_table.b_fix_tx_ant = (u8)value;
2590 break;
2591 #endif
2592
2593 case ODM_CMNINFO_BOARD_TYPE:
2594 if (!dm->is_init_hw_info_by_rfe)
2595 dm->board_type = (u8)value;
2596 break;
2597
2598 case ODM_CMNINFO_PACKAGE_TYPE:
2599 if (!dm->is_init_hw_info_by_rfe)
2600 dm->package_type = (u8)value;
2601 break;
2602
2603 case ODM_CMNINFO_EXT_LNA:
2604 if (!dm->is_init_hw_info_by_rfe)
2605 dm->ext_lna = (u8)value;
2606 break;
2607
2608 case ODM_CMNINFO_5G_EXT_LNA:
2609 if (!dm->is_init_hw_info_by_rfe)
2610 dm->ext_lna_5g = (u8)value;
2611 break;
2612
2613 case ODM_CMNINFO_EXT_PA:
2614 if (!dm->is_init_hw_info_by_rfe)
2615 dm->ext_pa = (u8)value;
2616 break;
2617
2618 case ODM_CMNINFO_5G_EXT_PA:
2619 if (!dm->is_init_hw_info_by_rfe)
2620 dm->ext_pa_5g = (u8)value;
2621 break;
2622
2623 case ODM_CMNINFO_GPA:
2624 if (!dm->is_init_hw_info_by_rfe)
2625 dm->type_gpa = (u16)value;
2626 break;
2627
2628 case ODM_CMNINFO_APA:
2629 if (!dm->is_init_hw_info_by_rfe)
2630 dm->type_apa = (u16)value;
2631 break;
2632
2633 case ODM_CMNINFO_GLNA:
2634 if (!dm->is_init_hw_info_by_rfe)
2635 dm->type_glna = (u16)value;
2636 break;
2637
2638 case ODM_CMNINFO_ALNA:
2639 if (!dm->is_init_hw_info_by_rfe)
2640 dm->type_alna = (u16)value;
2641 break;
2642
2643 case ODM_CMNINFO_EXT_TRSW:
2644 if (!dm->is_init_hw_info_by_rfe)
2645 dm->ext_trsw = (u8)value;
2646 break;
2647 case ODM_CMNINFO_EXT_LNA_GAIN:
2648 dm->ext_lna_gain = (u8)value;
2649 break;
2650 case ODM_CMNINFO_PATCH_ID:
2651 dm->iot_table.win_patch_id = (u8)value;
2652 break;
2653 case ODM_CMNINFO_BINHCT_TEST:
2654 dm->is_in_hct_test = (boolean)value;
2655 break;
2656 case ODM_CMNINFO_BWIFI_TEST:
2657 dm->wifi_test = (u8)value;
2658 break;
2659 case ODM_CMNINFO_SMART_CONCURRENT:
2660 dm->is_dual_mac_smart_concurrent = (boolean)value;
2661 break;
2662 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2663 case ODM_CMNINFO_CONFIG_BB_RF:
2664 dm->config_bbrf = (boolean)value;
2665 break;
2666 #endif
2667 case ODM_CMNINFO_IQKPAOFF:
2668 dm->rf_calibrate_info.is_iqk_pa_off = (boolean)value;
2669 break;
2670 case ODM_CMNINFO_REGRFKFREEENABLE:
2671 dm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value;
2672 break;
2673 case ODM_CMNINFO_RFKFREEENABLE:
2674 dm->rf_calibrate_info.rf_kfree_enable = (u8)value;
2675 break;
2676 case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE:
2677 dm->normal_rx_path = (u8)value;
2678 break;
2679 case ODM_CMNINFO_VALID_PATH_SET:
2680 dm->valid_path_set = (u8)value;
2681 break;
2682 case ODM_CMNINFO_EFUSE0X3D8:
2683 dm->efuse0x3d8 = (u8)value;
2684 break;
2685 case ODM_CMNINFO_EFUSE0X3D7:
2686 dm->efuse0x3d7 = (u8)value;
2687 break;
2688 case ODM_CMNINFO_ADVANCE_OTA:
2689 dm->p_advance_ota = (u8)value;
2690 break;
2691
2692 #ifdef CONFIG_PHYDM_DFS_MASTER
2693 case ODM_CMNINFO_DFS_REGION_DOMAIN:
2694 dm->dfs_region_domain = (u8)value;
2695 break;
2696 #endif
2697 case ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING:
2698 dm->soft_ap_special_setting = (u32)value;
2699 break;
2700
2701 case ODM_CMNINFO_X_CAP_SETTING:
2702 dm->dm_cfo_track.crystal_cap_default = (u8)value;
2703 break;
2704
2705 case ODM_CMNINFO_DPK_EN:
2706 /*@dm->dpk_en = (u1Byte)value;*/
2707 halrf_cmn_info_set(dm, HALRF_CMNINFO_DPK_EN, (u64)value);
2708 break;
2709
2710 case ODM_CMNINFO_HP_HWID:
2711 dm->hp_hw_id = (boolean)value;
2712 break;
2713 case ODM_CMNINFO_TSSI_ENABLE:
2714 dm->en_tssi_mode = (u8)value;
2715 break;
2716 case ODM_CMNINFO_DIS_DPD:
2717 dm->en_dis_dpd = (boolean)value;
2718 break;
2719 case ODM_CMNINFO_EN_AUTO_BW_TH:
2720 dm->en_auto_bw_th = (u8)value;
2721 break;
2722 #if (RTL8721D_SUPPORT)
2723 case ODM_CMNINFO_POWER_VOLTAGE:
2724 dm->power_voltage = (u8)value;
2725 break;
2726 case ODM_CMNINFO_ANTDIV_GPIO:
2727 dm->antdiv_gpio = (u8)value;
2728 break;
2729 case ODM_CMNINFO_PEAK_DETECT_MODE:
2730 dm->peak_detect_mode = (u8)value;
2731 break;
2732 #endif
2733 default:
2734 break;
2735 }
2736 }
2737
odm_cmn_info_hook(struct dm_struct * dm,enum odm_cmninfo cmn_info,void * value)2738 void odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info,
2739 void *value)
2740 {
2741 /* @Hook call by reference pointer. */
2742 switch (cmn_info) {
2743 /* @Dynamic call by reference pointer. */
2744 case ODM_CMNINFO_TX_UNI:
2745 dm->num_tx_bytes_unicast = (u64 *)value;
2746 break;
2747
2748 case ODM_CMNINFO_RX_UNI:
2749 dm->num_rx_bytes_unicast = (u64 *)value;
2750 break;
2751
2752 case ODM_CMNINFO_BAND:
2753 dm->band_type = (u8 *)value;
2754 break;
2755
2756 case ODM_CMNINFO_SEC_CHNL_OFFSET:
2757 dm->sec_ch_offset = (u8 *)value;
2758 break;
2759
2760 case ODM_CMNINFO_SEC_MODE:
2761 dm->security = (u8 *)value;
2762 break;
2763
2764 case ODM_CMNINFO_BW:
2765 dm->band_width = (u8 *)value;
2766 break;
2767
2768 case ODM_CMNINFO_CHNL:
2769 dm->channel = (u8 *)value;
2770 break;
2771
2772 case ODM_CMNINFO_SCAN:
2773 dm->is_scan_in_process = (boolean *)value;
2774 break;
2775
2776 case ODM_CMNINFO_POWER_SAVING:
2777 dm->is_power_saving = (boolean *)value;
2778 break;
2779
2780 case ODM_CMNINFO_TDMA:
2781 dm->is_tdma = (boolean *)value;
2782 break;
2783
2784 case ODM_CMNINFO_ONE_PATH_CCA:
2785 dm->one_path_cca = (u8 *)value;
2786 break;
2787
2788 case ODM_CMNINFO_DRV_STOP:
2789 dm->is_driver_stopped = (boolean *)value;
2790 break;
2791 case ODM_CMNINFO_INIT_ON:
2792 dm->pinit_adpt_in_progress = (boolean *)value;
2793 break;
2794
2795 case ODM_CMNINFO_ANT_TEST:
2796 dm->antenna_test = (u8 *)value;
2797 break;
2798
2799 case ODM_CMNINFO_NET_CLOSED:
2800 dm->is_net_closed = (boolean *)value;
2801 break;
2802
2803 case ODM_CMNINFO_FORCED_RATE:
2804 dm->forced_data_rate = (u16 *)value;
2805 break;
2806 case ODM_CMNINFO_ANT_DIV:
2807 dm->enable_antdiv = (u8 *)value;
2808 break;
2809 case ODM_CMNINFO_PATH_DIV:
2810 dm->enable_pathdiv = (u8 *)value;
2811 break;
2812 case ODM_CMNINFO_ADAPTIVE_SOML:
2813 dm->en_adap_soml = (u8 *)value;
2814 break;
2815 case ODM_CMNINFO_ADAPTIVITY:
2816 dm->edcca_mode = (u8 *)value;
2817 break;
2818
2819 case ODM_CMNINFO_P2P_LINK:
2820 dm->dm_dig_table.is_p2p_in_process = (u8 *)value;
2821 break;
2822
2823 case ODM_CMNINFO_IS1ANTENNA:
2824 dm->is_1_antenna = (boolean *)value;
2825 break;
2826
2827 case ODM_CMNINFO_RFDEFAULTPATH:
2828 dm->rf_default_path = (u8 *)value;
2829 break;
2830
2831 case ODM_CMNINFO_FCS_MODE: /* @fast channel switch (= MCC mode)*/
2832 dm->is_fcs_mode_enable = (boolean *)value;
2833 break;
2834
2835 case ODM_CMNINFO_HUBUSBMODE:
2836 dm->hub_usb_mode = (u8 *)value;
2837 break;
2838 case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS:
2839 dm->is_fw_dw_rsvd_page_in_progress = (boolean *)value;
2840 break;
2841 case ODM_CMNINFO_TX_TP:
2842 dm->current_tx_tp = (u32 *)value;
2843 break;
2844 case ODM_CMNINFO_RX_TP:
2845 dm->current_rx_tp = (u32 *)value;
2846 break;
2847 case ODM_CMNINFO_SOUNDING_SEQ:
2848 dm->sounding_seq = (u8 *)value;
2849 break;
2850 #ifdef CONFIG_PHYDM_DFS_MASTER
2851 case ODM_CMNINFO_DFS_MASTER_ENABLE:
2852 dm->dfs_master_enabled = (u8 *)value;
2853 break;
2854 #endif
2855
2856 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2857 case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC:
2858 dm->dm_fat_table.p_force_tx_by_desc = (u8 *)value;
2859 break;
2860 case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA:
2861 dm->dm_fat_table.p_default_s0_s1 = (u8 *)value;
2862 break;
2863 case ODM_CMNINFO_BF_ANTDIV_DECISION:
2864 dm->dm_fat_table.is_no_csi_feedback = (boolean *)value;
2865 break;
2866 #endif
2867
2868 case ODM_CMNINFO_SOFT_AP_MODE:
2869 dm->soft_ap_mode = (u32 *)value;
2870 break;
2871 case ODM_CMNINFO_MP_MODE:
2872 dm->mp_mode = (u8 *)value;
2873 break;
2874 case ODM_CMNINFO_INTERRUPT_MASK:
2875 dm->interrupt_mask = (u32 *)value;
2876 break;
2877 case ODM_CMNINFO_BB_OPERATION_MODE:
2878 dm->bb_op_mode = (u8 *)value;
2879 break;
2880 case ODM_CMNINFO_MANUAL_SUPPORTABILITY:
2881 dm->manual_supportability = (u32 *)value;
2882 break;
2883 case ODM_CMNINFO_EN_DYM_BW_INDICATION:
2884 dm->dis_dym_bw_indication = (u8 *)value;
2885 default:
2886 /*do nothing*/
2887 break;
2888 }
2889 }
2890
2891 /*@
2892 * Update band/CHannel/.. The values are dynamic but non-per-packet.
2893 */
odm_cmn_info_update(struct dm_struct * dm,u32 cmn_info,u64 value)2894 void odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value)
2895 {
2896 /* This init variable may be changed in run time. */
2897 switch (cmn_info) {
2898 case ODM_CMNINFO_LINK_IN_PROGRESS:
2899 dm->is_link_in_process = (boolean)value;
2900 break;
2901
2902 case ODM_CMNINFO_ABILITY:
2903 dm->support_ability = (u64)value;
2904 break;
2905
2906 case ODM_CMNINFO_RF_TYPE:
2907 dm->rf_type = (u8)value;
2908 break;
2909
2910 case ODM_CMNINFO_WIFI_DIRECT:
2911 dm->is_wifi_direct = (boolean)value;
2912 break;
2913
2914 case ODM_CMNINFO_WIFI_DISPLAY:
2915 dm->is_wifi_display = (boolean)value;
2916 break;
2917
2918 case ODM_CMNINFO_LINK:
2919 dm->is_linked = (boolean)value;
2920 break;
2921
2922 case ODM_CMNINFO_CMW500LINK:
2923 dm->iot_table.is_linked_cmw500 = (boolean)value;
2924 break;
2925
2926 case ODM_CMNINFO_STATION_STATE:
2927 dm->bsta_state = (boolean)value;
2928 break;
2929
2930 case ODM_CMNINFO_RSSI_MIN:
2931 #if 0
2932 dm->rssi_min = (u8)value;
2933 #endif
2934 break;
2935
2936 case ODM_CMNINFO_RSSI_MIN_BY_PATH:
2937 dm->rssi_min_by_path = (u8)value;
2938 break;
2939
2940 case ODM_CMNINFO_DBG_COMP:
2941 dm->debug_components = (u64)value;
2942 break;
2943
2944 #ifdef ODM_CONFIG_BT_COEXIST
2945 /* The following is for BT HS mode and BT coexist mechanism. */
2946 case ODM_CMNINFO_BT_ENABLED:
2947 dm->bt_info_table.is_bt_enabled = (boolean)value;
2948 break;
2949
2950 case ODM_CMNINFO_BT_HS_CONNECT_PROCESS:
2951 dm->bt_info_table.is_bt_connect_process = (boolean)value;
2952 break;
2953
2954 case ODM_CMNINFO_BT_HS_RSSI:
2955 dm->bt_info_table.bt_hs_rssi = (u8)value;
2956 break;
2957
2958 case ODM_CMNINFO_BT_OPERATION:
2959 dm->bt_info_table.is_bt_hs_operation = (boolean)value;
2960 break;
2961
2962 case ODM_CMNINFO_BT_LIMITED_DIG:
2963 dm->bt_info_table.is_bt_limited_dig = (boolean)value;
2964 break;
2965 #endif
2966
2967 case ODM_CMNINFO_AP_TOTAL_NUM:
2968 dm->ap_total_num = (u8)value;
2969 break;
2970
2971 #ifdef CONFIG_PHYDM_DFS_MASTER
2972 case ODM_CMNINFO_DFS_REGION_DOMAIN:
2973 dm->dfs_region_domain = (u8)value;
2974 break;
2975 #endif
2976
2977 case ODM_CMNINFO_BT_CONTINUOUS_TURN:
2978 dm->is_bt_continuous_turn = (boolean)value;
2979 break;
2980 case ODM_CMNINFO_IS_DOWNLOAD_FW:
2981 dm->is_download_fw = (boolean)value;
2982 break;
2983 case ODM_CMNINFO_PHYDM_PATCH_ID:
2984 dm->iot_table.phydm_patch_id = (u32)value;
2985 break;
2986 case ODM_CMNINFO_RRSR_VAL:
2987 dm->dm_ra_table.rrsr_val_init = (u32)value;
2988 break;
2989 case ODM_CMNINFO_LINKED_BF_SUPPORT:
2990 dm->linked_bf_support = (u8)value;
2991 break;
2992 case ODM_CMNINFO_FLATNESS_TYPE:
2993 dm->flatness_type = (u8)value;
2994 break;
2995 case ODM_CMNINFO_TSSI_ENABLE:
2996 dm->en_tssi_mode = (u8)value;
2997 break;
2998 default:
2999 break;
3000 }
3001 }
3002
phydm_cmn_info_query(struct dm_struct * dm,enum phydm_info_query info_type)3003 u32 phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type)
3004 {
3005 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
3006 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3007 struct ccx_info *ccx_info = &dm->dm_ccx_info;
3008
3009 switch (info_type) {
3010 /*@=== [FA Relative] ===========================================*/
3011 case PHYDM_INFO_FA_OFDM:
3012 return fa_t->cnt_ofdm_fail;
3013
3014 case PHYDM_INFO_FA_CCK:
3015 return fa_t->cnt_cck_fail;
3016
3017 case PHYDM_INFO_FA_TOTAL:
3018 return fa_t->cnt_all;
3019
3020 case PHYDM_INFO_CCA_OFDM:
3021 return fa_t->cnt_ofdm_cca;
3022
3023 case PHYDM_INFO_CCA_CCK:
3024 return fa_t->cnt_cck_cca;
3025
3026 case PHYDM_INFO_CCA_ALL:
3027 return fa_t->cnt_cca_all;
3028
3029 case PHYDM_INFO_CRC32_OK_VHT:
3030 return fa_t->cnt_vht_crc32_ok;
3031
3032 case PHYDM_INFO_CRC32_OK_HT:
3033 return fa_t->cnt_ht_crc32_ok;
3034
3035 case PHYDM_INFO_CRC32_OK_LEGACY:
3036 return fa_t->cnt_ofdm_crc32_ok;
3037
3038 case PHYDM_INFO_CRC32_OK_CCK:
3039 return fa_t->cnt_cck_crc32_ok;
3040
3041 case PHYDM_INFO_CRC32_ERROR_VHT:
3042 return fa_t->cnt_vht_crc32_error;
3043
3044 case PHYDM_INFO_CRC32_ERROR_HT:
3045 return fa_t->cnt_ht_crc32_error;
3046
3047 case PHYDM_INFO_CRC32_ERROR_LEGACY:
3048 return fa_t->cnt_ofdm_crc32_error;
3049
3050 case PHYDM_INFO_CRC32_ERROR_CCK:
3051 return fa_t->cnt_cck_crc32_error;
3052
3053 case PHYDM_INFO_EDCCA_FLAG:
3054 return fa_t->edcca_flag;
3055
3056 case PHYDM_INFO_OFDM_ENABLE:
3057 return fa_t->ofdm_block_enable;
3058
3059 case PHYDM_INFO_CCK_ENABLE:
3060 return fa_t->cck_block_enable;
3061
3062 case PHYDM_INFO_DBG_PORT_0:
3063 return fa_t->dbg_port0;
3064
3065 case PHYDM_INFO_CRC32_OK_HT_AGG:
3066 return fa_t->cnt_ht_crc32_ok_agg;
3067
3068 case PHYDM_INFO_CRC32_ERROR_HT_AGG:
3069 return fa_t->cnt_ht_crc32_error_agg;
3070
3071 /*@=== [DIG] ================================================*/
3072
3073 case PHYDM_INFO_CURR_IGI:
3074 return dig_t->cur_ig_value;
3075
3076 /*@=== [RSSI] ===============================================*/
3077 case PHYDM_INFO_RSSI_MIN:
3078 return (u32)dm->rssi_min;
3079
3080 case PHYDM_INFO_RSSI_MAX:
3081 return (u32)dm->rssi_max;
3082
3083 case PHYDM_INFO_CLM_RATIO:
3084 return (u32)ccx_info->clm_ratio;
3085 case PHYDM_INFO_NHM_RATIO:
3086 return (u32)ccx_info->nhm_ratio;
3087 case PHYDM_INFO_NHM_NOISE_PWR:
3088 return (u32)ccx_info->nhm_level;
3089 case PHYDM_INFO_NHM_PWR:
3090 return (u32)ccx_info->nhm_pwr;
3091 case PHYDM_INFO_NHM_ENV_RATIO:
3092 return (u32)ccx_info->nhm_env_ratio;
3093
3094 default:
3095 return 0xffffffff;
3096 }
3097 }
3098
3099 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
odm_init_all_work_items(struct dm_struct * dm)3100 void odm_init_all_work_items(struct dm_struct *dm)
3101 {
3102 void *adapter = dm->adapter;
3103 #if USE_WORKITEM
3104
3105 #ifdef CONFIG_ADAPTIVE_SOML
3106 odm_initialize_work_item(dm,
3107 &dm->dm_soml_table.phydm_adaptive_soml_workitem,
3108 (RT_WORKITEM_CALL_BACK)phydm_adaptive_soml_workitem_callback,
3109 (void *)adapter,
3110 "AdaptiveSOMLWorkitem");
3111 #endif
3112
3113 #ifdef ODM_EVM_ENHANCE_ANTDIV
3114 odm_initialize_work_item(dm,
3115 &dm->phydm_evm_antdiv_workitem,
3116 (RT_WORKITEM_CALL_BACK)phydm_evm_antdiv_workitem_callback,
3117 (void *)adapter,
3118 "EvmAntdivWorkitem");
3119 #endif
3120
3121 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
3122 odm_initialize_work_item(dm,
3123 &dm->dm_swat_table.phydm_sw_antenna_switch_workitem,
3124 (RT_WORKITEM_CALL_BACK)odm_sw_antdiv_workitem_callback,
3125 (void *)adapter,
3126 "AntennaSwitchWorkitem");
3127 #endif
3128 #if (defined(CONFIG_HL_SMART_ANTENNA))
3129 odm_initialize_work_item(dm,
3130 &dm->dm_sat_table.hl_smart_antenna_workitem,
3131 (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback,
3132 (void *)adapter,
3133 "hl_smart_ant_workitem");
3134
3135 odm_initialize_work_item(dm,
3136 &dm->dm_sat_table.hl_smart_antenna_decision_workitem,
3137 (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback,
3138 (void *)adapter,
3139 "hl_smart_ant_decision_workitem");
3140 #endif
3141
3142 odm_initialize_work_item(
3143 dm,
3144 &dm->ra_rpt_workitem,
3145 (RT_WORKITEM_CALL_BACK)halrf_update_init_rate_work_item_callback,
3146 (void *)adapter,
3147 "ra_rpt_workitem");
3148
3149 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
3150 odm_initialize_work_item(
3151 dm,
3152 &dm->fast_ant_training_workitem,
3153 (RT_WORKITEM_CALL_BACK)odm_fast_ant_training_work_item_callback,
3154 (void *)adapter,
3155 "fast_ant_training_workitem");
3156 #endif
3157
3158 #endif /*#if USE_WORKITEM*/
3159
3160 #ifdef PHYDM_BEAMFORMING_SUPPORT
3161 odm_initialize_work_item(
3162 dm,
3163 &dm->beamforming_info.txbf_info.txbf_enter_work_item,
3164 (RT_WORKITEM_CALL_BACK)hal_com_txbf_enter_work_item_callback,
3165 (void *)adapter,
3166 "txbf_enter_work_item");
3167
3168 odm_initialize_work_item(
3169 dm,
3170 &dm->beamforming_info.txbf_info.txbf_leave_work_item,
3171 (RT_WORKITEM_CALL_BACK)hal_com_txbf_leave_work_item_callback,
3172 (void *)adapter,
3173 "txbf_leave_work_item");
3174
3175 odm_initialize_work_item(
3176 dm,
3177 &dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item,
3178 (RT_WORKITEM_CALL_BACK)hal_com_txbf_fw_ndpa_work_item_callback,
3179 (void *)adapter,
3180 "txbf_fw_ndpa_work_item");
3181
3182 odm_initialize_work_item(
3183 dm,
3184 &dm->beamforming_info.txbf_info.txbf_clk_work_item,
3185 (RT_WORKITEM_CALL_BACK)hal_com_txbf_clk_work_item_callback,
3186 (void *)adapter,
3187 "txbf_clk_work_item");
3188
3189 odm_initialize_work_item(
3190 dm,
3191 &dm->beamforming_info.txbf_info.txbf_rate_work_item,
3192 (RT_WORKITEM_CALL_BACK)hal_com_txbf_rate_work_item_callback,
3193 (void *)adapter,
3194 "txbf_rate_work_item");
3195
3196 odm_initialize_work_item(
3197 dm,
3198 &dm->beamforming_info.txbf_info.txbf_status_work_item,
3199 (RT_WORKITEM_CALL_BACK)hal_com_txbf_status_work_item_callback,
3200 (void *)adapter,
3201 "txbf_status_work_item");
3202
3203 odm_initialize_work_item(
3204 dm,
3205 &dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item,
3206 (RT_WORKITEM_CALL_BACK)hal_com_txbf_reset_tx_path_work_item_callback,
3207 (void *)adapter,
3208 "txbf_reset_tx_path_work_item");
3209
3210 odm_initialize_work_item(
3211 dm,
3212 &dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item,
3213 (RT_WORKITEM_CALL_BACK)hal_com_txbf_get_tx_rate_work_item_callback,
3214 (void *)adapter,
3215 "txbf_get_tx_rate_work_item");
3216 #endif
3217
3218 #if (PHYDM_LA_MODE_SUPPORT == 1)
3219 odm_initialize_work_item(
3220 dm,
3221 &dm->adcsmp.adc_smp_work_item,
3222 (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
3223 (void *)adapter,
3224 "adc_smp_work_item");
3225
3226 odm_initialize_work_item(
3227 dm,
3228 &dm->adcsmp.adc_smp_work_item_1,
3229 (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
3230 (void *)adapter,
3231 "adc_smp_work_item_1");
3232 #endif
3233 }
3234
odm_free_all_work_items(struct dm_struct * dm)3235 void odm_free_all_work_items(struct dm_struct *dm)
3236 {
3237 #if USE_WORKITEM
3238
3239 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
3240 odm_free_work_item(&dm->dm_swat_table.phydm_sw_antenna_switch_workitem);
3241 #endif
3242
3243 #ifdef CONFIG_ADAPTIVE_SOML
3244 odm_free_work_item(&dm->dm_soml_table.phydm_adaptive_soml_workitem);
3245 #endif
3246
3247 #ifdef ODM_EVM_ENHANCE_ANTDIV
3248 odm_free_work_item(&dm->phydm_evm_antdiv_workitem);
3249 #endif
3250
3251 #if (defined(CONFIG_HL_SMART_ANTENNA))
3252 odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_workitem);
3253 odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_decision_workitem);
3254 #endif
3255
3256 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
3257 odm_free_work_item(&dm->fast_ant_training_workitem);
3258 #endif
3259 odm_free_work_item(&dm->ra_rpt_workitem);
3260 /*odm_free_work_item((&dm->sbdcnt_workitem));*/
3261 #endif
3262
3263 #ifdef PHYDM_BEAMFORMING_SUPPORT
3264 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_enter_work_item));
3265 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_leave_work_item));
3266 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item));
3267 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_clk_work_item));
3268 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_rate_work_item));
3269 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_status_work_item));
3270 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item));
3271 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item));
3272 #endif
3273
3274 #if (PHYDM_LA_MODE_SUPPORT == 1)
3275 odm_free_work_item((&dm->adcsmp.adc_smp_work_item));
3276 odm_free_work_item((&dm->adcsmp.adc_smp_work_item_1));
3277 #endif
3278 }
3279 #endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
3280
odm_init_all_timers(struct dm_struct * dm)3281 void odm_init_all_timers(struct dm_struct *dm)
3282 {
3283 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
3284 odm_ant_div_timers(dm, INIT_ANTDIV_TIMMER);
3285 #endif
3286 #if (defined(PHYDM_TDMA_DIG_SUPPORT))
3287 #ifdef IS_USE_NEW_TDMA
3288 phydm_tdma_dig_timers(dm, INIT_TDMA_DIG_TIMMER);
3289 #endif
3290 #endif
3291 #ifdef CONFIG_ADAPTIVE_SOML
3292 phydm_adaptive_soml_timers(dm, INIT_SOML_TIMMER);
3293 #endif
3294 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
3295 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
3296 phydm_lna_sat_chk_timers(dm, INIT_LNA_SAT_CHK_TIMMER);
3297 #endif
3298 #endif
3299
3300 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3301 odm_initialize_timer(dm, &dm->sbdcnt_timer,
3302 (void *)phydm_sbd_callback, NULL, "SbdTimer");
3303 #ifdef PHYDM_BEAMFORMING_SUPPORT
3304 odm_initialize_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer,
3305 (void *)hal_com_txbf_fw_ndpa_timer_callback, NULL,
3306 "txbf_fw_ndpa_timer");
3307 #endif
3308 #endif
3309
3310 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3311 #ifdef PHYDM_BEAMFORMING_SUPPORT
3312 odm_initialize_timer(dm, &dm->beamforming_info.beamforming_timer,
3313 (void *)beamforming_sw_timer_callback, NULL,
3314 "beamforming_timer");
3315 #endif
3316 #endif
3317 }
3318
odm_cancel_all_timers(struct dm_struct * dm)3319 void odm_cancel_all_timers(struct dm_struct *dm)
3320 {
3321 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3322 /* @2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in win7*/
3323 if (dm->adapter == NULL)
3324 return;
3325 #endif
3326
3327 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
3328 odm_ant_div_timers(dm, CANCEL_ANTDIV_TIMMER);
3329 #endif
3330 #ifdef PHYDM_TDMA_DIG_SUPPORT
3331 #ifdef IS_USE_NEW_TDMA
3332 phydm_tdma_dig_timers(dm, CANCEL_TDMA_DIG_TIMMER);
3333 #endif
3334 #endif
3335 #ifdef CONFIG_ADAPTIVE_SOML
3336 phydm_adaptive_soml_timers(dm, CANCEL_SOML_TIMMER);
3337 #endif
3338 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
3339 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
3340 phydm_lna_sat_chk_timers(dm, CANCEL_LNA_SAT_CHK_TIMMER);
3341 #endif
3342 #endif
3343
3344 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3345 odm_cancel_timer(dm, &dm->sbdcnt_timer);
3346 #ifdef PHYDM_BEAMFORMING_SUPPORT
3347 odm_cancel_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
3348 #endif
3349 #endif
3350
3351 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3352 #ifdef PHYDM_BEAMFORMING_SUPPORT
3353 odm_cancel_timer(dm, &dm->beamforming_info.beamforming_timer);
3354 #endif
3355 #endif
3356 }
3357
odm_release_all_timers(struct dm_struct * dm)3358 void odm_release_all_timers(struct dm_struct *dm)
3359 {
3360 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
3361 odm_ant_div_timers(dm, RELEASE_ANTDIV_TIMMER);
3362 #endif
3363 #ifdef PHYDM_TDMA_DIG_SUPPORT
3364 #ifdef IS_USE_NEW_TDMA
3365 phydm_tdma_dig_timers(dm, RELEASE_TDMA_DIG_TIMMER);
3366 #endif
3367 #endif
3368 #ifdef CONFIG_ADAPTIVE_SOML
3369 phydm_adaptive_soml_timers(dm, RELEASE_SOML_TIMMER);
3370 #endif
3371 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
3372 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
3373 phydm_lna_sat_chk_timers(dm, RELEASE_LNA_SAT_CHK_TIMMER);
3374 #endif
3375 #endif
3376
3377 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3378 odm_release_timer(dm, &dm->sbdcnt_timer);
3379 #ifdef PHYDM_BEAMFORMING_SUPPORT
3380 odm_release_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
3381 #endif
3382 #endif
3383
3384 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3385 #ifdef PHYDM_BEAMFORMING_SUPPORT
3386 odm_release_timer(dm, &dm->beamforming_info.beamforming_timer);
3387 #endif
3388 #endif
3389 }
3390
3391 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
odm_init_all_threads(struct dm_struct * dm)3392 void odm_init_all_threads(
3393 struct dm_struct *dm)
3394 {
3395 #ifdef TPT_THREAD
3396 k_tpt_task_init(dm->priv);
3397 #endif
3398 }
3399
odm_stop_all_threads(struct dm_struct * dm)3400 void odm_stop_all_threads(
3401 struct dm_struct *dm)
3402 {
3403 #ifdef TPT_THREAD
3404 k_tpt_task_stop(dm->priv);
3405 #endif
3406 }
3407 #endif
3408
3409 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3410 /* @Justin: According to the current RRSI to adjust Response Frame TX power,
3411 * 2012/11/05
3412 */
odm_dtc(struct dm_struct * dm)3413 void odm_dtc(struct dm_struct *dm)
3414 {
3415 #ifdef CONFIG_DM_RESP_TXAGC
3416 /* RSSI higher than this value, start to decade TX power */
3417 #define DTC_BASE 35
3418
3419 /* RSSI lower than this value, start to increase TX power */
3420 #define DTC_DWN_BASE (DTC_BASE - 5)
3421
3422 /* RSSI vs TX power step mapping: decade TX power */
3423 static const u8 dtc_table_down[] = {
3424 DTC_BASE,
3425 (DTC_BASE + 5),
3426 (DTC_BASE + 10),
3427 (DTC_BASE + 15),
3428 (DTC_BASE + 20),
3429 (DTC_BASE + 25)};
3430
3431 /* RSSI vs TX power step mapping: increase TX power */
3432 static const u8 dtc_table_up[] = {
3433 DTC_DWN_BASE,
3434 (DTC_DWN_BASE - 5),
3435 (DTC_DWN_BASE - 10),
3436 (DTC_DWN_BASE - 15),
3437 (DTC_DWN_BASE - 15),
3438 (DTC_DWN_BASE - 20),
3439 (DTC_DWN_BASE - 20),
3440 (DTC_DWN_BASE - 25),
3441 (DTC_DWN_BASE - 25),
3442 (DTC_DWN_BASE - 30),
3443 (DTC_DWN_BASE - 35)};
3444
3445 u8 i;
3446 u8 dtc_steps = 0;
3447 u8 sign;
3448 u8 resp_txagc = 0;
3449
3450 if (dm->rssi_min > DTC_BASE) {
3451 /* need to decade the CTS TX power */
3452 sign = 1;
3453 for (i = 0; i < ARRAY_SIZE(dtc_table_down); i++) {
3454 if (dtc_table_down[i] >= dm->rssi_min || dtc_steps >= 6)
3455 break;
3456 else
3457 dtc_steps++;
3458 }
3459 }
3460 #if 0
3461 else if (dm->rssi_min > DTC_DWN_BASE) {
3462 /* needs to increase the CTS TX power */
3463 sign = 0;
3464 dtc_steps = 1;
3465 for (i = 0; i < ARRAY_SIZE(dtc_table_up); i++) {
3466 if (dtc_table_up[i] <= dm->rssi_min || dtc_steps >= 10)
3467 break;
3468 else
3469 dtc_steps++;
3470 }
3471 }
3472 #endif
3473 else {
3474 sign = 0;
3475 dtc_steps = 0;
3476 }
3477
3478 resp_txagc = dtc_steps | (sign << 4);
3479 resp_txagc = resp_txagc | (resp_txagc << 5);
3480 odm_write_1byte(dm, 0x06d9, resp_txagc);
3481
3482 PHYDM_DBG(dm, ODM_COMP_PWR_TRAIN,
3483 "%s rssi_min:%u, set RESP_TXAGC to %s %u\n", __func__,
3484 dm->rssi_min, sign ? "minus" : "plus", dtc_steps);
3485 #endif /* @CONFIG_RESP_TXAGC_ADJUST */
3486 }
3487
3488 #endif /* @#if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
3489
3490 /*@<20170126, BB-Kevin>8188F D-CUT DC cancellation and 8821C*/
phydm_dc_cancellation(struct dm_struct * dm)3491 void phydm_dc_cancellation(struct dm_struct *dm)
3492 {
3493 #ifdef PHYDM_DC_CANCELLATION
3494 u32 offset_i_hex[PHYDM_MAX_RF_PATH] = {0};
3495 u32 offset_q_hex[PHYDM_MAX_RF_PATH] = {0};
3496 u32 reg_value32[PHYDM_MAX_RF_PATH] = {0};
3497 u8 path = RF_PATH_A;
3498 u8 set_result;
3499
3500 if (!(dm->support_ic_type & ODM_DC_CANCELLATION_SUPPORT))
3501 return;
3502 if ((dm->support_ic_type & ODM_RTL8188F) &&
3503 dm->cut_version < ODM_CUT_D)
3504 return;
3505 if ((dm->support_ic_type & ODM_RTL8192F) &&
3506 dm->cut_version == ODM_CUT_A)
3507 return;
3508 if (*dm->band_width == CHANNEL_WIDTH_5)
3509 return;
3510 if (*dm->band_width == CHANNEL_WIDTH_10)
3511 return;
3512
3513 PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
3514
3515 /*@DC_Estimation (only for 2x2 ic now) */
3516
3517 for (path = RF_PATH_A; path < PHYDM_MAX_RF_PATH; path++) {
3518 if (path > RF_PATH_A &&
3519 dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8188F |
3520 ODM_RTL8710B | ODM_RTL8721D |
3521 ODM_RTL8710C | ODM_RTL8723D))
3522 break;
3523 else if (path > RF_PATH_B &&
3524 dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8192F))
3525 break;
3526 if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
3527 PHYDM_DBG(dm, ODM_COMP_API, "STOP_TRX_FAIL\n");
3528 return;
3529 }
3530 odm_write_dig(dm, 0x7e);
3531 /*@Disable LNA*/
3532 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D |
3533 ODM_RTL8710C))
3534 halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE);
3535 /*Turn off 3-wire*/
3536 phydm_stop_3_wire(dm, PHYDM_SET);
3537 if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8723D |
3538 ODM_RTL8710B)) {
3539 /*set debug port to 0x235*/
3540 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
3541 PHYDM_DBG(dm, ODM_COMP_API,
3542 "Set Debug port Fail\n");
3543 return;
3544 }
3545 } else if (dm->support_ic_type & (ODM_RTL8721D |
3546 ODM_RTL8710C)) {
3547 /*set debug port to 0x200*/
3548 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x200)) {
3549 PHYDM_DBG(dm, ODM_COMP_API,
3550 "Set Debug port Fail\n");
3551 return;
3552 }
3553 } else if (dm->support_ic_type & ODM_RTL8821C) {
3554 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
3555 /*set debug port to 0x200*/
3556 PHYDM_DBG(dm, ODM_COMP_API,
3557 "Set Debug port Fail\n");
3558 return;
3559 }
3560 phydm_bb_dbg_port_header_sel(dm, 0x0);
3561 } else if (dm->support_ic_type & ODM_RTL8822B) {
3562 if (path == RF_PATH_A &&
3563 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
3564 /*set debug port to 0x200*/
3565 PHYDM_DBG(dm, ODM_COMP_API,
3566 "Set Debug port Fail\n");
3567 return;
3568 }
3569 if (path == RF_PATH_B &&
3570 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x202)) {
3571 /*set debug port to 0x200*/
3572 PHYDM_DBG(dm, ODM_COMP_API,
3573 "Set Debug port Fail\n");
3574 return;
3575 }
3576 phydm_bb_dbg_port_header_sel(dm, 0x0);
3577 } else if (dm->support_ic_type & ODM_RTL8192F) {
3578 if (path == RF_PATH_A &&
3579 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
3580 /*set debug port to 0x235*/
3581 PHYDM_DBG(dm, ODM_COMP_API,
3582 "Set Debug port Fail\n");
3583 return;
3584 }
3585 if (path == RF_PATH_B &&
3586 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x23d)) {
3587 /*set debug port to 0x23d*/
3588 PHYDM_DBG(dm, ODM_COMP_API,
3589 "Set Debug port Fail\n");
3590 return;
3591 }
3592 }
3593
3594 /*@disable CCK DCNF*/
3595 odm_set_bb_reg(dm, R_0xa78, MASKBYTE1, 0x0);
3596
3597 PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation Begin!!!\n");
3598
3599 phydm_stop_ck320(dm, true); /*stop ck320*/
3600
3601 /* the same debug port both for path-a and path-b*/
3602 reg_value32[path] = phydm_get_bb_dbg_port_val(dm);
3603
3604 phydm_stop_ck320(dm, false); /*start ck320*/
3605
3606 phydm_release_bb_dbg_port(dm);
3607 /* @Turn on 3-wire*/
3608 phydm_stop_3_wire(dm, PHYDM_REVERT);
3609 /* @Enable LNA*/
3610 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D |
3611 ODM_RTL8710C))
3612 halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE);
3613
3614 odm_write_dig(dm, 0x20);
3615
3616 set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT);
3617
3618 PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation OK!!!\n");
3619 }
3620
3621 /*@DC_Cancellation*/
3622 /*@DC compensation to CCK data path*/
3623 odm_set_bb_reg(dm, R_0xa9c, BIT(20), 0x1);
3624 if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8723D |
3625 ODM_RTL8710B)) {
3626 offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
3627 offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
3628
3629 /*@Before filling into registers,
3630 *offset should be multiplexed (-1)
3631 */
3632 offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
3633 (0x400 - offset_i_hex[0]) :
3634 (0x1ff - offset_i_hex[0]);
3635 offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
3636 (0x400 - offset_q_hex[0]) :
3637 (0x1ff - offset_q_hex[0]);
3638
3639 odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
3640 odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
3641 } else if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) {
3642 /* Path-a */
3643 offset_i_hex[0] = (reg_value32[0] & 0xffc00) >> 10;
3644 offset_q_hex[0] = reg_value32[0] & 0x3ff;
3645
3646 /*@Before filling into registers,
3647 *offset should be multiplexed (-1)
3648 */
3649 offset_i_hex[0] = 0x400 - offset_i_hex[0];
3650 offset_q_hex[0] = 0x400 - offset_q_hex[0];
3651
3652 odm_set_bb_reg(dm, R_0xc10, 0x3c000000,
3653 (0x3c0 & offset_i_hex[0]) >> 6);
3654 odm_set_bb_reg(dm, R_0xc10, 0xfc00, 0x3f & offset_i_hex[0]);
3655 odm_set_bb_reg(dm, R_0xc14, 0x3c000000,
3656 (0x3c0 & offset_q_hex[0]) >> 6);
3657 odm_set_bb_reg(dm, R_0xc14, 0xfc00, 0x3f & offset_q_hex[0]);
3658
3659 /* Path-b */
3660 if (dm->rf_type > RF_1T1R) {
3661 offset_i_hex[1] = (reg_value32[1] & 0xffc00) >> 10;
3662 offset_q_hex[1] = reg_value32[1] & 0x3ff;
3663
3664 /*@Before filling into registers,
3665 *offset should be multiplexed (-1)
3666 */
3667 offset_i_hex[1] = 0x400 - offset_i_hex[1];
3668 offset_q_hex[1] = 0x400 - offset_q_hex[1];
3669
3670 odm_set_bb_reg(dm, R_0xe10, 0x3c000000,
3671 (0x3c0 & offset_i_hex[1]) >> 6);
3672 odm_set_bb_reg(dm, R_0xe10, 0xfc00,
3673 0x3f & offset_i_hex[1]);
3674 odm_set_bb_reg(dm, R_0xe14, 0x3c000000,
3675 (0x3c0 & offset_q_hex[1]) >> 6);
3676 odm_set_bb_reg(dm, R_0xe14, 0xfc00,
3677 0x3f & offset_q_hex[1]);
3678 }
3679 } else if (dm->support_ic_type & (ODM_RTL8192F)) {
3680 /* Path-a I:df4[27:18],Q:df4[17:8]*/
3681 offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
3682 offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
3683
3684 /*@Before filling into registers,
3685 *offset should be multiplexed (-1)
3686 */
3687 offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
3688 (0x400 - offset_i_hex[0]) :
3689 (0xff - offset_i_hex[0]);
3690 offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
3691 (0x400 - offset_q_hex[0]) :
3692 (0xff - offset_q_hex[0]);
3693 /*Path-a I:c10[7:0],Q:c10[15:8]*/
3694 odm_set_bb_reg(dm, R_0xc10, 0xff, offset_i_hex[0]);
3695 odm_set_bb_reg(dm, R_0xc10, 0xff00, offset_q_hex[0]);
3696
3697 /* Path-b */
3698 if (dm->rf_type > RF_1T1R) {
3699 /* @I:df4[27:18],Q:df4[17:8]*/
3700 offset_i_hex[1] = (reg_value32[1] & 0xffc0000) >> 18;
3701 offset_q_hex[1] = (reg_value32[1] & 0x3ff00) >> 8;
3702
3703 /*@Before filling into registers,
3704 *offset should be multiplexed (-1)
3705 */
3706 offset_i_hex[1] = (offset_i_hex[1] >= 0x200) ?
3707 (0x400 - offset_i_hex[1]) :
3708 (0xff - offset_i_hex[1]);
3709 offset_q_hex[1] = (offset_q_hex[1] >= 0x200) ?
3710 (0x400 - offset_q_hex[1]) :
3711 (0xff - offset_q_hex[1]);
3712 /*Path-b I:c18[7:0],Q:c18[15:8]*/
3713 odm_set_bb_reg(dm, R_0xc18, 0xff, offset_i_hex[1]);
3714 odm_set_bb_reg(dm, R_0xc18, 0xff00, offset_q_hex[1]);
3715 }
3716 } else if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C)) {
3717 /*judy modified 20180517*/
3718 offset_i_hex[0] = (reg_value32[0] & 0xff80000) >> 19;
3719 offset_q_hex[0] = (reg_value32[0] & 0x3fe00) >> 9;
3720
3721 if ((offset_i_hex[0] > 0xF && offset_i_hex[0] < 0x1F1)
3722 || (offset_q_hex[0] > 0xF && offset_q_hex[0] < 0x1F1)) {
3723 /*@Discard outliers*/
3724 offset_i_hex[0] = 0x0;
3725 offset_q_hex[0] = 0x0;
3726 } else {
3727 /*@Before filling into registers,
3728 *offset should be multiplexed (-1)
3729 */
3730 offset_i_hex[0] = 0x200 - offset_i_hex[0];
3731 offset_q_hex[0] = 0x200 - offset_q_hex[0];
3732 }
3733 odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
3734 odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
3735 }
3736 #endif
3737 }
3738
phydm_receiver_blocking(void * dm_void)3739 void phydm_receiver_blocking(void *dm_void)
3740 {
3741 #ifdef CONFIG_RECEIVER_BLOCKING
3742 struct dm_struct *dm = (struct dm_struct *)dm_void;
3743 u32 chnl = *dm->channel;
3744 u8 bw = *dm->band_width;
3745 u32 bb_regf0 = odm_get_bb_reg(dm, R_0xf0, 0xf000);
3746
3747 if (!(dm->support_ic_type & ODM_RECEIVER_BLOCKING_SUPPORT) ||
3748 *dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
3749 return;
3750
3751 if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 < 8) ||
3752 dm->support_ic_type & ODM_RTL8192E) {
3753 /*@8188E_T version*/
3754 if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
3755 goto end;
3756
3757 if (bw == CHANNEL_WIDTH_20 && chnl == 1) {
3758 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2410,
3759 PHYDM_DONT_CARE);
3760 dm->is_rx_blocking_en = true;
3761 } else if ((bw == CHANNEL_WIDTH_20) && (chnl == 13)) {
3762 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
3763 PHYDM_DONT_CARE);
3764 dm->is_rx_blocking_en = true;
3765 } else if (dm->is_rx_blocking_en && chnl != 1 && chnl != 13) {
3766 phydm_nbi_enable(dm, FUNC_DISABLE);
3767 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3768 dm->is_rx_blocking_en = false;
3769 }
3770 return;
3771 } else if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 >= 8)) {
3772 /*@8188E_S version*/
3773 if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
3774 goto end;
3775
3776 if (bw == CHANNEL_WIDTH_20 && chnl == 13) {
3777 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
3778 PHYDM_DONT_CARE);
3779 dm->is_rx_blocking_en = true;
3780 } else if (dm->is_rx_blocking_en && chnl != 13) {
3781 phydm_nbi_enable(dm, FUNC_DISABLE);
3782 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3783 dm->is_rx_blocking_en = false;
3784 }
3785 return;
3786 }
3787
3788 end:
3789 if (dm->is_rx_blocking_en) {
3790 phydm_nbi_enable(dm, FUNC_DISABLE);
3791 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3792 dm->is_rx_blocking_en = false;
3793 }
3794 #endif
3795 }
3796
phydm_dyn_bw_indication(void * dm_void)3797 void phydm_dyn_bw_indication(void *dm_void)
3798 {
3799 #ifdef CONFIG_BW_INDICATION
3800 struct dm_struct *dm = (struct dm_struct *)dm_void;
3801 u8 en_auto_bw_th = dm->en_auto_bw_th;
3802
3803 if (!(dm->support_ic_type & ODM_DYM_BW_INDICATION_SUPPORT))
3804 return;
3805
3806 /*driver decide bw cobime timing*/
3807 if (dm->dis_dym_bw_indication) {
3808 if (*dm->dis_dym_bw_indication)
3809 return;
3810 }
3811
3812 /*check for auto bw*/
3813 if (dm->rssi_min <= en_auto_bw_th && dm->is_linked) {
3814 phydm_bw_fixed_enable(dm, FUNC_DISABLE);
3815 return;
3816 }
3817
3818 phydm_bw_fixed_setting(dm);
3819 #endif
3820 }
3821
3822