1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2017 Realtek Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 *****************************************************************************/ 16 #ifndef __GSPI_OPS_H__ 17 #define __GSPI_OPS_H__ 18 19 /* follwing defination is based on 20 * GSPI spec of RTL8723, we temp 21 * suppose that it will be the same 22 * for diff chips of GSPI, if not 23 * we should move it to HAL folder */ 24 #define SPI_LOCAL_DOMAIN 0x0 25 #define WLAN_IOREG_DOMAIN 0x8 26 #define FW_FIFO_DOMAIN 0x4 27 #define TX_HIQ_DOMAIN 0xc 28 #define TX_MIQ_DOMAIN 0xd 29 #define TX_LOQ_DOMAIN 0xe 30 #define RX_RXFIFO_DOMAIN 0x1f 31 32 /* IO Bus domain address mapping */ 33 #define DEFUALT_OFFSET 0x0 34 #define SPI_LOCAL_OFFSET 0x10250000 35 #define WLAN_IOREG_OFFSET 0x10260000 36 #define FW_FIFO_OFFSET 0x10270000 37 #define TX_HIQ_OFFSET 0x10310000 38 #define TX_MIQ_OFFSET 0x1032000 39 #define TX_LOQ_OFFSET 0x10330000 40 #define RX_RXOFF_OFFSET 0x10340000 41 42 /* SPI Local registers */ 43 #define SPI_REG_TX_CTRL 0x0000 /* SPI Tx Control */ 44 #define SPI_REG_STATUS_RECOVERY 0x0004 45 #define SPI_REG_INT_TIMEOUT 0x0006 46 #define SPI_REG_HIMR 0x0014 /* SPI Host Interrupt Mask */ 47 #define SPI_REG_HISR 0x0018 /* SPI Host Interrupt Service Routine */ 48 #define SPI_REG_RX0_REQ_LEN 0x001C /* RXDMA Request Length */ 49 #define SPI_REG_FREE_TXPG 0x0020 /* Free Tx Buffer Page */ 50 #define SPI_REG_HCPWM1 0x0024 /* HCI Current Power Mode 1 */ 51 #define SPI_REG_HCPWM2 0x0026 /* HCI Current Power Mode 2 */ 52 #define SPI_REG_HTSFR_INFO 0x0030 /* HTSF Informaion */ 53 #define SPI_REG_HRPWM1 0x0080 /* HCI Request Power Mode 1 */ 54 #define SPI_REG_HRPWM2 0x0082 /* HCI Request Power Mode 2 */ 55 #define SPI_REG_HPS_CLKR 0x0084 /* HCI Power Save Clock */ 56 #define SPI_REG_HSUS_CTRL 0x0086 /* SPI HCI Suspend Control */ 57 #define SPI_REG_HIMR_ON 0x0090 /* SPI Host Extension Interrupt Mask Always */ 58 #define SPI_REG_HISR_ON 0x0091 /* SPI Host Extension Interrupt Status Always */ 59 #define SPI_REG_CFG 0x00F0 /* SPI Configuration Register */ 60 61 #define SPI_TX_CTRL (SPI_REG_TX_CTRL | SPI_LOCAL_OFFSET) 62 #define SPI_STATUS_RECOVERY (SPI_REG_STATUS_RECOVERY | SPI_LOCAL_OFFSET) 63 #define SPI_INT_TIMEOUT (SPI_REG_INT_TIMEOUT | SPI_LOCAL_OFFSET) 64 #define SPI_HIMR (SPI_REG_HIMR | SPI_LOCAL_OFFSET) 65 #define SPI_HISR (SPI_REG_HISR | SPI_LOCAL_OFFSET) 66 #define SPI_RX0_REQ_LEN_1_BYTE (SPI_REG_RX0_REQ_LEN | SPI_LOCAL_OFFSET) 67 #define SPI_FREE_TXPG (SPI_REG_FREE_TXPG | SPI_LOCAL_OFFSET) 68 69 #define SPI_HIMR_DISABLED 0 70 71 /* SPI HIMR MASK diff with SDIO */ 72 #define SPI_HISR_RX_REQUEST BIT(0) 73 #define SPI_HISR_AVAL BIT(1) 74 #define SPI_HISR_TXERR BIT(2) 75 #define SPI_HISR_RXERR BIT(3) 76 #define SPI_HISR_TXFOVW BIT(4) 77 #define SPI_HISR_RXFOVW BIT(5) 78 #define SPI_HISR_TXBCNOK BIT(6) 79 #define SPI_HISR_TXBCNERR BIT(7) 80 #define SPI_HISR_BCNERLY_INT BIT(16) 81 #define SPI_HISR_ATIMEND BIT(17) 82 #define SPI_HISR_ATIMEND_E BIT(18) 83 #define SPI_HISR_CTWEND BIT(19) 84 #define SPI_HISR_C2HCMD BIT(20) 85 #define SPI_HISR_CPWM1 BIT(21) 86 #define SPI_HISR_CPWM2 BIT(22) 87 #define SPI_HISR_HSISR_IND BIT(23) 88 #define SPI_HISR_GTINT3_IND BIT(24) 89 #define SPI_HISR_GTINT4_IND BIT(25) 90 #define SPI_HISR_PSTIMEOUT BIT(26) 91 #define SPI_HISR_OCPINT BIT(27) 92 #define SPI_HISR_TSF_BIT32_TOGGLE BIT(29) 93 94 #define MASK_SPI_HISR_CLEAR (SPI_HISR_TXERR |\ 95 SPI_HISR_RXERR |\ 96 SPI_HISR_TXFOVW |\ 97 SPI_HISR_RXFOVW |\ 98 SPI_HISR_TXBCNOK |\ 99 SPI_HISR_TXBCNERR |\ 100 SPI_HISR_C2HCMD |\ 101 SPI_HISR_CPWM1 |\ 102 SPI_HISR_CPWM2 |\ 103 SPI_HISR_HSISR_IND |\ 104 SPI_HISR_GTINT3_IND |\ 105 SPI_HISR_GTINT4_IND |\ 106 SPI_HISR_PSTIMEOUT |\ 107 SPI_HISR_OCPINT) 108 109 #define REG_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 8, x)/* (x<<(unsigned int)24) */ 110 #define REG_ADDR_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)/* (x<<(unsigned int)16) */ 111 #define REG_DOMAIN_ID_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)/* (x<<(unsigned int)0) */ 112 #define REG_FUN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)/* (x<<(unsigned int)5) */ 113 #define REG_RW_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)/* (x<<(unsigned int)7) */ 114 115 #define FIFO_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 16, x)/* (x<<(unsigned int)24) 116 * #define FIFO_ADDR_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x) */ /* (x<<(unsigned int)16) */ 117 #define FIFO_DOMAIN_ID_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)/* (x<<(unsigned int)0) */ 118 #define FIFO_FUN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)/* (x<<(unsigned int)5) */ 119 #define FIFO_RW_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)/* (x<<(unsigned int)7) */ 120 121 122 /* get status dword0 */ 123 #define GET_STATUS_PUB_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 24, 8) 124 #define GET_STATUS_HI_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 18, 6) 125 #define GET_STATUS_MID_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 12, 6) 126 #define GET_STATUS_LOW_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 6, 6) 127 #define GET_STATUS_HISR_HI6BIT(status) LE_BITS_TO_4BYTE(status, 0, 6) 128 129 /* get status dword1 */ 130 #define GET_STATUS_HISR_MID8BIT(status) LE_BITS_TO_4BYTE(status + 4, 24, 8) 131 #define GET_STATUS_HISR_LOW8BIT(status) LE_BITS_TO_4BYTE(status + 4, 16, 8) 132 #define GET_STATUS_ERROR(status) LE_BITS_TO_4BYTE(status + 4, 17, 1) 133 #define GET_STATUS_INT(status) LE_BITS_TO_4BYTE(status + 4, 16, 1) 134 #define GET_STATUS_RX_LENGTH(status) LE_BITS_TO_4BYTE(status + 4, 0, 16) 135 136 137 #define RXDESC_SIZE 24 138 139 140 struct spi_more_data { 141 unsigned long more_data; 142 unsigned long len; 143 }; 144 145 #ifdef CONFIG_RTL8188E 146 void rtl8188es_set_hal_ops(PADAPTER padapter); 147 #define set_hal_ops rtl8188es_set_hal_ops 148 #endif 149 extern void spi_set_chip_endian(PADAPTER padapter); 150 extern unsigned int spi_write8_endian(ADAPTER *Adapter, unsigned int addr, unsigned int buf, u32 big); 151 extern void spi_set_intf_ops(_adapter *padapter, struct _io_ops *pops); 152 extern void spi_set_chip_endian(PADAPTER padapter); 153 extern void InitInterrupt8723ASdio(PADAPTER padapter); 154 extern void InitSysInterrupt8723ASdio(PADAPTER padapter); 155 extern void EnableInterrupt8723ASdio(PADAPTER padapter); 156 extern void DisableInterrupt8723ASdio(PADAPTER padapter); 157 extern void spi_int_hdl(PADAPTER padapter); 158 extern u8 HalQueryTxBufferStatus8723ASdio(PADAPTER padapter); 159 #ifdef CONFIG_RTL8723B 160 extern void InitInterrupt8723BSdio(PADAPTER padapter); 161 extern void InitSysInterrupt8723BSdio(PADAPTER padapter); 162 extern void EnableInterrupt8723BSdio(PADAPTER padapter); 163 extern void DisableInterrupt8723BSdio(PADAPTER padapter); 164 extern u8 HalQueryTxBufferStatus8723BSdio(PADAPTER padapter); 165 #endif 166 167 #ifdef CONFIG_RTL8188E 168 extern void InitInterrupt8188EGspi(PADAPTER padapter); 169 extern void EnableInterrupt8188EGspi(PADAPTER padapter); 170 extern void DisableInterrupt8188EGspi(PADAPTER padapter); 171 extern void UpdateInterruptMask8188EGspi(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR); 172 extern u8 HalQueryTxBufferStatus8189EGspi(PADAPTER padapter); 173 extern u8 HalQueryTxOQTBufferStatus8189EGspi(PADAPTER padapter); 174 extern void ClearInterrupt8188EGspi(PADAPTER padapter); 175 extern u8 CheckIPSStatus(PADAPTER padapter); 176 #endif /* CONFIG_RTL8188E */ 177 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) 178 extern u8 RecvOnePkt(PADAPTER padapter); 179 #endif /* CONFIG_WOWLAN */ 180 181 #endif /* __GSPI_OPS_H__ */ 182