1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2017 Realtek Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 *****************************************************************************/ 16 #ifndef __INC_HAL8814PHYREG_H__ 17 #define __INC_HAL8814PHYREG_H__ 18 /*--------------------------Define Parameters-------------------------------*/ 19 /* 20 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF 21 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 22 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 23 * 3. RF register 0x00-2E 24 * 4. Bit Mask for BB/RF register 25 * 5. Other defintion for BB/RF R/W 26 * */ 27 28 29 /* BB Register Definition */ 30 31 #define rCCAonSec_Jaguar 0x838 32 #define rPwed_TH_Jaguar 0x830 33 #define rL1_Weight_Jaguar 0x840 34 #define r_L1_SBD_start_time 0x844 35 36 /* BW and sideband setting */ 37 #define rBWIndication_Jaguar 0x834 38 #define rL1PeakTH_Jaguar 0x848 39 #define rRFMOD_Jaguar 0x8ac /* RF mode */ 40 #define rADC_Buf_Clk_Jaguar 0x8c4 41 #define rADC_Buf_40_Clk_Jaguar2 0x8c8 42 #define rRFECTRL_Jaguar 0x900 43 #define bRFMOD_Jaguar 0xc3 44 #define rCCK_System_Jaguar 0xa00 /* for cck sideband */ 45 #define bCCK_System_Jaguar 0x10 46 47 /* Block & Path enable */ 48 #define rOFDMCCKEN_Jaguar 0x808 /* OFDM/CCK block enable */ 49 #define bOFDMEN_Jaguar 0x20000000 50 #define bCCKEN_Jaguar 0x10000000 51 #define rRxPath_Jaguar 0x808 /* Rx antenna */ 52 #define bRxPath_Jaguar 0xff 53 #define rTxPath_Jaguar 0x80c /* Tx antenna */ 54 #define bTxPath_Jaguar 0x0fffffff 55 #define rCCK_RX_Jaguar 0xa04 /* for cck rx path selection */ 56 #define bCCK_RX_Jaguar 0x0c000000 57 #define rVhtlen_Use_Lsig_Jaguar 0x8c3 /* Use LSIG for VHT length */ 58 59 #define rRxPath_Jaguar2 0xa04 /* Rx antenna */ 60 #define rTxAnt_1Nsts_Jaguar2 0x93c /* Tx antenna for 1Nsts */ 61 #define rTxAnt_23Nsts_Jaguar2 0x940 /* Tx antenna for 2Nsts and 3Nsts */ 62 63 64 /* RF read/write-related */ 65 #define rHSSIRead_Jaguar 0x8b0 /* RF read addr */ 66 #define bHSSIRead_addr_Jaguar 0xff 67 #define bHSSIRead_trigger_Jaguar 0x100 68 #define rA_PIRead_Jaguar 0xd04 /* RF readback with PI */ 69 #define rB_PIRead_Jaguar 0xd44 /* RF readback with PI */ 70 #define rA_SIRead_Jaguar 0xd08 /* RF readback with SI */ 71 #define rB_SIRead_Jaguar 0xd48 /* RF readback with SI */ 72 #define rRead_data_Jaguar 0xfffff 73 #define rA_LSSIWrite_Jaguar 0xc90 /* RF write addr */ 74 #define rB_LSSIWrite_Jaguar 0xe90 /* RF write addr */ 75 #define bLSSIWrite_data_Jaguar 0x000fffff 76 #define bLSSIWrite_addr_Jaguar 0x0ff00000 77 78 #define rC_PIRead_Jaguar2 0xd84 /* RF readback with PI */ 79 #define rD_PIRead_Jaguar2 0xdC4 /* RF readback with PI */ 80 #define rC_SIRead_Jaguar2 0xd88 /* RF readback with SI */ 81 #define rD_SIRead_Jaguar2 0xdC8 /* RF readback with SI */ 82 #define rC_LSSIWrite_Jaguar2 0x1890 /* RF write addr */ 83 #define rD_LSSIWrite_Jaguar2 0x1A90 /* RF write addr */ 84 85 86 /* YN: mask the following register definition temporarily */ 87 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 88 #define rFPGA0_XB_RFInterfaceOE 0x864 89 90 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ 91 #define rFPGA0_XCD_RFInterfaceSW 0x874 92 93 /* #define rFPGA0_XAB_RFParameter 0x878 */ /* RF Parameter 94 * #define rFPGA0_XCD_RFParameter 0x87c */ 95 96 /* #define rFPGA0_AnalogParameter1 0x880 */ /* Crystal cap setting RF-R/W protection for parameter4?? 97 * #define rFPGA0_AnalogParameter2 0x884 98 * #define rFPGA0_AnalogParameter3 0x888 99 * #define rFPGA0_AdDaClockEn 0x888 */ /* enable ad/da clock1 for dual-phy 100 * #define rFPGA0_AnalogParameter4 0x88c */ 101 102 103 /* CCK TX scaling */ 104 #define rCCK_TxFilter1_Jaguar 0xa20 105 #define bCCK_TxFilter1_C0_Jaguar 0x00ff0000 106 #define bCCK_TxFilter1_C1_Jaguar 0xff000000 107 #define rCCK_TxFilter2_Jaguar 0xa24 108 #define bCCK_TxFilter2_C2_Jaguar 0x000000ff 109 #define bCCK_TxFilter2_C3_Jaguar 0x0000ff00 110 #define bCCK_TxFilter2_C4_Jaguar 0x00ff0000 111 #define bCCK_TxFilter2_C5_Jaguar 0xff000000 112 #define rCCK_TxFilter3_Jaguar 0xa28 113 #define bCCK_TxFilter3_C6_Jaguar 0x000000ff 114 #define bCCK_TxFilter3_C7_Jaguar 0x0000ff00 115 /* NBI & CSI Mask setting */ 116 #define rCSI_Mask_Setting1_Jaguar 0x874 117 #define rCSI_Fix_Mask0_Jaguar 0x880 118 #define rCSI_Fix_Mask1_Jaguar 0x884 119 #define rCSI_Fix_Mask2_Jaguar 0x888 120 #define rCSI_Fix_Mask3_Jaguar 0x88c 121 #define rCSI_Fix_Mask4_Jaguar 0x890 122 #define rCSI_Fix_Mask5_Jaguar 0x894 123 #define rCSI_Fix_Mask6_Jaguar 0x898 124 #define rCSI_Fix_Mask7_Jaguar 0x89c 125 #define rNBI_Setting_Jaguar 0x87c 126 127 128 /* YN: mask the following register definition temporarily 129 * #define rPdp_AntA 0xb00 130 * #define rPdp_AntA_4 0xb04 131 * #define rConfig_Pmpd_AntA 0xb28 132 * #define rConfig_AntA 0xb68 133 * #define rConfig_AntB 0xb6c 134 * #define rPdp_AntB 0xb70 135 * #define rPdp_AntB_4 0xb74 136 * #define rConfig_Pmpd_AntB 0xb98 137 * #define rAPK 0xbd8 */ 138 139 /* RXIQC */ 140 #define rA_RxIQC_AB_Jaguar 0xc10 /* RxIQ imblance matrix coeff. A & B */ 141 #define rA_RxIQC_CD_Jaguar 0xc14 /* RxIQ imblance matrix coeff. C & D */ 142 #define rA_TxScale_Jaguar 0xc1c /* Pah_A TX scaling factor */ 143 #define rB_TxScale_Jaguar 0xe1c /* Path_B TX scaling factor */ 144 #define rB_RxIQC_AB_Jaguar 0xe10 /* RxIQ imblance matrix coeff. A & B */ 145 #define rB_RxIQC_CD_Jaguar 0xe14 /* RxIQ imblance matrix coeff. C & D */ 146 #define b_RxIQC_AC_Jaguar 0x02ff /* bit mask for IQC matrix element A & C */ 147 #define b_RxIQC_BD_Jaguar 0x02ff0000 /* bit mask for IQC matrix element A & C */ 148 149 #define rC_TxScale_Jaguar2 0x181c /* Pah_C TX scaling factor */ 150 #define rD_TxScale_Jaguar2 0x1A1c /* Path_D TX scaling factor */ 151 #define rRF_TxGainOffset 0x55 152 153 /* DIG-related */ 154 #define rA_IGI_Jaguar 0xc50 /* Initial Gain for path-A */ 155 #define rB_IGI_Jaguar 0xe50 /* Initial Gain for path-B */ 156 #define rC_IGI_Jaguar2 0x1850 /* Initial Gain for path-C */ 157 #define rD_IGI_Jaguar2 0x1A50 /* Initial Gain for path-D */ 158 159 #define rOFDM_FalseAlarm1_Jaguar 0xf48 /* counter for break */ 160 #define rOFDM_FalseAlarm2_Jaguar 0xf4c /* counter for spoofing */ 161 #define rCCK_FalseAlarm_Jaguar 0xa5c /* counter for cck false alarm */ 162 #define b_FalseAlarm_Jaguar 0xffff 163 #define rCCK_CCA_Jaguar 0xa08 /* cca threshold */ 164 #define bCCK_CCA_Jaguar 0x00ff0000 165 166 /* Tx Power Ttraining-related */ 167 #define rA_TxPwrTraing_Jaguar 0xc54 168 #define rB_TxPwrTraing_Jaguar 0xe54 169 170 /* Report-related */ 171 #define rOFDM_ShortCFOAB_Jaguar 0xf60 172 #define rOFDM_LongCFOAB_Jaguar 0xf64 173 #define rOFDM_EndCFOAB_Jaguar 0xf70 174 #define rOFDM_AGCReport_Jaguar 0xf84 175 #define rOFDM_RxSNR_Jaguar 0xf88 176 #define rOFDM_RxEVMCSI_Jaguar 0xf8c 177 #define rOFDM_SIGReport_Jaguar 0xf90 178 179 /* Misc functions */ 180 #define rEDCCA_Jaguar 0x8a4 /* EDCCA */ 181 #define bEDCCA_Jaguar 0xffff 182 #define rAGC_table_Jaguar 0x82c /* AGC tabel select */ 183 #define bAGC_table_Jaguar 0x3 184 #define b_sel5g_Jaguar 0x1000 /* sel5g */ 185 #define b_LNA_sw_Jaguar 0x8000 /* HW/WS control for LNA */ 186 #define rFc_area_Jaguar 0x860 /* fc_area */ 187 #define bFc_area_Jaguar 0x1ffe000 188 #define rSingleTone_ContTx_Jaguar 0x914 189 190 #define rAGC_table_Jaguar2 0x958 /* AGC tabel select */ 191 #define rDMA_trigger_Jaguar2 0x95C /* ADC sample mode */ 192 193 194 /* RFE */ 195 #define rA_RFE_Pinmux_Jaguar 0xcb0 /* Path_A RFE cotrol pinmux */ 196 #define rB_RFE_Pinmux_Jaguar 0xeb0 /* Path_B RFE control pinmux */ 197 #define rA_RFE_Inv_Jaguar 0xcb4 /* Path_A RFE cotrol */ 198 #define rB_RFE_Inv_Jaguar 0xeb4 /* Path_B RFE control */ 199 #define rA_RFE_Jaguar 0xcb8 /* Path_A RFE cotrol */ 200 #define rB_RFE_Jaguar 0xeb8 /* Path_B RFE control */ 201 #define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */ 202 #define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */ 203 #define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */ 204 #define bMask_RFEInv_Jaguar 0x3ff00000 205 #define bMask_AntselPathFollow_Jaguar 0x00030000 206 207 #define rC_RFE_Pinmux_Jaguar 0x18B4 /* Path_C RFE cotrol pinmux */ 208 #define rD_RFE_Pinmux_Jaguar 0x1AB4 /* Path_D RFE cotrol pinmux */ 209 #define rA_RFE_Sel_Jaguar2 0x1990 210 211 212 213 /* TX AGC */ 214 #define rTxAGC_A_CCK11_CCK1_JAguar 0xc20 215 #define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24 216 #define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28 217 #define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c 218 #define rTxAGC_A_MCS7_MCS4_JAguar 0xc30 219 #define rTxAGC_A_MCS11_MCS8_JAguar 0xc34 220 #define rTxAGC_A_MCS15_MCS12_JAguar 0xc38 221 #define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c 222 #define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40 223 #define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44 224 #define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48 225 #define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c 226 #define rTxAGC_B_CCK11_CCK1_JAguar 0xe20 227 #define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24 228 #define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28 229 #define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c 230 #define rTxAGC_B_MCS7_MCS4_JAguar 0xe30 231 #define rTxAGC_B_MCS11_MCS8_JAguar 0xe34 232 #define rTxAGC_B_MCS15_MCS12_JAguar 0xe38 233 #define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c 234 #define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40 235 #define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44 236 #define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48 237 #define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c 238 #define bTxAGC_byte0_Jaguar 0xff 239 #define bTxAGC_byte1_Jaguar 0xff00 240 #define bTxAGC_byte2_Jaguar 0xff0000 241 #define bTxAGC_byte3_Jaguar 0xff000000 242 243 244 /* TX AGC */ 245 #define rTxAGC_A_CCK11_CCK1_Jaguar2 0xc20 246 #define rTxAGC_A_Ofdm18_Ofdm6_Jaguar2 0xc24 247 #define rTxAGC_A_Ofdm54_Ofdm24_Jaguar2 0xc28 248 #define rTxAGC_A_MCS3_MCS0_Jaguar2 0xc2c 249 #define rTxAGC_A_MCS7_MCS4_Jaguar2 0xc30 250 #define rTxAGC_A_MCS11_MCS8_Jaguar2 0xc34 251 #define rTxAGC_A_MCS15_MCS12_Jaguar2 0xc38 252 #define rTxAGC_A_MCS19_MCS16_Jaguar2 0xcd8 253 #define rTxAGC_A_MCS23_MCS20_Jaguar2 0xcdc 254 #define rTxAGC_A_Nss1Index3_Nss1Index0_Jaguar2 0xc3c 255 #define rTxAGC_A_Nss1Index7_Nss1Index4_Jaguar2 0xc40 256 #define rTxAGC_A_Nss2Index1_Nss1Index8_Jaguar2 0xc44 257 #define rTxAGC_A_Nss2Index5_Nss2Index2_Jaguar2 0xc48 258 #define rTxAGC_A_Nss2Index9_Nss2Index6_Jaguar2 0xc4c 259 #define rTxAGC_A_Nss3Index3_Nss3Index0_Jaguar2 0xce0 260 #define rTxAGC_A_Nss3Index7_Nss3Index4_Jaguar2 0xce4 261 #define rTxAGC_A_Nss3Index9_Nss3Index8_Jaguar2 0xce8 262 #define rTxAGC_B_CCK11_CCK1_Jaguar2 0xe20 263 #define rTxAGC_B_Ofdm18_Ofdm6_Jaguar2 0xe24 264 #define rTxAGC_B_Ofdm54_Ofdm24_Jaguar2 0xe28 265 #define rTxAGC_B_MCS3_MCS0_Jaguar2 0xe2c 266 #define rTxAGC_B_MCS7_MCS4_Jaguar2 0xe30 267 #define rTxAGC_B_MCS11_MCS8_Jaguar2 0xe34 268 #define rTxAGC_B_MCS15_MCS12_Jaguar2 0xe38 269 #define rTxAGC_B_MCS19_MCS16_Jaguar2 0xed8 270 #define rTxAGC_B_MCS23_MCS20_Jaguar2 0xedc 271 #define rTxAGC_B_Nss1Index3_Nss1Index0_Jaguar2 0xe3c 272 #define rTxAGC_B_Nss1Index7_Nss1Index4_Jaguar2 0xe40 273 #define rTxAGC_B_Nss2Index1_Nss1Index8_Jaguar2 0xe44 274 #define rTxAGC_B_Nss2Index5_Nss2Index2_Jaguar2 0xe48 275 #define rTxAGC_B_Nss2Index9_Nss2Index6_Jaguar2 0xe4c 276 #define rTxAGC_B_Nss3Index3_Nss3Index0_Jaguar2 0xee0 277 #define rTxAGC_B_Nss3Index7_Nss3Index4_Jaguar2 0xee4 278 #define rTxAGC_B_Nss3Index9_Nss3Index8_Jaguar2 0xee8 279 #define rTxAGC_C_CCK11_CCK1_Jaguar2 0x1820 280 #define rTxAGC_C_Ofdm18_Ofdm6_Jaguar2 0x1824 281 #define rTxAGC_C_Ofdm54_Ofdm24_Jaguar2 0x1828 282 #define rTxAGC_C_MCS3_MCS0_Jaguar2 0x182c 283 #define rTxAGC_C_MCS7_MCS4_Jaguar2 0x1830 284 #define rTxAGC_C_MCS11_MCS8_Jaguar2 0x1834 285 #define rTxAGC_C_MCS15_MCS12_Jaguar2 0x1838 286 #define rTxAGC_C_MCS19_MCS16_Jaguar2 0x18d8 287 #define rTxAGC_C_MCS23_MCS20_Jaguar2 0x18dc 288 #define rTxAGC_C_Nss1Index3_Nss1Index0_Jaguar2 0x183c 289 #define rTxAGC_C_Nss1Index7_Nss1Index4_Jaguar2 0x1840 290 #define rTxAGC_C_Nss2Index1_Nss1Index8_Jaguar2 0x1844 291 #define rTxAGC_C_Nss2Index5_Nss2Index2_Jaguar2 0x1848 292 #define rTxAGC_C_Nss2Index9_Nss2Index6_Jaguar2 0x184c 293 #define rTxAGC_C_Nss3Index3_Nss3Index0_Jaguar2 0x18e0 294 #define rTxAGC_C_Nss3Index7_Nss3Index4_Jaguar2 0x18e4 295 #define rTxAGC_C_Nss3Index9_Nss3Index8_Jaguar2 0x18e8 296 #define rTxAGC_D_CCK11_CCK1_Jaguar2 0x1a20 297 #define rTxAGC_D_Ofdm18_Ofdm6_Jaguar2 0x1a24 298 #define rTxAGC_D_Ofdm54_Ofdm24_Jaguar2 0x1a28 299 #define rTxAGC_D_MCS3_MCS0_Jaguar2 0x1a2c 300 #define rTxAGC_D_MCS7_MCS4_Jaguar2 0x1a30 301 #define rTxAGC_D_MCS11_MCS8_Jaguar2 0x1a34 302 #define rTxAGC_D_MCS15_MCS12_Jaguar2 0x1a38 303 #define rTxAGC_D_MCS19_MCS16_Jaguar2 0x1ad8 304 #define rTxAGC_D_MCS23_MCS20_Jaguar2 0x1adc 305 #define rTxAGC_D_Nss1Index3_Nss1Index0_Jaguar2 0x1a3c 306 #define rTxAGC_D_Nss1Index7_Nss1Index4_Jaguar2 0x1a40 307 #define rTxAGC_D_Nss2Index1_Nss1Index8_Jaguar2 0x1a44 308 #define rTxAGC_D_Nss2Index5_Nss2Index2_Jaguar2 0x1a48 309 #define rTxAGC_D_Nss2Index9_Nss2Index6_Jaguar2 0x1a4c 310 #define rTxAGC_D_Nss3Index3_Nss3Index0_Jaguar2 0x1ae0 311 #define rTxAGC_D_Nss3Index7_Nss3Index4_Jaguar2 0x1ae4 312 #define rTxAGC_D_Nss3Index9_Nss3Index8_Jaguar2 0x1ae8 313 /* IQK YN: temporaily mask this part 314 * #define rFPGA0_IQK 0xe28 315 * #define rTx_IQK_Tone_A 0xe30 316 * #define rRx_IQK_Tone_A 0xe34 317 * #define rTx_IQK_PI_A 0xe38 318 * #define rRx_IQK_PI_A 0xe3c */ 319 320 /* #define rTx_IQK 0xe40 */ 321 /* #define rRx_IQK 0xe44 */ 322 /* #define rIQK_AGC_Pts 0xe48 */ 323 /* #define rIQK_AGC_Rsp 0xe4c */ 324 /* #define rTx_IQK_Tone_B 0xe50 */ 325 /* #define rRx_IQK_Tone_B 0xe54 */ 326 /* #define rTx_IQK_PI_B 0xe58 */ 327 /* #define rRx_IQK_PI_B 0xe5c */ 328 /* #define rIQK_AGC_Cont 0xe60 */ 329 330 331 /* AFE-related */ 332 #define rA_AFEPwr1_Jaguar 0xc60 /* dynamic AFE power control */ 333 #define rA_AFEPwr2_Jaguar 0xc64 /* dynamic AFE power control */ 334 #define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xc68 335 #define rA_Tx_CCKBBON_OFDMRFON_Jaguar 0xc6c 336 #define rA_Tx_OFDMBBON_Tx2Rx_Jaguar 0xc70 337 #define rA_Tx2Tx_RXCCK_Jaguar 0xc74 338 #define rA_Rx_OFDM_WaitRIFS_Jaguar 0xc78 339 #define rA_Rx2Rx_BT_Jaguar 0xc7c 340 #define rA_sleep_nav_Jaguar 0xc80 341 #define rA_pmpd_Jaguar 0xc84 342 #define rB_AFEPwr1_Jaguar 0xe60 /* dynamic AFE power control */ 343 #define rB_AFEPwr2_Jaguar 0xe64 /* dynamic AFE power control */ 344 #define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xe68 345 #define rB_Tx_CCKBBON_OFDMRFON_Jaguar 0xe6c 346 #define rB_Tx_OFDMBBON_Tx2Rx_Jaguar 0xe70 347 #define rB_Tx2Tx_RXCCK_Jaguar 0xe74 348 #define rB_Rx_OFDM_WaitRIFS_Jaguar 0xe78 349 #define rB_Rx2Rx_BT_Jaguar 0xe7c 350 #define rB_sleep_nav_Jaguar 0xe80 351 #define rB_pmpd_Jaguar 0xe84 352 353 354 /* YN: mask these registers temporaily 355 * #define rTx_Power_Before_IQK_A 0xe94 356 * #define rTx_Power_After_IQK_A 0xe9c */ 357 358 /* #define rRx_Power_Before_IQK_A 0xea0 */ 359 /* #define rRx_Power_Before_IQK_A_2 0xea4 */ 360 /* #define rRx_Power_After_IQK_A 0xea8 */ 361 /* #define rRx_Power_After_IQK_A_2 0xeac */ 362 363 /* #define rTx_Power_Before_IQK_B 0xeb4 */ 364 /* #define rTx_Power_After_IQK_B 0xebc */ 365 366 /* #define rRx_Power_Before_IQK_B 0xec0 */ 367 /* #define rRx_Power_Before_IQK_B_2 0xec4 */ 368 /* #define rRx_Power_After_IQK_B 0xec8 */ 369 /* #define rRx_Power_After_IQK_B_2 0xecc */ 370 371 372 /* RSSI Dump */ 373 #define rA_RSSIDump_Jaguar 0xBF0 374 #define rB_RSSIDump_Jaguar 0xBF1 375 #define rS1_RXevmDump_Jaguar 0xBF4 376 #define rS2_RXevmDump_Jaguar 0xBF5 377 #define rA_RXsnrDump_Jaguar 0xBF6 378 #define rB_RXsnrDump_Jaguar 0xBF7 379 #define rA_CfoShortDump_Jaguar 0xBF8 380 #define rB_CfoShortDump_Jaguar 0xBFA 381 #define rA_CfoLongDump_Jaguar 0xBEC 382 #define rB_CfoLongDump_Jaguar 0xBEE 383 384 385 /* RF Register 386 * */ 387 #define RF_AC_Jaguar 0x00 /* */ 388 #define RF_RF_Top_Jaguar 0x07 /* */ 389 #define RF_TXLOK_Jaguar 0x08 /* */ 390 #define RF_TXAPK_Jaguar 0x0B 391 #define RF_CHNLBW_Jaguar 0x18 /* RF channel and BW switch */ 392 #define RF_RCK1_Jaguar 0x1c /* */ 393 #define RF_RCK2_Jaguar 0x1d 394 #define RF_RCK3_Jaguar 0x1e 395 #define RF_ModeTableAddr 0x30 396 #define RF_ModeTableData0 0x31 397 #define RF_ModeTableData1 0x32 398 #define RF_TxLCTank_Jaguar 0x54 399 #define RF_APK_Jaguar 0x63 400 #define RF_LCK 0xB4 401 #define RF_WeLut_Jaguar 0xEF 402 403 #define bRF_CHNLBW_MOD_AG_Jaguar 0x70300 404 #define bRF_CHNLBW_BW 0xc00 405 406 407 /* 408 * RL6052 Register definition 409 * */ 410 #define RF_AC 0x00 /* */ 411 #define RF_IPA_A 0x0C /* */ 412 #define RF_TXBIAS_A 0x0D 413 #define RF_BS_PA_APSET_G9_G11 0x0E 414 #define RF_MODE1 0x10 /* */ 415 #define RF_MODE2 0x11 /* */ 416 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ 417 #define RF_RCK_OS 0x30 /* RF TX PA control */ 418 #define RF_TXPA_G1 0x31 /* RF TX PA control */ 419 #define RF_TXPA_G2 0x32 /* RF TX PA control */ 420 #define RF_TXPA_G3 0x33 /* RF TX PA control */ 421 #define RF_0x52 0x52 422 #define RF_WE_LUT 0xEF 423 424 /* 425 * Bit Mask 426 * 427 * 1. Page1(0x100) */ 428 #define bBBResetB 0x100 /* Useless now? */ 429 #define bGlobalResetB 0x200 430 #define bOFDMTxStart 0x4 431 #define bCCKTxStart 0x8 432 #define bCRC32Debug 0x100 433 #define bPMACLoopback 0x10 434 #define bTxLSIG 0xffffff 435 #define bOFDMTxRate 0xf 436 #define bOFDMTxReserved 0x10 437 #define bOFDMTxLength 0x1ffe0 438 #define bOFDMTxParity 0x20000 439 #define bTxHTSIG1 0xffffff 440 #define bTxHTMCSRate 0x7f 441 #define bTxHTBW 0x80 442 #define bTxHTLength 0xffff00 443 #define bTxHTSIG2 0xffffff 444 #define bTxHTSmoothing 0x1 445 #define bTxHTSounding 0x2 446 #define bTxHTReserved 0x4 447 #define bTxHTAggreation 0x8 448 #define bTxHTSTBC 0x30 449 #define bTxHTAdvanceCoding 0x40 450 #define bTxHTShortGI 0x80 451 #define bTxHTNumberHT_LTF 0x300 452 #define bTxHTCRC8 0x3fc00 453 #define bCounterReset 0x10000 454 #define bNumOfOFDMTx 0xffff 455 #define bNumOfCCKTx 0xffff0000 456 #define bTxIdleInterval 0xffff 457 #define bOFDMService 0xffff0000 458 #define bTxMACHeader 0xffffffff 459 #define bTxDataInit 0xff 460 #define bTxHTMode 0x100 461 #define bTxDataType 0x30000 462 #define bTxRandomSeed 0xffffffff 463 #define bCCKTxPreamble 0x1 464 #define bCCKTxSFD 0xffff0000 465 #define bCCKTxSIG 0xff 466 #define bCCKTxService 0xff00 467 #define bCCKLengthExt 0x8000 468 #define bCCKTxLength 0xffff0000 469 #define bCCKTxCRC16 0xffff 470 #define bCCKTxStatus 0x1 471 #define bOFDMTxStatus 0x2 472 473 474 /* 475 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 476 * 1. Page1(0x100) 477 * */ 478 #define rPMAC_Reset 0x100 479 #define rPMAC_TxStart 0x104 480 #define rPMAC_TxLegacySIG 0x108 481 #define rPMAC_TxHTSIG1 0x10c 482 #define rPMAC_TxHTSIG2 0x110 483 #define rPMAC_PHYDebug 0x114 484 #define rPMAC_TxPacketNum 0x118 485 #define rPMAC_TxIdle 0x11c 486 #define rPMAC_TxMACHeader0 0x120 487 #define rPMAC_TxMACHeader1 0x124 488 #define rPMAC_TxMACHeader2 0x128 489 #define rPMAC_TxMACHeader3 0x12c 490 #define rPMAC_TxMACHeader4 0x130 491 #define rPMAC_TxMACHeader5 0x134 492 #define rPMAC_TxDataType 0x138 493 #define rPMAC_TxRandomSeed 0x13c 494 #define rPMAC_CCKPLCPPreamble 0x140 495 #define rPMAC_CCKPLCPHeader 0x144 496 #define rPMAC_CCKCRC16 0x148 497 #define rPMAC_OFDMRxCRC32OK 0x170 498 #define rPMAC_OFDMRxCRC32Er 0x174 499 #define rPMAC_OFDMRxParityEr 0x178 500 #define rPMAC_OFDMRxCRC8Er 0x17c 501 #define rPMAC_CCKCRxRC16Er 0x180 502 #define rPMAC_CCKCRxRC32Er 0x184 503 #define rPMAC_CCKCRxRC32OK 0x188 504 #define rPMAC_TxStatus 0x18c 505 506 /* 507 * 3. Page8(0x800) 508 * */ 509 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */ 510 511 #define rFPGA0_TxInfo 0x804 /* Status report?? */ 512 #define rFPGA0_PSDFunction 0x808 513 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 514 515 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 516 #define rFPGA0_XA_HSSIParameter2 0x824 517 #define rFPGA0_XB_HSSIParameter1 0x828 518 #define rFPGA0_XB_HSSIParameter2 0x82c 519 520 #define rFPGA0_XA_LSSIParameter 0x840 521 #define rFPGA0_XB_LSSIParameter 0x844 522 523 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 524 #define rFPGA0_XCD_SwitchControl 0x85c 525 526 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 527 #define rFPGA0_XCD_RFParameter 0x87c 528 529 #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ 530 #define rFPGA0_AnalogParameter2 0x884 531 #define rFPGA0_AnalogParameter3 0x888 532 #define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */ 533 #define rFPGA0_AnalogParameter4 0x88c 534 535 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ 536 #define rFPGA0_XB_LSSIReadBack 0x8a4 537 #define rFPGA0_XC_LSSIReadBack 0x8a8 538 #define rFPGA0_XD_LSSIReadBack 0x8ac 539 540 #define rFPGA0_XCD_RFPara 0x8b4 541 #define rFPGA0_PSDReport 0x8b4 /* Useless now */ 542 #define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ 543 #define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ 544 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now */ /* RF Interface Readback Value */ 545 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ 546 547 /* 548 * 4. Page9(0x900) 549 * */ 550 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */ 551 #define REG_BB_TX_PATH_SEL_1_8814A 0x93c 552 #define REG_BB_TX_PATH_SEL_2_8814A 0x940 553 #define rFPGA1_TxBlock 0x904 /* Useless now */ 554 #define rFPGA1_DebugSelect 0x908 /* Useless now */ 555 #define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */ 556 /*Page 19 for TxBF*/ 557 #define REG_BB_TXBF_ANT_SET_BF1_8814A 0x19ac 558 #define REG_BB_TXBF_ANT_SET_BF0_8814A 0x19b4 559 /* 560 * PageA(0xA00) 561 * */ 562 #define rCCK0_System 0xa00 563 #define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */ 564 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 565 #define rCCK0_TxFilter1 0xa20 566 #define rCCK0_TxFilter2 0xa24 567 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 568 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ 569 570 /* 571 * PageB(0xB00) 572 * */ 573 #define rPdp_AntA 0xb00 574 #define rPdp_AntA_4 0xb04 575 #define rConfig_Pmpd_AntA 0xb28 576 #define rConfig_AntA 0xb68 577 #define rConfig_AntB 0xb6c 578 #define rPdp_AntB 0xb70 579 #define rPdp_AntB_4 0xb74 580 #define rConfig_Pmpd_AntB 0xb98 581 #define rAPK 0xbd8 582 583 /* 584 * 6. PageC(0xC00) 585 * */ 586 #define rOFDM0_LSTF 0xc00 587 588 #define rOFDM0_TRxPathEnable 0xc04 589 #define rOFDM0_TRMuxPar 0xc08 590 #define rOFDM0_TRSWIsolation 0xc0c 591 592 #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 593 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ 594 #define rOFDM0_XBRxAFE 0xc18 595 #define rOFDM0_XBRxIQImbalance 0xc1c 596 #define rOFDM0_XCRxAFE 0xc20 597 #define rOFDM0_XCRxIQImbalance 0xc24 598 #define rOFDM0_XDRxAFE 0xc28 599 #define rOFDM0_XDRxIQImbalance 0xc2c 600 601 #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */ 602 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 603 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 604 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 605 606 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 607 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 608 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 609 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 610 611 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 612 #define rOFDM0_XAAGCCore2 0xc54 613 #define rOFDM0_XBAGCCore1 0xc58 614 #define rOFDM0_XBAGCCore2 0xc5c 615 #define rOFDM0_XCAGCCore1 0xc60 616 #define rOFDM0_XCAGCCore2 0xc64 617 #define rOFDM0_XDAGCCore1 0xc68 618 #define rOFDM0_XDAGCCore2 0xc6c 619 620 #define rOFDM0_AGCParameter1 0xc70 621 #define rOFDM0_AGCParameter2 0xc74 622 #define rOFDM0_AGCRSSITable 0xc78 623 #define rOFDM0_HTSTFAGC 0xc7c 624 625 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 626 #define rOFDM0_XATxAFE 0xc84 627 #define rOFDM0_XBTxIQImbalance 0xc88 628 #define rOFDM0_XBTxAFE 0xc8c 629 #define rOFDM0_XCTxIQImbalance 0xc90 630 #define rOFDM0_XCTxAFE 0xc94 631 #define rOFDM0_XDTxIQImbalance 0xc98 632 #define rOFDM0_XDTxAFE 0xc9c 633 634 #define rOFDM0_RxIQExtAnta 0xca0 635 #define rOFDM0_TxCoeff1 0xca4 636 #define rOFDM0_TxCoeff2 0xca8 637 #define rOFDM0_TxCoeff3 0xcac 638 #define rOFDM0_TxCoeff4 0xcb0 639 #define rOFDM0_TxCoeff5 0xcb4 640 #define rOFDM0_TxCoeff6 0xcb8 641 #define rOFDM0_RxHPParameter 0xce0 642 #define rOFDM0_TxPseudoNoiseWgt 0xce4 643 #define rOFDM0_FrameSync 0xcf0 644 #define rOFDM0_DFSReport 0xcf4 645 646 /* 647 * 7. PageD(0xD00) 648 * */ 649 #define rOFDM1_LSTF 0xd00 650 #define rOFDM1_TRxPathEnable 0xd04 651 652 /* 653 * 8. PageE(0xE00) 654 * */ 655 #define rTxAGC_A_Rate18_06 0xe00 656 #define rTxAGC_A_Rate54_24 0xe04 657 #define rTxAGC_A_CCK1_Mcs32 0xe08 658 #define rTxAGC_A_Mcs03_Mcs00 0xe10 659 #define rTxAGC_A_Mcs07_Mcs04 0xe14 660 #define rTxAGC_A_Mcs11_Mcs08 0xe18 661 #define rTxAGC_A_Mcs15_Mcs12 0xe1c 662 663 #define rTxAGC_B_Rate18_06 0x830 664 #define rTxAGC_B_Rate54_24 0x834 665 #define rTxAGC_B_CCK1_55_Mcs32 0x838 666 #define rTxAGC_B_Mcs03_Mcs00 0x83c 667 #define rTxAGC_B_Mcs07_Mcs04 0x848 668 #define rTxAGC_B_Mcs11_Mcs08 0x84c 669 #define rTxAGC_B_Mcs15_Mcs12 0x868 670 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c 671 672 #define rFPGA0_IQK 0xe28 673 #define rTx_IQK_Tone_A 0xe30 674 #define rRx_IQK_Tone_A 0xe34 675 #define rTx_IQK_PI_A 0xe38 676 #define rRx_IQK_PI_A 0xe3c 677 678 #define rTx_IQK 0xe40 679 #define rRx_IQK 0xe44 680 #define rIQK_AGC_Pts 0xe48 681 #define rIQK_AGC_Rsp 0xe4c 682 #define rTx_IQK_Tone_B 0xe50 683 #define rRx_IQK_Tone_B 0xe54 684 #define rTx_IQK_PI_B 0xe58 685 #define rRx_IQK_PI_B 0xe5c 686 #define rIQK_AGC_Cont 0xe60 687 688 #define rBlue_Tooth 0xe6c 689 #define rRx_Wait_CCA 0xe70 690 #define rTx_CCK_RFON 0xe74 691 #define rTx_CCK_BBON 0xe78 692 #define rTx_OFDM_RFON 0xe7c 693 #define rTx_OFDM_BBON 0xe80 694 #define rTx_To_Rx 0xe84 695 #define rTx_To_Tx 0xe88 696 #define rRx_CCK 0xe8c 697 698 #define rTx_Power_Before_IQK_A 0xe94 699 #define rTx_Power_After_IQK_A 0xe9c 700 701 #define rRx_Power_Before_IQK_A 0xea0 702 #define rRx_Power_Before_IQK_A_2 0xea4 703 #define rRx_Power_After_IQK_A 0xea8 704 #define rRx_Power_After_IQK_A_2 0xeac 705 706 #define rTx_Power_Before_IQK_B 0xeb4 707 #define rTx_Power_After_IQK_B 0xebc 708 709 #define rRx_Power_Before_IQK_B 0xec0 710 #define rRx_Power_Before_IQK_B_2 0xec4 711 #define rRx_Power_After_IQK_B 0xec8 712 #define rRx_Power_After_IQK_B_2 0xecc 713 714 #define rRx_OFDM 0xed0 715 #define rRx_Wait_RIFS 0xed4 716 #define rRx_TO_Rx 0xed8 717 #define rStandby 0xedc 718 #define rSleep 0xee0 719 #define rPMPD_ANAEN 0xeec 720 721 722 /* 2. Page8(0x800) */ 723 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 724 #define bJapanMode 0x2 725 #define bCCKTxSC 0x30 726 #define bCCKEn 0x1000000 727 #define bOFDMEn 0x2000000 728 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 729 #define bXCTxAGC 0xf000 730 #define bXDTxAGC 0xf0000 731 732 /* 4. PageA(0xA00) */ 733 #define bCCKBBMode 0x3 /* Useless */ 734 #define bCCKTxPowerSaving 0x80 735 #define bCCKRxPowerSaving 0x40 736 737 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ 738 739 #define bCCKScramble 0x8 /* Useless */ 740 #define bCCKAntDiversity 0x8000 741 #define bCCKCarrierRecovery 0x4000 742 #define bCCKTxRate 0x3000 743 #define bCCKDCCancel 0x0800 744 #define bCCKISICancel 0x0400 745 #define bCCKMatchFilter 0x0200 746 #define bCCKEqualizer 0x0100 747 #define bCCKPreambleDetect 0x800000 748 #define bCCKFastFalseCCA 0x400000 749 #define bCCKChEstStart 0x300000 750 #define bCCKCCACount 0x080000 751 #define bCCKcs_lim 0x070000 752 #define bCCKBistMode 0x80000000 753 #define bCCKCCAMask 0x40000000 754 #define bCCKTxDACPhase 0x4 755 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 756 #define bCCKr_cp_mode0 0x0100 757 #define bCCKTxDCOffset 0xf0 758 #define bCCKRxDCOffset 0xf 759 #define bCCKCCAMode 0xc000 760 #define bCCKFalseCS_lim 0x3f00 761 #define bCCKCS_ratio 0xc00000 762 #define bCCKCorgBit_sel 0x300000 763 #define bCCKPD_lim 0x0f0000 764 #define bCCKNewCCA 0x80000000 765 #define bCCKRxHPofIG 0x8000 766 #define bCCKRxIG 0x7f00 767 #define bCCKLNAPolarity 0x800000 768 #define bCCKRx1stGain 0x7f0000 769 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 770 #define bCCKRxAGCSatLevel 0x1f000000 771 #define bCCKRxAGCSatCount 0xe0 772 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 773 #define bCCKFixedRxAGC 0x8000 774 /* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ 775 #define bCCKAntennaPolarity 0x2000 776 #define bCCKTxFilterType 0x0c00 777 #define bCCKRxAGCReportType 0x0300 778 #define bCCKRxDAGCEn 0x80000000 779 #define bCCKRxDAGCPeriod 0x20000000 780 #define bCCKRxDAGCSatLevel 0x1f000000 781 #define bCCKTimingRecovery 0x800000 782 #define bCCKTxC0 0x3f0000 783 #define bCCKTxC1 0x3f000000 784 #define bCCKTxC2 0x3f 785 #define bCCKTxC3 0x3f00 786 #define bCCKTxC4 0x3f0000 787 #define bCCKTxC5 0x3f000000 788 #define bCCKTxC6 0x3f 789 #define bCCKTxC7 0x3f00 790 #define bCCKDebugPort 0xff0000 791 #define bCCKDACDebug 0x0f000000 792 #define bCCKFalseAlarmEnable 0x8000 793 #define bCCKFalseAlarmRead 0x4000 794 #define bCCKTRSSI 0x7f 795 #define bCCKRxAGCReport 0xfe 796 #define bCCKRxReport_AntSel 0x80000000 797 #define bCCKRxReport_MFOff 0x40000000 798 #define bCCKRxRxReport_SQLoss 0x20000000 799 #define bCCKRxReport_Pktloss 0x10000000 800 #define bCCKRxReport_Lockedbit 0x08000000 801 #define bCCKRxReport_RateError 0x04000000 802 #define bCCKRxReport_RxRate 0x03000000 803 #define bCCKRxFACounterLower 0xff 804 #define bCCKRxFACounterUpper 0xff000000 805 #define bCCKRxHPAGCStart 0xe000 806 #define bCCKRxHPAGCFinal 0x1c00 807 #define bCCKRxFalseAlarmEnable 0x8000 808 #define bCCKFACounterFreeze 0x4000 809 #define bCCKTxPathSel 0x10000000 810 #define bCCKDefaultRxPath 0xc000000 811 #define bCCKOptionRxPath 0x3000000 812 813 #define RF_T_METER_88E 0x42 814 815 /* 6. PageE(0xE00) */ 816 #define bSTBCEn 0x4 /* Useless */ 817 #define bAntennaMapping 0x10 818 #define bNss 0x20 819 #define bCFOAntSumD 0x200 820 #define bPHYCounterReset 0x8000000 821 #define bCFOReportGet 0x4000000 822 #define bOFDMContinueTx 0x10000000 823 #define bOFDMSingleCarrier 0x20000000 824 #define bOFDMSingleTone 0x40000000 825 826 827 /* 828 * Other Definition 829 * */ 830 831 #define bEnable 0x1 /* Useless */ 832 #define bDisable 0x0 833 834 /* byte endable for srwrite */ 835 #define bByte0 0x1 /* Useless */ 836 #define bByte1 0x2 837 #define bByte2 0x4 838 #define bByte3 0x8 839 #define bWord0 0x3 840 #define bWord1 0xc 841 #define bDWord 0xf 842 843 /* for PutRegsetting & GetRegSetting BitMask */ 844 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 845 #define bMaskByte1 0xff00 846 #define bMaskByte2 0xff0000 847 #define bMaskByte3 0xff000000 848 #define bMaskHWord 0xffff0000 849 #define bMaskLWord 0x0000ffff 850 #define bMaskDWord 0xffffffff 851 #define bMaskH3Bytes 0xffffff00 852 #define bMask12Bits 0xfff 853 #define bMaskH4Bits 0xf0000000 854 #define bMaskOFDM_D 0xffc00000 855 #define bMaskCCK 0x3f3f3f3f 856 #define bMask7bits 0x7f 857 #define bMaskByte2HighNibble 0x00f00000 858 #define bMaskByte3LowNibble 0x0f000000 859 #define bMaskL3Bytes 0x00ffffff 860 861 /*--------------------------Define Parameters-------------------------------*/ 862 863 864 #endif 865