1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2017 Realtek Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 *****************************************************************************/ 16 #ifndef __INC_HAL8188EPHYCFG_H__ 17 #define __INC_HAL8188EPHYCFG_H__ 18 19 20 /*--------------------------Define Parameters-------------------------------*/ 21 #define LOOP_LIMIT 5 22 #define MAX_STALL_TIME 50 /* us */ 23 #define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */ 24 #define MAX_TXPWR_IDX_NMODE_92S 63 25 #define Reset_Cnt_Limit 3 26 27 #ifdef CONFIG_PCI_HCI 28 #define MAX_AGGR_NUM 0x0B 29 #else 30 #define MAX_AGGR_NUM 0x07 31 #endif /* CONFIG_PCI_HCI */ 32 33 34 /*--------------------------Define Parameters-------------------------------*/ 35 36 37 /*------------------------------Define structure----------------------------*/ 38 39 #define MAX_TX_COUNT_8188E 1 40 41 /* BB/RF related */ 42 43 44 /*------------------------------Define structure----------------------------*/ 45 46 47 /*------------------------Export global variable----------------------------*/ 48 /*------------------------Export global variable----------------------------*/ 49 50 51 /*------------------------Export Marco Definition---------------------------*/ 52 /*------------------------Export Marco Definition---------------------------*/ 53 54 55 /*--------------------------Exported Function prototype---------------------*/ 56 /* 57 * BB and RF register read/write 58 * */ 59 u32 PHY_QueryBBReg8188E(PADAPTER Adapter, 60 u32 RegAddr, 61 u32 BitMask); 62 void PHY_SetBBReg8188E(PADAPTER Adapter, 63 u32 RegAddr, 64 u32 BitMask, 65 u32 Data); 66 u32 PHY_QueryRFReg8188E(PADAPTER Adapter, 67 enum rf_path eRFPath, 68 u32 RegAddr, 69 u32 BitMask); 70 void PHY_SetRFReg8188E(PADAPTER Adapter, 71 enum rf_path eRFPath, 72 u32 RegAddr, 73 u32 BitMask, 74 u32 Data); 75 76 /* 77 * Initialization related function 78 */ 79 /* MAC/BB/RF HAL config */ 80 int PHY_MACConfig8188E(PADAPTER Adapter); 81 int PHY_BBConfig8188E(PADAPTER Adapter); 82 int PHY_RFConfig8188E(PADAPTER Adapter); 83 84 /* RF config */ 85 int rtl8188e_PHY_ConfigRFWithParaFile( PADAPTER Adapter, u8 *pFileName, enum rf_path eRFPath); 86 87 /* 88 * RF Power setting 89 */ 90 /* extern BOOLEAN PHY_SetRFPowerState(PADAPTER Adapter, 91 * RT_RF_POWER_STATE eRFPowerState); */ 92 93 /* 94 * BB TX Power R/W 95 * */ 96 void PHY_SetTxPowerLevel8188E(PADAPTER Adapter, 97 u8 channel); 98 99 void 100 PHY_SetTxPowerIndex_8188E( 101 PADAPTER Adapter, 102 u32 PowerIndex, 103 enum rf_path RFPath, 104 u8 Rate 105 ); 106 107 s8 phy_get_txpwr_target_extra_bias_8188e(_adapter *adapter, enum rf_path rfpath 108 , RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch); 109 110 /* 111 * Switch bandwidth for 8192S 112 */ 113 /* extern void PHY_SetBWModeCallback8192C(PRT_TIMER pTimer ); */ 114 void PHY_SetBWMode8188E(PADAPTER pAdapter, 115 enum channel_width ChnlWidth, 116 unsigned char Offset); 117 118 /* 119 * Set FW CMD IO for 8192S. 120 */ 121 /* extern BOOLEAN HalSetIO8192C(PADAPTER Adapter, 122 * IO_TYPE IOType); */ 123 124 /* 125 * Set A2 entry to fw for 8192S 126 * */ 127 extern void FillA2Entry8192C(PADAPTER Adapter, 128 u8 index, 129 u8 *val); 130 131 132 /* 133 * channel switch related funciton 134 */ 135 /* extern void PHY_SwChnlCallback8192C(PRT_TIMER pTimer ); */ 136 void PHY_SwChnl8188E(PADAPTER pAdapter, 137 u8 channel); 138 139 void 140 PHY_SetSwChnlBWMode8188E( 141 PADAPTER Adapter, 142 u8 channel, 143 enum channel_width Bandwidth, 144 u8 Offset40, 145 u8 Offset80 146 ); 147 148 void 149 PHY_SetRFEReg_8188E( 150 PADAPTER Adapter 151 ); 152 /* 153 * BB/MAC/RF other monitor API 154 * */ 155 void phy_set_rf_path_switch_8188e(struct dm_struct *phydm, bool bMain); 156 157 extern void 158 PHY_SwitchEphyParameter( 159 PADAPTER Adapter 160 ); 161 162 extern void 163 PHY_EnableHostClkReq( 164 PADAPTER Adapter 165 ); 166 167 BOOLEAN 168 SetAntennaConfig92C( 169 PADAPTER Adapter, 170 u8 DefaultAnt 171 ); 172 173 /*--------------------------Exported Function prototype---------------------*/ 174 175 /* 176 * Initialization related function 177 * 178 * MAC/BB/RF HAL config */ 179 /* extern s32 PHY_MACConfig8723(PADAPTER padapter); 180 * s32 PHY_BBConfig8723(PADAPTER padapter); 181 * s32 PHY_RFConfig8723(PADAPTER padapter); */ 182 183 184 185 /* ****************************************************************** 186 * Note: If SIC_ENABLE under PCIE, because of the slow operation 187 * you should 188 * 2) "#define RTL8723_FPGA_VERIFICATION 1" in Precomp.h.WlanE.Windows 189 * 3) "#define RTL8190_Download_Firmware_From_Header 0" in Precomp.h.WlanE.Windows if needed. 190 * */ 191 #if (RTL8188E_SUPPORT == 1) && (RTL8188E_FPGA_TRUE_PHY_VERIFICATION == 1) 192 #define SIC_ENABLE 1 193 #define SIC_HW_SUPPORT 1 194 #else 195 #define SIC_ENABLE 0 196 #define SIC_HW_SUPPORT 0 197 #endif 198 /* ****************************************************************** */ 199 200 201 #define SIC_MAX_POLL_CNT 5 202 203 #if (SIC_HW_SUPPORT == 1) 204 #define SIC_CMD_READY 0 205 #define SIC_CMD_PREWRITE 0x1 206 #if (RTL8188E_SUPPORT == 1) 207 #define SIC_CMD_WRITE 0x40 208 #define SIC_CMD_PREREAD 0x2 209 #define SIC_CMD_READ 0x80 210 #define SIC_CMD_INIT 0xf0 211 #define SIC_INIT_VAL 0xff 212 213 #define SIC_INIT_REG 0x1b7 214 #define SIC_CMD_REG 0x1EB /* 1byte */ 215 #define SIC_ADDR_REG 0x1E8 /* 1b4~1b5, 2 bytes */ 216 #define SIC_DATA_REG 0x1EC /* 1b0~1b3 */ 217 #else 218 #define SIC_CMD_WRITE 0x11 219 #define SIC_CMD_PREREAD 0x2 220 #define SIC_CMD_READ 0x12 221 #define SIC_CMD_INIT 0x1f 222 #define SIC_INIT_VAL 0xff 223 224 #define SIC_INIT_REG 0x1b7 225 #define SIC_CMD_REG 0x1b6 /* 1byte */ 226 #define SIC_ADDR_REG 0x1b4 /* 1b4~1b5, 2 bytes */ 227 #define SIC_DATA_REG 0x1b0 /* 1b0~1b3 */ 228 #endif 229 #else 230 #define SIC_CMD_READY 0 231 #define SIC_CMD_WRITE 1 232 #define SIC_CMD_READ 2 233 234 #if (RTL8188E_SUPPORT == 1) 235 #define SIC_CMD_REG 0x1EB /* 1byte */ 236 #define SIC_ADDR_REG 0x1E8 /* 1b9~1ba, 2 bytes */ 237 #define SIC_DATA_REG 0x1EC /* 1bc~1bf */ 238 #else 239 #define SIC_CMD_REG 0x1b8 /* 1byte */ 240 #define SIC_ADDR_REG 0x1b9 /* 1b9~1ba, 2 bytes */ 241 #define SIC_DATA_REG 0x1bc /* 1bc~1bf */ 242 #endif 243 #endif 244 245 #if (SIC_ENABLE == 1) 246 void SIC_Init( PADAPTER Adapter); 247 #endif 248 249 250 #endif /* __INC_HAL8192CPHYCFG_H */ 251