1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2017 Realtek Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 *****************************************************************************/
16 #define _HAL_MP_C_
17
18 #include <drv_types.h>
19
20 #ifdef CONFIG_MP_INCLUDED
21
22 #ifdef RTW_HALMAC
23 #include <hal_data.h> /* struct HAL_DATA_TYPE, RF register definition and etc. */
24 #else /* !RTW_HALMAC */
25 #ifdef CONFIG_RTL8188E
26 #include <rtl8188e_hal.h>
27 #endif
28 #ifdef CONFIG_RTL8723B
29 #include <rtl8723b_hal.h>
30 #endif
31 #ifdef CONFIG_RTL8192E
32 #include <rtl8192e_hal.h>
33 #endif
34 #ifdef CONFIG_RTL8814A
35 #include <rtl8814a_hal.h>
36 #endif
37 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
38 #include <rtl8812a_hal.h>
39 #endif
40 #ifdef CONFIG_RTL8703B
41 #include <rtl8703b_hal.h>
42 #endif
43 #ifdef CONFIG_RTL8723D
44 #include <rtl8723d_hal.h>
45 #endif
46 #ifdef CONFIG_RTL8710B
47 #include <rtl8710b_hal.h>
48 #endif
49 #ifdef CONFIG_RTL8188F
50 #include <rtl8188f_hal.h>
51 #endif
52 #ifdef CONFIG_RTL8188GTV
53 #include <rtl8188gtv_hal.h>
54 #endif
55 #ifdef CONFIG_RTL8192F
56 #include <rtl8192f_hal.h>
57 #endif
58 #endif /* !RTW_HALMAC */
59
60
MgntQuery_NssTxRate(u16 Rate)61 u8 MgntQuery_NssTxRate(u16 Rate)
62 {
63 u8 NssNum = RF_TX_NUM_NONIMPLEMENT;
64
65 if ((Rate >= MGN_MCS8 && Rate <= MGN_MCS15) ||
66 (Rate >= MGN_VHT2SS_MCS0 && Rate <= MGN_VHT2SS_MCS9))
67 NssNum = RF_2TX;
68 else if ((Rate >= MGN_MCS16 && Rate <= MGN_MCS23) ||
69 (Rate >= MGN_VHT3SS_MCS0 && Rate <= MGN_VHT3SS_MCS9))
70 NssNum = RF_3TX;
71 else if ((Rate >= MGN_MCS24 && Rate <= MGN_MCS31) ||
72 (Rate >= MGN_VHT4SS_MCS0 && Rate <= MGN_VHT4SS_MCS9))
73 NssNum = RF_4TX;
74 else
75 NssNum = RF_1TX;
76
77 return NssNum;
78 }
79
hal_mpt_SwitchRfSetting(PADAPTER pAdapter)80 void hal_mpt_SwitchRfSetting(PADAPTER pAdapter)
81 {
82 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
83 u8 ChannelToSw = pMptCtx->MptChannelToSw;
84 u32 ulRateIdx = pMptCtx->mpt_rate_index;
85 u32 ulbandwidth = pMptCtx->MptBandWidth;
86
87 /* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/
88 if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) &&
89 (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) {
90 pMptCtx->backup0x52_RF_A = (u8)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
91 pMptCtx->backup0x52_RF_B = (u8)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
92
93 if ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) {
94 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB);
95 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB);
96 } else {
97 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD);
98 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xD);
99 }
100 } else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/
101 if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) {
102 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
103 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
104 } else {
105 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
106 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
107 }
108 } else if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
109 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A);
110 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B);
111 }
112 }
113
hal_mpt_SetPowerTracking(PADAPTER padapter,u8 enable)114 s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable)
115 {
116 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
117 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
118
119
120 if (!netif_running(padapter->pnetdev)) {
121 return _FAIL;
122 }
123
124 if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
125 return _FAIL;
126 }
127 if (enable)
128 pDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE;
129 else
130 pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
131
132 return _SUCCESS;
133 }
134
hal_mpt_GetPowerTracking(PADAPTER padapter,u8 * enable)135 void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable)
136 {
137 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
138 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
139
140
141 *enable = pDM_Odm->rf_calibrate_info.txpowertrack_control;
142 }
143
144
hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter,BOOLEAN bInCH14)145 void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
146 {
147 u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0;
148 u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12;
149 u8 i;
150 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
151 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
152 u8 u1Channel = pHalData->current_channel;
153 u32 ulRateIdx = pMptCtx->mpt_rate_index;
154 u8 DataRate = 0xFF;
155
156 /* Do not modify CCK TX filter parameters for 8822B*/
157 if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) ||
158 IS_HARDWARE_TYPE_8723D(Adapter) || IS_HARDWARE_TYPE_8192F(Adapter) || IS_HARDWARE_TYPE_8822C(Adapter))
159 return;
160
161 DataRate = mpt_to_mgnt_rate(ulRateIdx);
162
163 if (u1Channel == 14 && IS_CCK_RATE(DataRate))
164 pHalData->bCCKinCH14 = TRUE;
165 else
166 pHalData->bCCKinCH14 = FALSE;
167
168 if (IS_HARDWARE_TYPE_8703B(Adapter)) {
169 if ((u1Channel == 14) && IS_CCK_RATE(DataRate)) {
170 /* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */
171 phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0);
172 phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskLWord, 0);
173
174 } else {
175 /* Normal setting for 8703B, just recover to the default setting. */
176 /* This hardcore values reference from the parameter which BB team gave. */
177 for (i = 0 ; i < 2 ; ++i)
178 phy_set_bb_reg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);
179
180 }
181 } else if (IS_HARDWARE_TYPE_8723D(Adapter)) {
182 /* 2.4G CCK TX DFIR */
183 /* 2016.01.20 Suggest from RS BB mingzhi*/
184 if ((u1Channel == 14)) {
185 phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C);
186 phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000000);
187 phy_set_bb_reg(Adapter, 0xAAC, bMaskDWord, 0x00003667);
188 } else {
189 for (i = 0 ; i < 3 ; ++i) {
190 phy_set_bb_reg(Adapter,
191 pHalData->RegForRecover[i].offset,
192 bMaskDWord,
193 pHalData->RegForRecover[i].value);
194 }
195 }
196 } else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) {
197 /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
198 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
199 CCKSwingIndex = 20; /* default index */
200
201 if (!pHalData->bCCKinCH14) {
202 /* Readback the current bb cck swing value and compare with the table to */
203 /* get the current swing index */
204 for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
205 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13_88f[i][0]) &&
206 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13_88f[i][1])) {
207 CCKSwingIndex = i;
208 break;
209 }
210 }
211 write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][0]);
212 write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][1]);
213 write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][2]);
214 write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][3]);
215 write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][4]);
216 write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][5]);
217 write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][6]);
218 write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][7]);
219 write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][8]);
220 write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][9]);
221 write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][10]);
222 write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][11]);
223 write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][12]);
224 write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][13]);
225 write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][14]);
226 write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][15]);
227 RTW_INFO("%s , cck_swing_table_ch1_ch13_88f[%d]\n", __func__, CCKSwingIndex);
228 } else {
229 for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
230 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14_88f[i][0]) &&
231 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14_88f[i][1])) {
232 CCKSwingIndex = i;
233 break;
234 }
235 }
236 write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][0]);
237 write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][1]);
238 write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][2]);
239 write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][3]);
240 write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][4]);
241 write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][5]);
242 write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][6]);
243 write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][7]);
244 write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][8]);
245 write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][9]);
246 write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][10]);
247 write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][11]);
248 write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][12]);
249 write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][13]);
250 write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][14]);
251 write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][15]);
252 RTW_INFO("%s , cck_swing_table_ch14_88f[%d]\n", __func__, CCKSwingIndex);
253 }
254 } else {
255
256 /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
257 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
258
259 if (!pHalData->bCCKinCH14) {
260 /* Readback the current bb cck swing value and compare with the table to */
261 /* get the current swing index */
262 for (i = 0; i < CCK_TABLE_SIZE; i++) {
263 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13[i][0]) &&
264 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13[i][1])) {
265 CCKSwingIndex = i;
266 break;
267 }
268 }
269
270 /*Write 0xa22 0xa23*/
271 TempVal = cck_swing_table_ch1_ch13[CCKSwingIndex][0] +
272 (cck_swing_table_ch1_ch13[CCKSwingIndex][1] << 8);
273
274
275 /*Write 0xa24 ~ 0xa27*/
276 TempVal2 = 0;
277 TempVal2 = cck_swing_table_ch1_ch13[CCKSwingIndex][2] +
278 (cck_swing_table_ch1_ch13[CCKSwingIndex][3] << 8) +
279 (cck_swing_table_ch1_ch13[CCKSwingIndex][4] << 16) +
280 (cck_swing_table_ch1_ch13[CCKSwingIndex][5] << 24);
281
282 /*Write 0xa28 0xa29*/
283 TempVal3 = 0;
284 TempVal3 = cck_swing_table_ch1_ch13[CCKSwingIndex][6] +
285 (cck_swing_table_ch1_ch13[CCKSwingIndex][7] << 8);
286 } else {
287 for (i = 0; i < CCK_TABLE_SIZE; i++) {
288 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14[i][0]) &&
289 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14[i][1])) {
290 CCKSwingIndex = i;
291 break;
292 }
293 }
294
295 /*Write 0xa22 0xa23*/
296 TempVal = cck_swing_table_ch14[CCKSwingIndex][0] +
297 (cck_swing_table_ch14[CCKSwingIndex][1] << 8);
298
299 /*Write 0xa24 ~ 0xa27*/
300 TempVal2 = 0;
301 TempVal2 = cck_swing_table_ch14[CCKSwingIndex][2] +
302 (cck_swing_table_ch14[CCKSwingIndex][3] << 8) +
303 (cck_swing_table_ch14[CCKSwingIndex][4] << 16) +
304 (cck_swing_table_ch14[CCKSwingIndex][5] << 24);
305
306 /*Write 0xa28 0xa29*/
307 TempVal3 = 0;
308 TempVal3 = cck_swing_table_ch14[CCKSwingIndex][6] +
309 (cck_swing_table_ch14[CCKSwingIndex][7] << 8);
310 }
311
312 write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
313 write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
314 write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
315 }
316
317 }
318
hal_mpt_SetChannel(PADAPTER pAdapter)319 void hal_mpt_SetChannel(PADAPTER pAdapter)
320 {
321 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
322 struct mp_priv *pmp = &pAdapter->mppriv;
323 u8 channel = pmp->channel;
324 u8 bandwidth = pmp->bandwidth;
325
326 hal_mpt_SwitchRfSetting(pAdapter);
327
328 pHalData->bSwChnl = _TRUE;
329 pHalData->bSetChnlBW = _TRUE;
330
331 if (bandwidth == 2) {
332 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
333 } else if (bandwidth == 1) {
334 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
335 } else
336 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
337
338 hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
339 rtw_btcoex_wifionly_scan_notify(pAdapter);
340
341 }
342
343 /*
344 * Notice
345 * Switch bandwitdth may change center frequency(channel)
346 */
hal_mpt_SetBandwidth(PADAPTER pAdapter)347 void hal_mpt_SetBandwidth(PADAPTER pAdapter)
348 {
349 struct mp_priv *pmp = &pAdapter->mppriv;
350 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
351
352 u8 channel = pmp->channel;
353 u8 bandwidth = pmp->bandwidth;
354
355 pHalData->bSwChnl = _TRUE;
356 pHalData->bSetChnlBW = _TRUE;
357
358 if (bandwidth == 2) {
359 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
360 } else if (bandwidth == 1) {
361 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
362 } else
363 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
364
365 hal_mpt_SwitchRfSetting(pAdapter);
366 rtw_btcoex_wifionly_scan_notify(pAdapter);
367
368 }
369
mpt_SetTxPower_Old(PADAPTER pAdapter,MPT_TXPWR_DEF Rate,u8 * pTxPower)370 void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)
371 {
372 switch (Rate) {
373 case MPT_CCK: {
374 u32 TxAGC = 0, pwr = 0;
375
376 pwr = pTxPower[RF_PATH_A];
377 if (pwr < 0x3f) {
378 TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
379 phy_set_bb_reg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[RF_PATH_A]);
380 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC);
381 }
382 pwr = pTxPower[RF_PATH_B];
383 if (pwr < 0x3f) {
384 TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
385 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[RF_PATH_B]);
386 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC);
387 }
388 }
389 break;
390
391 case MPT_OFDM_AND_HT: {
392 u32 TxAGC = 0;
393 u8 pwr = 0;
394
395 pwr = pTxPower[0];
396 if (pwr < 0x3f) {
397 TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
398 RTW_INFO("HT Tx-rf(A) Power = 0x%x\n", TxAGC);
399 phy_set_bb_reg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
400 phy_set_bb_reg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
401 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
402 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
403 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
404 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
405 }
406 TxAGC = 0;
407 pwr = pTxPower[1];
408 if (pwr < 0x3f) {
409 TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
410 RTW_INFO("HT Tx-rf(B) Power = 0x%x\n", TxAGC);
411 phy_set_bb_reg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
412 phy_set_bb_reg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
413 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
414 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
415 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
416 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
417 }
418 }
419 break;
420
421 default:
422 break;
423 }
424 RTW_INFO("<===mpt_SetTxPower_Old()\n");
425 }
426
427 void
mpt_SetTxPower(PADAPTER pAdapter,MPT_TXPWR_DEF Rate,u8 * pTxPower)428 mpt_SetTxPower(
429 PADAPTER pAdapter,
430 MPT_TXPWR_DEF Rate,
431 u8 *pTxPower
432 )
433 {
434 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
435
436 u8 path = 0 , i = 0, MaxRate = MGN_6M;
437 u8 StartPath = RF_PATH_A, EndPath = RF_PATH_B;
438
439 if (IS_HARDWARE_TYPE_8814A(pAdapter) || IS_HARDWARE_TYPE_8814B(pAdapter))
440 EndPath = RF_PATH_D;
441 else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)
442 || IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter))
443 EndPath = RF_PATH_A;
444
445 switch (Rate) {
446 case MPT_CCK: {
447 u8 rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
448
449 for (path = StartPath; path <= EndPath; path++)
450 for (i = 0; i < sizeof(rate); ++i)
451 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
452 }
453 break;
454 case MPT_OFDM: {
455 u8 rate[] = {
456 MGN_6M, MGN_9M, MGN_12M, MGN_18M,
457 MGN_24M, MGN_36M, MGN_48M, MGN_54M,
458 };
459
460 for (path = StartPath; path <= EndPath; path++)
461 for (i = 0; i < sizeof(rate); ++i)
462 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
463 }
464 break;
465 case MPT_HT: {
466 u8 rate[] = {
467 MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4,
468 MGN_MCS5, MGN_MCS6, MGN_MCS7, MGN_MCS8, MGN_MCS9,
469 MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14,
470 MGN_MCS15, MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19,
471 MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23, MGN_MCS24,
472 MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29,
473 MGN_MCS30, MGN_MCS31,
474 };
475 if (pHalData->rf_type == RF_4T4R)
476 MaxRate = MGN_MCS31;
477 else if (pHalData->rf_type == RF_3T3R)
478 MaxRate = MGN_MCS23;
479 else if (pHalData->rf_type == RF_2T2R)
480 MaxRate = MGN_MCS15;
481 else
482 MaxRate = MGN_MCS7;
483 for (path = StartPath; path <= EndPath; path++) {
484 for (i = 0; i < sizeof(rate); ++i) {
485 if (rate[i] > MaxRate)
486 break;
487 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
488 }
489 }
490 }
491 break;
492 case MPT_VHT: {
493 u8 rate[] = {
494 MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
495 MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9,
496 MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
497 MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9,
498 MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
499 MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9,
500 MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4,
501 MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9,
502 };
503 if (pHalData->rf_type == RF_4T4R)
504 MaxRate = MGN_VHT4SS_MCS9;
505 else if (pHalData->rf_type == RF_3T3R)
506 MaxRate = MGN_VHT3SS_MCS9;
507 else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
508 MaxRate = MGN_VHT2SS_MCS9;
509 else
510 MaxRate = MGN_VHT1SS_MCS9;
511
512 for (path = StartPath; path <= EndPath; path++) {
513 for (i = 0; i < sizeof(rate); ++i) {
514 if (rate[i] > MaxRate)
515 break;
516 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
517 }
518 }
519 }
520 break;
521 default:
522 RTW_INFO("<===mpt_SetTxPower: Illegal channel!!\n");
523 break;
524 }
525 }
526
hal_mpt_SetTxPower(PADAPTER pAdapter)527 void hal_mpt_SetTxPower(PADAPTER pAdapter)
528 {
529 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
530 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
531 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
532
533 if (pHalData->rf_chip < RF_CHIP_MAX) {
534 if (IS_HARDWARE_TYPE_8188E(pAdapter) ||
535 IS_HARDWARE_TYPE_8723B(pAdapter) ||
536 IS_HARDWARE_TYPE_8192E(pAdapter) ||
537 IS_HARDWARE_TYPE_8703B(pAdapter) ||
538 IS_HARDWARE_TYPE_8188F(pAdapter) ||
539 IS_HARDWARE_TYPE_8188GTV(pAdapter)
540 ) {
541
542 RTW_INFO("===> MPT_ProSetTxPower: Old\n");
543
544 mpt_SetTxPower_Old(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
545 mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel);
546
547 } else {
548
549 mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
550 mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);
551 mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel);
552 if(IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
553 RTW_INFO("===> MPT_ProSetTxPower: Jaguar/Jaguar2\n");
554 mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel);
555 }
556 }
557
558 rtw_hal_set_txpwr_done(pAdapter);
559 } else
560 RTW_INFO("RFChipID < RF_CHIP_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);
561
562 odm_clear_txpowertracking_state(pDM_Odm);
563 }
564
hal_mpt_SetDataRate(PADAPTER pAdapter)565 void hal_mpt_SetDataRate(PADAPTER pAdapter)
566 {
567 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
568 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
569 u32 DataRate;
570
571 DataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
572
573 hal_mpt_SwitchRfSetting(pAdapter);
574
575 hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
576 #ifdef CONFIG_RTL8723B
577 if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
578 if (IS_CCK_RATE(DataRate)) {
579 if (pMptCtx->mpt_rf_path == RF_PATH_A)
580 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0x6);
581 else
582 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0x6);
583 } else {
584 if (pMptCtx->mpt_rf_path == RF_PATH_A)
585 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
586 else
587 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
588 }
589 }
590
591 if ((IS_HARDWARE_TYPE_8723BS(pAdapter) &&
592 ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) {
593 if (pMptCtx->mpt_rf_path == RF_PATH_A)
594 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
595 else
596 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
597 }
598 #endif
599 }
600
601 #define RF_PATH_AB 22
602
603 #ifdef CONFIG_RTL8814A
mpt_ToggleIG_8814A(PADAPTER pAdapter)604 void mpt_ToggleIG_8814A(PADAPTER pAdapter)
605 {
606 u8 Path;
607 u32 IGReg = rA_IGI_Jaguar, IGvalue = 0;
608
609 for (Path = 0; Path <= RF_PATH_D; Path++) {
610 switch (Path) {
611 case RF_PATH_B:
612 IGReg = rB_IGI_Jaguar;
613 break;
614 case RF_PATH_C:
615 IGReg = rC_IGI_Jaguar2;
616 break;
617 case RF_PATH_D:
618 IGReg = rD_IGI_Jaguar2;
619 break;
620 default:
621 IGReg = rA_IGI_Jaguar;
622 break;
623 }
624
625 IGvalue = phy_query_bb_reg(pAdapter, IGReg, bMaskByte0);
626 phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue + 2);
627 phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue);
628 }
629 }
630
mpt_SetRFPath_8814A(PADAPTER pAdapter)631 void mpt_SetRFPath_8814A(PADAPTER pAdapter)
632 {
633
634 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
635 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
636 R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
637 R_ANTENNA_SELECT_CCK *p_cck_txrx;
638 u8 ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
639 /*/PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo);*/
640 /*/PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pMgntInfo);*/
641
642 u32 ulAntennaTx = pHalData->antenna_tx_path;
643 u32 ulAntennaRx = pHalData->AntennaRxPath;
644 u8 NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
645
646 if (NssforRate == RF_3TX) {
647 RTW_INFO("===> SetAntenna 3T Rate ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
648
649 switch (ulAntennaTx) {
650 case ANTENNA_BCD:
651 pMptCtx->mpt_rf_path = RF_PATH_BCD;
652 /*pHalData->ValidTxPath = 0x0e;*/
653 phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e); /*/ 0x940[27:16]=12'b0010_0100_0111*/
654 break;
655
656 case ANTENNA_ABC:
657 default:
658 pMptCtx->mpt_rf_path = RF_PATH_ABC;
659 /*pHalData->ValidTxPath = 0x0d;*/
660 phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247); /*/ 0x940[27:16]=12'b0010_0100_0111*/
661 break;
662 }
663
664 } else { /*/if(NssforRate == RF_1TX)*/
665 RTW_INFO("===> SetAntenna for 1T/2T Rate, ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
666 switch (ulAntennaTx) {
667 case ANTENNA_BCD:
668 pMptCtx->mpt_rf_path = RF_PATH_BCD;
669 /*pHalData->ValidTxPath = 0x0e;*/
670 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x7);
671 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0xe);
672 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0xe);
673 break;
674
675 case ANTENNA_BC:
676 pMptCtx->mpt_rf_path = RF_PATH_BC;
677 /*pHalData->ValidTxPath = 0x06;*/
678 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x6);
679 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0x6);
680 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x6);
681 break;
682 case ANTENNA_B:
683 pMptCtx->mpt_rf_path = RF_PATH_B;
684 /*pHalData->ValidTxPath = 0x02;*/
685 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4); /*/ 0xa07[7:4] = 4'b0100*/
686 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002); /*/ 0x93C[31:20]=12'b0000_0000_0010*/
687 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2); /* 0x80C[7:4] = 4'b0010*/
688 break;
689
690 case ANTENNA_C:
691 pMptCtx->mpt_rf_path = RF_PATH_C;
692 /*pHalData->ValidTxPath = 0x04;*/
693 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2); /*/ 0xa07[7:4] = 4'b0010*/
694 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004); /*/ 0x93C[31:20]=12'b0000_0000_0100*/
695 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4); /*/ 0x80C[7:4] = 4'b0100*/
696 break;
697
698 case ANTENNA_D:
699 pMptCtx->mpt_rf_path = RF_PATH_D;
700 /*pHalData->ValidTxPath = 0x08;*/
701 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1); /*/ 0xa07[7:4] = 4'b0001*/
702 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008); /*/ 0x93C[31:20]=12'b0000_0000_1000*/
703 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8); /*/ 0x80C[7:4] = 4'b1000*/
704 break;
705
706 case ANTENNA_A:
707 default:
708 pMptCtx->mpt_rf_path = RF_PATH_A;
709 /*pHalData->ValidTxPath = 0x01;*/
710 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8); /*/ 0xa07[7:4] = 4'b1000*/
711 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001); /*/ 0x93C[31:20]=12'b0000_0000_0001*/
712 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1); /*/ 0x80C[7:4] = 4'b0001*/
713 break;
714 }
715 }
716
717 switch (ulAntennaRx) {
718 case ANTENNA_A:
719 /*pHalData->ValidRxPath = 0x01;*/
720 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
721 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
722 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
723 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
724 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
725 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0);
726 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
727 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
728 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
729 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
730 /*/ CCA related PD_delay_th*/
731 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
732 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
733 break;
734
735 case ANTENNA_B:
736 /*pHalData->ValidRxPath = 0x02;*/
737 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
738 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
739 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
740 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
741 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
742 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1);
743 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
744 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
745 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
746 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
747 /*/ CCA related PD_delay_th*/
748 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
749 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
750 break;
751
752 case ANTENNA_C:
753 /*pHalData->ValidRxPath = 0x04;*/
754 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
755 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
756 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44);
757 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
758 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
759 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2);
760 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
761 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
762 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
763 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
764 /*/ CCA related PD_delay_th*/
765 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
766 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
767 break;
768
769 case ANTENNA_D:
770 /*pHalData->ValidRxPath = 0x08;*/
771 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
772 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
773 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88);
774 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
775 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
776 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3);
777 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
778 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
779 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
780 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
781 /*/ CCA related PD_delay_th*/
782 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
783 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
784 break;
785
786 case ANTENNA_BC:
787 /*pHalData->ValidRxPath = 0x06;*/
788 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
789 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
790 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66);
791 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
792 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
793 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
794 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
795 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
796 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
797 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
798 /*/ CCA related PD_delay_th*/
799 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
800 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
801 break;
802
803 case ANTENNA_CD:
804 /*pHalData->ValidRxPath = 0x0C;*/
805 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
806 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
807 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc);
808 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
809 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
810 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB);
811 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
812 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
813 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
814 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
815 /*/ CCA related PD_delay_th*/
816 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
817 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
818 break;
819
820 case ANTENNA_BCD:
821 /*pHalData->ValidRxPath = 0x0e;*/
822 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
823 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
824 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee);
825 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
826 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
827 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
828 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
829 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
830 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
831 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/
832 /*/ CCA related PD_delay_th*/
833 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
834 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
835 break;
836
837 case ANTENNA_ABCD:
838 /*pHalData->ValidRxPath = 0x0f;*/
839 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
840 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
841 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff);
842 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
843 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
844 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1);
845 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
846 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
847 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
848 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
849 /*/ CCA related PD_delay_th*/
850 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
851 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
852 break;
853
854 default:
855 break;
856 }
857
858 PHY_Set_SecCCATH_by_RXANT_8814A(pAdapter, ulAntennaRx);
859
860 mpt_ToggleIG_8814A(pAdapter);
861 }
862
863 #endif /* CONFIG_RTL8814A */
864 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
865 void
mpt_SetSingleTone_8814A(PADAPTER pAdapter,BOOLEAN bSingleTone,BOOLEAN bEnPMacTx)866 mpt_SetSingleTone_8814A(
867 PADAPTER pAdapter,
868 BOOLEAN bSingleTone,
869 BOOLEAN bEnPMacTx)
870 {
871
872 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
873 u8 StartPath = RF_PATH_A, EndPath = RF_PATH_A, path;
874 static u32 regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0;
875
876 if (bSingleTone) {
877 regIG0 = phy_query_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord); /*/ 0xC1C[31:21]*/
878 regIG1 = phy_query_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord); /*/ 0xE1C[31:21]*/
879 regIG2 = phy_query_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord); /*/ 0x181C[31:21]*/
880 regIG3 = phy_query_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord); /*/ 0x1A1C[31:21]*/
881
882 switch (pMptCtx->mpt_rf_path) {
883 case RF_PATH_A:
884 case RF_PATH_B:
885 case RF_PATH_C:
886 case RF_PATH_D:
887 StartPath = pMptCtx->mpt_rf_path;
888 EndPath = pMptCtx->mpt_rf_path;
889 break;
890 case RF_PATH_AB:
891 EndPath = RF_PATH_B;
892 break;
893 case RF_PATH_BC:
894 StartPath = RF_PATH_B;
895 EndPath = RF_PATH_C;
896 break;
897 case RF_PATH_ABC:
898 EndPath = RF_PATH_C;
899 break;
900 case RF_PATH_BCD:
901 StartPath = RF_PATH_B;
902 EndPath = RF_PATH_D;
903 break;
904 case RF_PATH_ABCD:
905 EndPath = RF_PATH_D;
906 break;
907 }
908
909 if (bEnPMacTx == FALSE) {
910 hal_mpt_SetContinuousTx(pAdapter, _TRUE);
911 issue_nulldata(pAdapter, NULL, 1, 3, 500);
912 }
913
914 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/
915
916 for (path = StartPath; path <= EndPath; path++) {
917 phy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
918 phy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
919
920 phy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
921 }
922
923 phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/
924 phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/
925 phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/
926 phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/
927 } else {
928 switch (pMptCtx->mpt_rf_path) {
929 case RF_PATH_A:
930 case RF_PATH_B:
931 case RF_PATH_C:
932 case RF_PATH_D:
933 StartPath = pMptCtx->mpt_rf_path;
934 EndPath = pMptCtx->mpt_rf_path;
935 break;
936 case RF_PATH_AB:
937 EndPath = RF_PATH_B;
938 break;
939 case RF_PATH_BC:
940 StartPath = RF_PATH_B;
941 EndPath = RF_PATH_C;
942 break;
943 case RF_PATH_ABC:
944 EndPath = RF_PATH_C;
945 break;
946 case RF_PATH_BCD:
947 StartPath = RF_PATH_B;
948 EndPath = RF_PATH_D;
949 break;
950 case RF_PATH_ABCD:
951 EndPath = RF_PATH_D;
952 break;
953 }
954 for (path = StartPath; path <= EndPath; path++)
955 phy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x0); /* RF LO disabled */
956
957 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/
958
959 if (bEnPMacTx == FALSE) {
960 if(IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
961 #ifdef PHYDM_MP_SUPPORT
962 phydm_stop_ofdm_cont_tx(pAdapter);
963 pMptCtx->bCckContTx = FALSE;
964 pMptCtx->bOfdmContTx = FALSE;
965 #endif
966 } else
967 hal_mpt_SetContinuousTx(pAdapter, _FALSE);
968 }
969
970 phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/
971 phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/
972 phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/
973 phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/
974 }
975 }
976
977 #endif
978
979 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
mpt_SetRFPath_8812A(PADAPTER pAdapter)980 void mpt_SetRFPath_8812A(PADAPTER pAdapter)
981 {
982 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
983 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
984 struct mp_priv *pmp = &pAdapter->mppriv;
985 u8 channel = pmp->channel;
986 u8 bandwidth = pmp->bandwidth;
987 u8 eLNA_2g = pHalData->ExternalLNA_2G;
988 u32 ulAntennaTx, ulAntennaRx;
989 u32 reg0xC50 = 0;
990
991 ulAntennaTx = pHalData->antenna_tx_path;
992 ulAntennaRx = pHalData->AntennaRxPath;
993
994 switch (ulAntennaTx) {
995 case ANTENNA_A:
996 pMptCtx->mpt_rf_path = RF_PATH_A;
997 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
998 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
999 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
1000 break;
1001 case ANTENNA_B:
1002 pMptCtx->mpt_rf_path = RF_PATH_B;
1003 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222);
1004 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
1005 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1);
1006 break;
1007 case ANTENNA_AB:
1008 pMptCtx->mpt_rf_path = RF_PATH_AB;
1009 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333);
1010 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
1011 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
1012 break;
1013 default:
1014 pMptCtx->mpt_rf_path = RF_PATH_AB;
1015 RTW_INFO("Unknown Tx antenna.\n");
1016 break;
1017 }
1018
1019 switch (ulAntennaRx) {
1020 case ANTENNA_A:
1021 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
1022 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
1023 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
1024 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
1025
1026 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
1027 reg0xC50 = phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
1028 phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
1029 phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50);
1030
1031 /* set PWED_TH for BB Yn user guide R29 */
1032 if (IS_HARDWARE_TYPE_8812(pAdapter)) {
1033 if (channel <= 14) { /* 2.4G */
1034 if (bandwidth == CHANNEL_WIDTH_20
1035 && eLNA_2g == 0) {
1036 /* 0x830[3:1]=3'b010 */
1037 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
1038 } else
1039 /* 0x830[3:1]=3'b100 */
1040 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1041 } else
1042 /* 0x830[3:1]=3'b100 for 5G */
1043 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1044 }
1045 break;
1046 case ANTENNA_B:
1047 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
1048 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */
1049 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1);
1050 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
1051
1052 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
1053 reg0xC50 = phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
1054 phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
1055 phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50);
1056
1057 /* set PWED_TH for BB Yn user guide R29 */
1058 if (IS_HARDWARE_TYPE_8812(pAdapter)) {
1059 if (channel <= 14) {
1060 if (bandwidth == CHANNEL_WIDTH_20
1061 && eLNA_2g == 0) {
1062 /* 0x830[3:1]=3'b010 */
1063 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
1064 } else
1065 /* 0x830[3:1]=3'b100 */
1066 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1067 } else
1068 /* 0x830[3:1]=3'b100 for 5G */
1069 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1070 }
1071 break;
1072 case ANTENNA_AB:
1073 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33);
1074 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/
1075 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
1076 /* set PWED_TH for BB Yn user guide R29 */
1077 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1078 break;
1079 default:
1080 RTW_INFO("Unknown Rx antenna.\n");
1081 break;
1082 }
1083
1084 if (pHalData->rfe_type == 5 || pHalData->rfe_type == 1) {
1085 if (ulAntennaTx == ANTENNA_A || ulAntennaTx == ANTENNA_AB) {
1086 /* WiFi */
1087 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x2);
1088 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
1089 } else {
1090 /* BT */
1091 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x1);
1092 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
1093 }
1094 }
1095 }
1096 #endif
1097
1098 #ifdef CONFIG_RTL8723B
mpt_SetRFPath_8723B(PADAPTER pAdapter)1099 void mpt_SetRFPath_8723B(PADAPTER pAdapter)
1100 {
1101 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1102 u32 ulAntennaTx, ulAntennaRx;
1103 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1104 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1105 struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1106 u8 i;
1107
1108 ulAntennaTx = pHalData->antenna_tx_path;
1109 ulAntennaRx = pHalData->AntennaRxPath;
1110
1111 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1112 RTW_INFO("This RF chip ID is not supported\n");
1113 return;
1114 }
1115
1116 switch (pAdapter->mppriv.antenna_tx) {
1117 case ANTENNA_A: { /*/ Actually path S1 (Wi-Fi)*/
1118 pMptCtx->mpt_rf_path = RF_PATH_A;
1119 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1120 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1121
1122 for (i = 0; i < 3; ++i) {
1123 u32 offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
1124 u32 data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][1];
1125
1126 if (offset != 0) {
1127 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1128 RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1129 }
1130 }
1131 for (i = 0; i < 2; ++i) {
1132 u32 offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
1133 u32 data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][1];
1134
1135 if (offset != 0) {
1136 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1137 RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1138 }
1139 }
1140 }
1141 break;
1142 case ANTENNA_B: { /*/ Actually path S0 (BT)*/
1143 u32 offset;
1144 u32 data;
1145
1146 pMptCtx->mpt_rf_path = RF_PATH_B;
1147 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1148 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/
1149
1150 for (i = 0; i < 3; ++i) {
1151 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1152 offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
1153 data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][1];
1154 if (pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][0] != 0) {
1155 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1156 RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1157 }
1158 }
1159 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1160 for (i = 0; i < 2; ++i) {
1161 offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
1162 data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][1];
1163 if (pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][0] != 0) {
1164 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1165 RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1166 }
1167 }
1168 }
1169 break;
1170 default:
1171 pMptCtx->mpt_rf_path = RF_PATH_AB;
1172 break;
1173 }
1174 }
1175 #endif
1176
1177 #ifdef CONFIG_RTL8703B
mpt_SetRFPath_8703B(PADAPTER pAdapter)1178 void mpt_SetRFPath_8703B(PADAPTER pAdapter)
1179 {
1180 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1181 u32 ulAntennaTx, ulAntennaRx;
1182 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1183 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1184 struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1185 u8 i;
1186
1187 ulAntennaTx = pHalData->antenna_tx_path;
1188 ulAntennaRx = pHalData->AntennaRxPath;
1189
1190 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1191 RTW_INFO("This RF chip ID is not supported\n");
1192 return;
1193 }
1194
1195 switch (pAdapter->mppriv.antenna_tx) {
1196 case ANTENNA_A: { /* Actually path S1 (Wi-Fi) */
1197 pMptCtx->mpt_rf_path = RF_PATH_A;
1198 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1199 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1200
1201 for (i = 0; i < 3; ++i) {
1202 u32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
1203 u32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
1204
1205 if (offset != 0) {
1206 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1207 RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1208 }
1209
1210 }
1211 for (i = 0; i < 2; ++i) {
1212 u32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
1213 u32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
1214
1215 if (offset != 0) {
1216 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1217 RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1218 }
1219 }
1220 }
1221 break;
1222 case ANTENNA_B: { /* Actually path S0 (BT)*/
1223 pMptCtx->mpt_rf_path = RF_PATH_B;
1224 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1225 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */
1226
1227 for (i = 0; i < 3; ++i) {
1228 u32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
1229 u32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
1230
1231 if (pRFCalibrateInfo->tx_iqc_8703b[i][0] != 0) {
1232 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1233 RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1234 }
1235 }
1236 for (i = 0; i < 2; ++i) {
1237 u32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
1238 u32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
1239
1240 if (pRFCalibrateInfo->rx_iqc_8703b[i][0] != 0) {
1241 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1242 RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1243 }
1244 }
1245 }
1246 break;
1247 default:
1248 pMptCtx->mpt_rf_path = RF_PATH_AB;
1249 break;
1250 }
1251
1252 }
1253 #endif
1254
1255 #ifdef CONFIG_RTL8723D
mpt_SetRFPath_8723D(PADAPTER pAdapter)1256 void mpt_SetRFPath_8723D(PADAPTER pAdapter)
1257 {
1258 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1259 u8 p = 0, i = 0;
1260 u32 ulAntennaTx, ulAntennaRx, offset = 0, data = 0, val32 = 0;
1261 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1262 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1263 struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1264
1265 ulAntennaTx = pHalData->antenna_tx_path;
1266 ulAntennaRx = pHalData->AntennaRxPath;
1267
1268 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1269 RTW_INFO("This RF chip ID is not supported\n");
1270 return;
1271 }
1272
1273 switch (pAdapter->mppriv.antenna_tx) {
1274 /* Actually path S1 (Wi-Fi) */
1275 case ANTENNA_A: {
1276 pMptCtx->mpt_rf_path = RF_PATH_A;
1277 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0);
1278 }
1279 break;
1280 /* Actually path S0 (BT) */
1281 case ANTENNA_B: {
1282 pMptCtx->mpt_rf_path = RF_PATH_B;
1283 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0xA);
1284
1285 }
1286 break;
1287 default:
1288 pMptCtx->mpt_rf_path = RF_PATH_AB;
1289 break;
1290 }
1291 }
1292 #endif
1293
mpt_SetRFPath_819X(PADAPTER pAdapter)1294 void mpt_SetRFPath_819X(PADAPTER pAdapter)
1295 {
1296 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1297 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1298 u32 ulAntennaTx, ulAntennaRx;
1299 R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
1300 R_ANTENNA_SELECT_CCK *p_cck_txrx;
1301 u8 r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
1302 u8 chgTx = 0, chgRx = 0;
1303 u32 r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
1304
1305 ulAntennaTx = pHalData->antenna_tx_path;
1306 ulAntennaRx = pHalData->AntennaRxPath;
1307
1308 p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;
1309 p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;
1310
1311 p_ofdm_tx->r_ant_ht1 = 0x1;
1312 p_ofdm_tx->r_ant_ht2 = 0x2;/*Second TX RF path is A*/
1313 p_ofdm_tx->r_ant_non_ht = 0x3;/*/ 0x1+0x2=0x3 */
1314
1315 switch (ulAntennaTx) {
1316 case ANTENNA_A:
1317 p_ofdm_tx->r_tx_antenna = 0x1;
1318 r_ofdm_tx_en_val = 0x1;
1319 p_ofdm_tx->r_ant_l = 0x1;
1320 p_ofdm_tx->r_ant_ht_s1 = 0x1;
1321 p_ofdm_tx->r_ant_non_ht_s1 = 0x1;
1322 p_cck_txrx->r_ccktx_enable = 0x8;
1323 chgTx = 1;
1324 /*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
1325 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1326 {
1327 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1328 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
1329 r_ofdm_tx_en_val = 0x3;
1330 /*/ Power save*/
1331 /*/cosa r_ant_select_ofdm_val = 0x11111111;*/
1332 /*/ We need to close RFB by SW control*/
1333 if (pHalData->rf_type == RF_2T2R) {
1334 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1335 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
1336 phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
1337 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1338 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
1339 }
1340 }
1341 pMptCtx->mpt_rf_path = RF_PATH_A;
1342 break;
1343 case ANTENNA_B:
1344 p_ofdm_tx->r_tx_antenna = 0x2;
1345 r_ofdm_tx_en_val = 0x2;
1346 p_ofdm_tx->r_ant_l = 0x2;
1347 p_ofdm_tx->r_ant_ht_s1 = 0x2;
1348 p_ofdm_tx->r_ant_non_ht_s1 = 0x2;
1349 p_cck_txrx->r_ccktx_enable = 0x4;
1350 chgTx = 1;
1351 /*/ From SD3 Willis suggestion !!! Set RF A as standby*/
1352 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1353 {
1354 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
1355 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1356
1357 /*/ 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.*/
1358 /*/ 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control*/
1359 if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
1360 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
1361 phy_set_bb_reg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
1362 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1363 /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1364 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
1365 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1366 }
1367 }
1368 pMptCtx->mpt_rf_path = RF_PATH_B;
1369 break;
1370 case ANTENNA_AB:/*/ For 8192S*/
1371 p_ofdm_tx->r_tx_antenna = 0x3;
1372 r_ofdm_tx_en_val = 0x3;
1373 p_ofdm_tx->r_ant_l = 0x3;
1374 p_ofdm_tx->r_ant_ht_s1 = 0x3;
1375 p_ofdm_tx->r_ant_non_ht_s1 = 0x3;
1376 p_cck_txrx->r_ccktx_enable = 0xC;
1377 chgTx = 1;
1378 /*/ From SD3Willis suggestion !!! Set RF B as standby*/
1379 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1380 {
1381 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1382 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1383 /* Disable Power save*/
1384 /*cosa r_ant_select_ofdm_val = 0x3321333;*/
1385 /* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control*/
1386 if (pHalData->rf_type == RF_2T2R) {
1387 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1388
1389 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1390 /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1391 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1392 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1393 }
1394 }
1395 pMptCtx->mpt_rf_path = RF_PATH_AB;
1396 break;
1397 default:
1398 break;
1399 }
1400 #if 0
1401 /* r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */
1402 /* r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */
1403 /* r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D */
1404 #endif
1405 switch (ulAntennaRx) {
1406 case ANTENNA_A:
1407 r_rx_antenna_ofdm = 0x1; /* A*/
1408 p_cck_txrx->r_cckrx_enable = 0x0; /* default: A*/
1409 p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A*/
1410 chgRx = 1;
1411 break;
1412 case ANTENNA_B:
1413 r_rx_antenna_ofdm = 0x2; /*/ B*/
1414 p_cck_txrx->r_cckrx_enable = 0x1; /*/ default: B*/
1415 p_cck_txrx->r_cckrx_enable_2 = 0x1; /*/ option: B*/
1416 chgRx = 1;
1417 break;
1418 case ANTENNA_AB:/*/ For 8192S and 8192E/U...*/
1419 r_rx_antenna_ofdm = 0x3;/*/ AB*/
1420 p_cck_txrx->r_cckrx_enable = 0x0;/*/ default:A*/
1421 p_cck_txrx->r_cckrx_enable_2 = 0x1;/*/ option:B*/
1422 chgRx = 1;
1423 break;
1424 default:
1425 break;
1426 }
1427
1428
1429 if (chgTx && chgRx) {
1430 switch (pHalData->rf_chip) {
1431 case RF_8225:
1432 case RF_8256:
1433 case RF_6052:
1434 /*/r_ant_sel_cck_val = r_ant_select_cck_val;*/
1435 phy_set_bb_reg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); /*/OFDM Tx*/
1436 phy_set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); /*/OFDM Tx*/
1437 phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
1438 phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
1439 if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1440 phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
1441 phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
1442 }
1443 phy_set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/
1444 break;
1445
1446 default:
1447 RTW_INFO("Unsupported RFChipID for switching antenna.\n");
1448 break;
1449 }
1450 }
1451 } /* MPT_ProSetRFPath */
1452
1453 #ifdef CONFIG_RTL8192F
1454
mpt_set_rfpath_8192f(PADAPTER pAdapter)1455 void mpt_set_rfpath_8192f(PADAPTER pAdapter)
1456 {
1457 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1458 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1459
1460 u16 ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
1461 u8 NssforRate, odmNssforRate;
1462 u32 ulAntennaTx, ulAntennaRx;
1463 enum bb_path RxAntToPhyDm;
1464 enum bb_path TxAntToPhyDm;
1465
1466 ulAntennaTx = pHalData->antenna_tx_path;
1467 ulAntennaRx = pHalData->AntennaRxPath;
1468 NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
1469
1470 if (pHalData->rf_chip >= RF_TYPE_MAX)
1471 RTW_INFO("This RF chip ID is not supported\n");
1472
1473 switch (ulAntennaTx) {
1474 case ANTENNA_A:
1475 pMptCtx->mpt_rf_path = RF_PATH_A;
1476 TxAntToPhyDm = BB_PATH_A;
1477 break;
1478 case ANTENNA_B:
1479 pMptCtx->mpt_rf_path = RF_PATH_B;
1480 TxAntToPhyDm = BB_PATH_B;
1481 break;
1482 case ANTENNA_AB:
1483 pMptCtx->mpt_rf_path = RF_PATH_AB;
1484 TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1485 break;
1486 default:
1487 pMptCtx->mpt_rf_path = RF_PATH_AB;
1488 TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1489 break;
1490 }
1491
1492 switch (ulAntennaRx) {
1493 case ANTENNA_A:
1494 RxAntToPhyDm = BB_PATH_A;
1495 break;
1496 case ANTENNA_B:
1497 RxAntToPhyDm = BB_PATH_B;
1498 break;
1499 case ANTENNA_AB:
1500 RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1501 break;
1502 default:
1503 RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1504 break;
1505 }
1506
1507 phydm_api_trx_mode(GET_PDM_ODM(pAdapter), TxAntToPhyDm, RxAntToPhyDm, TxAntToPhyDm);
1508
1509 }
1510
1511 #endif
1512
hal_mpt_SetAntenna(PADAPTER pAdapter)1513 void hal_mpt_SetAntenna(PADAPTER pAdapter)
1514 {
1515 PHAL_DATA_TYPE hal;
1516 ANTENNA_PATH anttx;
1517 enum bb_path bb_tx = 0;
1518
1519
1520 hal = GET_HAL_DATA(pAdapter);
1521 anttx = hal->antenna_tx_path;
1522
1523 switch (anttx) {
1524 case ANTENNA_A:
1525 bb_tx = BB_PATH_A;
1526 break;
1527 case ANTENNA_B:
1528 bb_tx = BB_PATH_B;
1529 break;
1530 case ANTENNA_C:
1531 bb_tx = BB_PATH_C;
1532 break;
1533 case ANTENNA_D:
1534 bb_tx = BB_PATH_D;
1535 break;
1536 case ANTENNA_AB:
1537 bb_tx = BB_PATH_AB;
1538 break;
1539 case ANTENNA_AC:
1540 bb_tx = BB_PATH_AC;
1541 break;
1542 case ANTENNA_AD:
1543 bb_tx = BB_PATH_AD;
1544 break;
1545 case ANTENNA_BC:
1546 bb_tx = BB_PATH_BC;
1547 break;
1548 case ANTENNA_BD:
1549 bb_tx = BB_PATH_BD;
1550 break;
1551 case ANTENNA_CD:
1552 bb_tx = BB_PATH_CD;
1553 break;
1554 case ANTENNA_ABC:
1555 bb_tx = BB_PATH_ABC;
1556 break;
1557 case ANTENNA_BCD:
1558 bb_tx = BB_PATH_BCD;
1559 break;
1560 case ANTENNA_ABD:
1561 bb_tx = BB_PATH_ABD;
1562 break;
1563 case ANTENNA_ACD:
1564 bb_tx = BB_PATH_ACD;
1565 break;
1566 case ANTENNA_ABCD:
1567 bb_tx = BB_PATH_ABCD;
1568 break;
1569 default:
1570 bb_tx = BB_PATH_A;
1571 break;
1572 }
1573 tx_path_nss_set_full_tx(hal->txpath_nss, hal->txpath_num_nss, bb_tx);
1574 RTW_INFO("%s ,ant idx %d, tx path_num_nss = %d\n", __func__, anttx, hal->txpath_num_nss[0]);
1575
1576 #ifdef CONFIG_RTL8822C
1577 if (IS_HARDWARE_TYPE_8822C(pAdapter)) {
1578 rtl8822c_mp_config_rfpath(pAdapter);
1579 return;
1580 }
1581 #endif
1582 #ifdef CONFIG_RTL8814A
1583 if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
1584 mpt_SetRFPath_8814A(pAdapter);
1585 return;
1586 }
1587 #endif
1588 #ifdef CONFIG_RTL8822B
1589 if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
1590 rtl8822b_mp_config_rfpath(pAdapter);
1591 return;
1592 }
1593 #endif
1594 #ifdef CONFIG_RTL8821C
1595 if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
1596 rtl8821c_mp_config_rfpath(pAdapter);
1597 return;
1598 }
1599 #endif
1600 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1601 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {
1602 mpt_SetRFPath_8812A(pAdapter);
1603 return;
1604 }
1605 #endif
1606 #ifdef CONFIG_RTL8723B
1607 if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1608 mpt_SetRFPath_8723B(pAdapter);
1609 return;
1610 }
1611 #endif
1612
1613 #ifdef CONFIG_RTL8703B
1614 if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1615 mpt_SetRFPath_8703B(pAdapter);
1616 return;
1617 }
1618 #endif
1619
1620 #ifdef CONFIG_RTL8723D
1621 if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1622 mpt_SetRFPath_8723D(pAdapter);
1623 return;
1624 }
1625 #endif
1626
1627 #ifdef CONFIG_RTL8192F
1628 if (IS_HARDWARE_TYPE_8192F(pAdapter)) {
1629 mpt_set_rfpath_8192f(pAdapter);
1630 return;
1631 }
1632 #endif
1633
1634 #ifdef CONFIG_RTL8814B
1635 if (IS_HARDWARE_TYPE_8814B(pAdapter)) {
1636 rtl8814b_mp_config_rfpath(pAdapter);
1637 return;
1638 }
1639 #endif
1640
1641 /* else if (IS_HARDWARE_TYPE_8821B(pAdapter))
1642 mpt_SetRFPath_8821B(pAdapter);
1643 Prepare for 8822B
1644 else if (IS_HARDWARE_TYPE_8822B(Context))
1645 mpt_SetRFPath_8822B(Context);
1646 */
1647 mpt_SetRFPath_819X(pAdapter);
1648 RTW_INFO("mpt_SetRFPath_819X Do %s\n", __func__);
1649 }
1650
hal_mpt_SetThermalMeter(PADAPTER pAdapter,u8 target_ther)1651 s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
1652 {
1653 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1654
1655 if (!netif_running(pAdapter->pnetdev)) {
1656 return _FAIL;
1657 }
1658
1659
1660 if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
1661 return _FAIL;
1662 }
1663
1664 target_ther &= 0xff;
1665
1666 pHalData->eeprom_thermal_meter = target_ther;
1667
1668 return _SUCCESS;
1669 }
1670
1671
hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)1672 void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)
1673 {
1674 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
1675 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);
1676 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x0);
1677 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);
1678 } else
1679 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT17 | BIT16, 0x03);
1680
1681 }
1682
1683
hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter,u8 rf_path)1684 u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter, u8 rf_path)
1685
1686 {
1687 struct dm_struct *p_dm_odm = adapter_to_phydm(pAdapter);
1688
1689 u32 ThermalValue = 0;
1690 s32 thermal_value_temp = 0;
1691 s8 thermal_offset = 0;
1692 u32 thermal_reg_mask = 0;
1693
1694 if (IS_8822C_SERIES(GET_HAL_DATA(pAdapter)->version_id))
1695 thermal_reg_mask = 0x007e; /*0x42: RF Reg[6:1], 35332(themal K & bias k & power trim) & 35325(tssi )*/
1696 else
1697 thermal_reg_mask = 0xfc00; /*0x42: RF Reg[15:10]*/
1698
1699 ThermalValue = (u8)phy_query_rf_reg(pAdapter, rf_path, 0x42, thermal_reg_mask);
1700
1701 thermal_offset = phydm_get_thermal_offset(p_dm_odm);
1702
1703 thermal_value_temp = ThermalValue + thermal_offset;
1704
1705 if (thermal_value_temp > 63)
1706 ThermalValue = 63;
1707 else if (thermal_value_temp < 0)
1708 ThermalValue = 0;
1709 else
1710 ThermalValue = thermal_value_temp;
1711
1712 return (u8)ThermalValue;
1713 }
1714
1715
hal_mpt_GetThermalMeter(PADAPTER pAdapter,u8 rfpath,u8 * value)1716 void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 rfpath, u8 *value)
1717 {
1718 #if 0
1719 fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
1720 rtw_msleep_os(1000);
1721 fw_cmd_data(pAdapter, value, 1);
1722 *value &= 0xFF;
1723 #else
1724 hal_mpt_TriggerRFThermalMeter(pAdapter);
1725 rtw_msleep_os(1000);
1726 *value = hal_mpt_ReadRFThermalMeter(pAdapter, rfpath);
1727 #endif
1728
1729 }
1730
1731
hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter,u8 bStart)1732 void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
1733 {
1734 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1735
1736 pAdapter->mppriv.mpt_ctx.bSingleCarrier = bStart;
1737
1738 if (bStart) {/*/ Start Single Carrier.*/
1739 /*/ Start Single Carrier.*/
1740 /*/ 1. if OFDM block on?*/
1741 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
1742 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/
1743
1744 /*/ 2. set CCK test mode off, set to CCK normal mode*/
1745 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
1746
1747 /*/ 3. turn on scramble setting*/
1748 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
1749
1750 /*/ 4. Turn On Continue Tx and turn off the other test modes.*/
1751 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1752 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
1753 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_SingleCarrier);
1754 else
1755 #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1756 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleCarrier);
1757
1758 } else {
1759 /*/ Stop Single Carrier.*/
1760 /*/ Stop Single Carrier.*/
1761 /*/ Turn off all test modes.*/
1762 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1763 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
1764 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1765 else
1766 #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1767 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1768
1769 rtw_msleep_os(10);
1770 /*/BB Reset*/
1771 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1772 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1773 }
1774 }
1775
1776
hal_mpt_SetSingleToneTx(PADAPTER pAdapter,u8 bStart)1777 void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
1778 {
1779 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1780 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1781 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1782 u32 ulAntennaTx = pHalData->antenna_tx_path;
1783 static u32 regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0;
1784 u8 rfPath;
1785
1786 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
1787 #ifdef PHYDM_MP_SUPPORT
1788 #ifdef CONFIG_RTL8814B
1789 if(pHalData->current_channel_bw == CHANNEL_WIDTH_80_80)
1790 {
1791 /* @Tx mode: RF0x00[19:16]=4'b0010 */
1792 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x0, 0xF0000, 0x2);
1793 /* @Lowest RF gain index: RF_0x0[4:0] = 0*/
1794 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x0, 0x1F, 0x0);
1795 /* @RF LO enabled */
1796 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x58, BIT(1), 0x1);
1797 /* @SYN1 */
1798 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x0, 0xF0000, 0x2);
1799 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x0, 0x1F, 0x0);
1800 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x58, BIT(1), 0x1);
1801 }
1802 #endif
1803 phydm_mp_set_single_tone(pDM_Odm, bStart, pMptCtx->mpt_rf_path);
1804 #endif
1805 return;
1806 }
1807
1808 switch (ulAntennaTx) {
1809 case ANTENNA_B:
1810 rfPath = RF_PATH_B;
1811 break;
1812 case ANTENNA_C:
1813 rfPath = RF_PATH_C;
1814 break;
1815 case ANTENNA_D:
1816 rfPath = RF_PATH_D;
1817 break;
1818 case ANTENNA_A:
1819 default:
1820 rfPath = RF_PATH_A;
1821 break;
1822 }
1823
1824 pAdapter->mppriv.mpt_ctx.is_single_tone = bStart;
1825 if (bStart) {
1826 /*/ Start Single Tone.*/
1827 /*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/
1828 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1829 regRF = phy_query_rf_reg(pAdapter, rfPath, lna_low_gain_3, bRFRegOffsetMask);
1830 phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1831 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
1832 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
1833 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
1834 /*/Set MAC REG 88C: Prevent SingleTone Fail*/
1835 phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0xF);
1836 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO disabled*/
1837 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1838 } else if (IS_HARDWARE_TYPE_8192F(pAdapter)) { /* USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
1839 #ifdef CONFIG_RTL8192F
1840 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x1);
1841 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x1);
1842 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x1);
1843 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x1);
1844 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x1);
1845 phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x1);
1846 phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0xF);
1847 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x1); /* RF LO disabled*/
1848 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /* Tx mode*/
1849 #endif
1850 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1851 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1852 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1853 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/
1854 } else {
1855 /*/ S0/S1 both use PATH A to configure*/
1856 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1857 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/
1858 }
1859 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1860 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1861 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */
1862 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */
1863 }
1864 } else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
1865 /*Set BB REG 88C: Prevent SingleTone Fail*/
1866 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF);
1867 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1);
1868 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2);
1869
1870 } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1871 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1872 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1873 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
1874 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x1);
1875 } else {/* S0/S1 both use PATH A to configure */
1876 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1877 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
1878 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x1);
1879 }
1880 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
1881 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1882 u8 p = RF_PATH_A;
1883
1884 regRF = phy_query_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);
1885 regBB0 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);
1886 regBB1 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);
1887 regBB2 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1888 regBB3 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1889
1890 phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x0); /*/ Disable CCK and OFDM*/
1891
1892 if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
1893 for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
1894 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1895 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1896 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1897 }
1898 } else {
1899 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1900 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1901 #ifdef CONFIG_RTL8821C
1902 if (IS_HARDWARE_TYPE_8821C(pAdapter) && pDM_Odm->current_rf_set_8821c == SWITCH_TO_BTG)
1903 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x75, BIT16, 0x1); /* RF LO (for BTG) enabled */
1904 else
1905 #endif
1906 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1907 }
1908 if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
1909 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777); /* 0xCB0=0x77777777*/
1910 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777); /* 0xEB0=0x77777777*/
1911 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777); /* 0xCB4[15:0] = 0x7777*/
1912 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777); /* 0xEB4[15:0] = 0x7777*/
1913 phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xFFF, 0xb); /* 0xCBC[23:16] = 0x12*/
1914 phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xFFF, 0x830); /* 0xEBC[23:16] = 0x12*/
1915 } else if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
1916 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xF0F0, 0x707); /* 0xCB0[[15:12, 7:4] = 0x707*/
1917
1918 if (pHalData->external_pa_5g)
1919 {
1920 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
1921 }
1922 else if (pHalData->ExternalPA_2G)
1923 {
1924 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
1925 }
1926 } else {
1927 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1928 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1929
1930 if (pHalData->external_pa_5g) {
1931 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/
1932 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/
1933 } else if (pHalData->ExternalPA_2G) {
1934 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/
1935 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/
1936 }
1937 }
1938 #endif
1939 }
1940 #if defined(CONFIG_RTL8814A)
1941 else if (IS_HARDWARE_TYPE_8814A(pAdapter))
1942 mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE);
1943 #endif
1944 else /*/ Turn On SingleTone and turn off the other test modes.*/
1945 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone);
1946
1947 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1948 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1949
1950 } else {/*/ Stop Single Ton e.*/
1951
1952 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1953 phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, bRFRegOffsetMask, regRF);
1954 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
1955 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
1956 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1957 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/
1958 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0);/*/ RF LO disabled */
1959 /*/ RESTORE MAC REG 88C: Enable RF Functions*/
1960 phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0x0);
1961 } else if (IS_HARDWARE_TYPE_8192F(pAdapter)){
1962 #ifdef CONFIG_RTL8192F
1963 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x0);
1964 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x0);
1965 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x0);
1966 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x0);
1967 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x0);
1968 phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x0);
1969 phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0x0);
1970 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x0); /* RF LO disabled*/
1971 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /* Rx mode*/
1972 #endif
1973 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1974 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1975 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1976 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/
1977 } else {
1978 /*/ S0/S1 both use PATH A to configure*/
1979 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1980 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/
1981 }
1982 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1983 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1984 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */
1985 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */
1986 }
1987 } else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
1988 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /*Tx mode*/
1989 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0); /*RF LO disabled*/
1990 /*Set BB REG 88C: Prevent SingleTone Fail*/
1991 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc);
1992 } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1993 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1994 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
1995 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
1996 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x0);
1997 } else { /* S0/S1 both use PATH A to configure */
1998 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
1999 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
2000 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x0);
2001 }
2002 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
2003 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
2004 u8 p = RF_PATH_A;
2005
2006 phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x3); /*/ Disable CCK and OFDM*/
2007
2008 if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
2009 for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
2010 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
2011 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
2012 }
2013 } else {
2014 p = pMptCtx->mpt_rf_path;
2015 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
2016
2017 if (IS_HARDWARE_TYPE_8821C(pAdapter))
2018 phy_set_rf_reg(pAdapter, p, 0x75, BIT16, 0x0); /* RF LO (for BTG) disabled */
2019
2020 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
2021 }
2022
2023 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0);
2024 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1);
2025 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB2);
2026 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB3);
2027
2028 if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
2029 RTW_INFO("Restore RFE control Pin cbc\n");
2030 phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xfff, 0x0);
2031 phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xfff, 0x0);
2032 }
2033 #endif
2034 }
2035 #if defined(CONFIG_RTL8814A)
2036 else if (IS_HARDWARE_TYPE_8814A(pAdapter))
2037 mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE);
2038
2039 else/*/ Turn off all test modes.*/
2040 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
2041 #endif
2042 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2043 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2044
2045 }
2046 }
2047
hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter,u8 bStart)2048 void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
2049 {
2050 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2051 struct dm_struct *pdm_odm = &pHalData->odmpriv;
2052 u8 Rate;
2053
2054 pAdapter->mppriv.mpt_ctx.is_carrier_suppression = bStart;
2055
2056 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
2057 #ifdef PHYDM_MP_SUPPORT
2058 phydm_mp_set_carrier_supp(pdm_odm, bStart, pAdapter->mppriv.rateidx);
2059 #endif
2060 return;
2061 }
2062
2063 Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
2064 if (bStart) {/* Start Carrier Suppression.*/
2065 if (Rate <= MPT_RATE_11M) {
2066 /*/ 1. if CCK block on?*/
2067 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
2068 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
2069
2070 /*/Turn Off All Test Mode*/
2071 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
2072 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /* rSingleTone_ContTx_Jaguar*/
2073 else
2074 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2075
2076 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/
2077 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); /*/turn off scramble setting*/
2078
2079 /*/Set CCK Tx Test Rate*/
2080 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); /*/Set FTxRate to 1Mbps*/
2081 }
2082
2083 /*Set for dynamic set Power index*/
2084 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2085 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2086
2087 } else {/* Stop Carrier Suppression.*/
2088
2089 if (Rate <= MPT_RATE_11M) {
2090 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
2091 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
2092
2093 /*BB Reset*/
2094 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2095 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2096 }
2097 /*Stop for dynamic set Power index*/
2098 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2099 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2100 }
2101 RTW_INFO("\n MPT_ProSetCarrierSupp() is finished.\n");
2102 }
2103
hal_mpt_query_phytxok(PADAPTER pAdapter)2104 u32 hal_mpt_query_phytxok(PADAPTER pAdapter)
2105 {
2106 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2107 RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
2108 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2109 u16 count = 0;
2110
2111 #ifdef PHYDM_MP_SUPPORT
2112 struct dm_struct *dm = (struct dm_struct *)&pHalData->odmpriv;
2113 struct phydm_mp *mp = &dm->dm_mp_table;
2114
2115 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
2116 phydm_mp_get_tx_ok(&pHalData->odmpriv, pAdapter->mppriv.rateidx);
2117 count = mp->tx_phy_ok_cnt;
2118
2119 } else
2120 #endif
2121 {
2122
2123 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2124 count = phy_query_bb_reg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/
2125 else
2126 count = phy_query_bb_reg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/
2127 }
2128
2129 if (count > 50000) {
2130 rtw_reset_phy_trx_ok_counters(pAdapter);
2131 pAdapter->mppriv.tx.sended += count;
2132 count = 0;
2133 }
2134
2135 return pAdapter->mppriv.tx.sended + count;
2136
2137 }
2138
mpt_StopCckContTx(PADAPTER pAdapter)2139 static void mpt_StopCckContTx(
2140 PADAPTER pAdapter
2141 )
2142 {
2143 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2144 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2145 u8 u1bReg;
2146
2147 pMptCtx->bCckContTx = FALSE;
2148 pMptCtx->bOfdmContTx = FALSE;
2149
2150 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
2151 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
2152
2153 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2154 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 2b00*/
2155 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
2156
2157 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
2158 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 0);
2159 phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 0);
2160 }
2161
2162 /*BB Reset*/
2163 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2164 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2165
2166 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2167 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2168 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2169 }
2170
2171 if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) ||
2172 IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) ||
2173 IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) ||
2174 IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
2175 phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);/* patch Count CCK adjust Rate*/
2176 }
2177
2178 } /* mpt_StopCckContTx */
2179
2180
mpt_StopOfdmContTx(PADAPTER pAdapter)2181 static void mpt_StopOfdmContTx(
2182 PADAPTER pAdapter
2183 )
2184 {
2185 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2186 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2187 u8 u1bReg;
2188 u32 data;
2189
2190 pMptCtx->bCckContTx = FALSE;
2191 pMptCtx->bOfdmContTx = FALSE;
2192
2193 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
2194 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
2195 else
2196 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2197
2198 rtw_mdelay_os(10);
2199
2200 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)){
2201 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 0*/
2202 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
2203 }
2204
2205 /*BB Reset*/
2206 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2207 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2208
2209 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2210 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2211 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2212 }
2213 } /* mpt_StopOfdmContTx */
2214
2215
mpt_StartCckContTx(PADAPTER pAdapter)2216 static void mpt_StartCckContTx(
2217 PADAPTER pAdapter
2218 )
2219 {
2220 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2221 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2222 u32 cckrate;
2223
2224 /* 1. if CCK block on */
2225 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn))
2226 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/
2227
2228 /*Turn Off All Test Mode*/
2229 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
2230 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
2231 else
2232 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2233
2234 cckrate = pAdapter->mppriv.rateidx;
2235
2236 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
2237
2238 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*transmit mode*/
2239 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
2240
2241 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2242 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 11 force cck rxiq = 0*/
2243 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
2244 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
2245 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 1);
2246 phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 1);
2247 }
2248
2249 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2250 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2251 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2252 }
2253
2254 if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) ||
2255 IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) ||
2256 IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) ||
2257 IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
2258 if (pAdapter->mppriv.rateidx == MPT_RATE_1M) /* patch Count CCK adjust Rate*/
2259 phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);
2260 else
2261 phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bEnable);
2262 }
2263
2264 pMptCtx->bCckContTx = TRUE;
2265 pMptCtx->bOfdmContTx = FALSE;
2266
2267 } /* mpt_StartCckContTx */
2268
2269
mpt_StartOfdmContTx(PADAPTER pAdapter)2270 static void mpt_StartOfdmContTx(
2271 PADAPTER pAdapter
2272 )
2273 {
2274 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2275 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2276
2277 /* 1. if OFDM block on?*/
2278 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
2279 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/
2280
2281 /* 2. set CCK test mode off, set to CCK normal mode*/
2282 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
2283
2284 /* 3. turn on scramble setting*/
2285 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
2286
2287 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2288 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 2b'11*/
2289 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/
2290 }
2291
2292 /* 4. Turn On Continue Tx and turn off the other test modes.*/
2293 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
2294 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx);
2295 else
2296 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx);
2297
2298 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2299 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2300 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2301 }
2302
2303 pMptCtx->bCckContTx = FALSE;
2304 pMptCtx->bOfdmContTx = TRUE;
2305 } /* mpt_StartOfdmContTx */
2306
2307 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
2308 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
mpt_convert_phydm_txinfo_for_jaguar3(RT_PMAC_TX_INFO * pMacTxInfo,struct phydm_pmac_info * phydmtxinfo)2309 static void mpt_convert_phydm_txinfo_for_jaguar3(
2310 RT_PMAC_TX_INFO *pMacTxInfo, struct phydm_pmac_info *phydmtxinfo)
2311 {
2312 phydmtxinfo->en_pmac_tx = pMacTxInfo->bEnPMacTx;
2313 phydmtxinfo->mode = pMacTxInfo->Mode;
2314 phydmtxinfo->tx_rate = MRateToHwRate(mpt_to_mgnt_rate(pMacTxInfo->TX_RATE));
2315 phydmtxinfo->tx_sc = pMacTxInfo->TX_SC;
2316 phydmtxinfo->is_short_preamble = pMacTxInfo->bSPreamble;
2317 phydmtxinfo->ndp_sound = pMacTxInfo->NDP_sound;
2318 phydmtxinfo->bw = pMacTxInfo->BandWidth;
2319 phydmtxinfo->m_stbc = pMacTxInfo->m_STBC;
2320 phydmtxinfo->packet_period = pMacTxInfo->PacketPeriod;
2321 phydmtxinfo->packet_count = pMacTxInfo->PacketCount;
2322 phydmtxinfo->packet_pattern = pMacTxInfo->PacketPattern;
2323 phydmtxinfo->sfd = pMacTxInfo->SFD;
2324 phydmtxinfo->signal_field = pMacTxInfo->SignalField;
2325 phydmtxinfo->service_field = pMacTxInfo->ServiceField;
2326 phydmtxinfo->length = pMacTxInfo->LENGTH;
2327 _rtw_memcpy(&phydmtxinfo->crc16,pMacTxInfo->CRC16, 2);
2328 _rtw_memcpy(&phydmtxinfo->lsig , pMacTxInfo->LSIG,3);
2329 _rtw_memcpy(&phydmtxinfo->ht_sig , pMacTxInfo->HT_SIG,6);
2330 _rtw_memcpy(&phydmtxinfo->vht_sig_a , pMacTxInfo->VHT_SIG_A,6);
2331 _rtw_memcpy(&phydmtxinfo->vht_sig_b , pMacTxInfo->VHT_SIG_B,4);
2332 phydmtxinfo->vht_sig_b_crc = pMacTxInfo->VHT_SIG_B_CRC;
2333 _rtw_memcpy(&phydmtxinfo->vht_delimiter,pMacTxInfo->VHT_Delimiter,4);
2334 }
2335 #endif
2336
2337 /* for HW TX mode */
mpt_ProSetPMacTx(PADAPTER Adapter)2338 u8 mpt_ProSetPMacTx(PADAPTER Adapter)
2339 {
2340 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2341 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
2342 struct mp_priv *pmppriv = &Adapter->mppriv;
2343 struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
2344 RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
2345 struct dm_struct *p_dm_odm;
2346 u32 u4bTmp;
2347 u8 status = _TRUE;
2348
2349 p_dm_odm = &pHalData->odmpriv;
2350
2351 #if 0
2352 PRINT_DATA("LSIG ", PMacTxInfo.LSIG, 3);
2353 PRINT_DATA("HT_SIG", PMacTxInfo.HT_SIG, 6);
2354 PRINT_DATA("VHT_SIG_A", PMacTxInfo.VHT_SIG_A, 6);
2355 PRINT_DATA("VHT_SIG_B", PMacTxInfo.VHT_SIG_B, 4);
2356 dbg_print("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC);
2357 PRINT_DATA("VHT_Delimiter", PMacTxInfo.VHT_Delimiter, 4);
2358
2359 PRINT_DATA("Src Address", Adapter->mac_addr, ETH_ALEN);
2360 PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, ETH_ALEN);
2361 #endif
2362 if (pmppriv->pktInterval != 0)
2363 PMacTxInfo.PacketPeriod = pmppriv->pktInterval;
2364
2365 if (pmppriv->tx.count != 0)
2366 PMacTxInfo.PacketCount = pmppriv->tx.count;
2367
2368 RTW_INFO("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound);
2369 RTW_INFO("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount,
2370 PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern);
2371
2372 if (hal_spec->tx_nss_num < 2 && MPT_IS_2SS_RATE(PMacTxInfo.TX_RATE))
2373 return _FALSE;
2374 if (hal_spec->tx_nss_num < 3 && MPT_IS_3SS_RATE(PMacTxInfo.TX_RATE))
2375 return _FALSE;
2376 if (hal_spec->tx_nss_num < 4 && MPT_IS_4SS_RATE(PMacTxInfo.TX_RATE))
2377 return _FALSE;
2378 if (!is_supported_vht(Adapter->registrypriv.wireless_mode) && MPT_IS_VHT_RATE(PMacTxInfo.TX_RATE))
2379 return _FALSE;
2380 if (!is_supported_ht(Adapter->registrypriv.wireless_mode) && MPT_IS_HT_RATE(PMacTxInfo.TX_RATE))
2381 return _FALSE;
2382
2383 if (PMacTxInfo.BandWidth == 1 && hal_chk_bw_cap(Adapter, BW_CAP_40M))
2384 PMacTxInfo.BandWidth = CHANNEL_WIDTH_40;
2385 else if (PMacTxInfo.BandWidth == 2 && hal_chk_bw_cap(Adapter, BW_CAP_80M))
2386 PMacTxInfo.BandWidth = CHANNEL_WIDTH_80;
2387 else
2388 PMacTxInfo.BandWidth = CHANNEL_WIDTH_20;
2389
2390 if (IS_HARDWARE_TYPE_JAGUAR3(Adapter)) {
2391 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
2392 struct phydm_pmac_info phydm_mactxinfo;
2393
2394 if (PMacTxInfo.bEnPMacTx == TRUE) {
2395 pMptCtx->HWTxmode = PMacTxInfo.Mode;
2396 pMptCtx->mpt_rate_index = PMacTxInfo.TX_RATE;
2397 if (PMacTxInfo.Mode == CONTINUOUS_TX)
2398 hal_mpt_SetTxPower(Adapter);
2399 } else {
2400 PMacTxInfo.Mode = pMptCtx->HWTxmode;
2401 PMacTxInfo.TX_RATE = pMptCtx->mpt_rate_index;
2402 pMptCtx->HWTxmode = TEST_NONE;
2403 }
2404 mpt_convert_phydm_txinfo_for_jaguar3(&PMacTxInfo, &phydm_mactxinfo);
2405 phydm_set_pmac_tx(p_dm_odm, &phydm_mactxinfo, pMptCtx->mpt_rf_path);
2406 #endif
2407 return status;
2408 }
2409
2410 if (PMacTxInfo.bEnPMacTx == FALSE) {
2411 if (pMptCtx->HWTxmode == CONTINUOUS_TX) {
2412 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
2413 if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
2414 mpt_StopCckContTx(Adapter);
2415 else
2416 mpt_StopOfdmContTx(Adapter);
2417 } else if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index)) {
2418 u4bTmp = phy_query_bb_reg(Adapter, 0xf50, bMaskLWord);
2419 phy_set_bb_reg(Adapter, 0xb1c, bMaskLWord, u4bTmp + 50);
2420 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /*TX Stop*/
2421 } else
2422 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
2423
2424 if (pMptCtx->HWTxmode == OFDM_Single_Tone_TX) {
2425 /* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/
2426 if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
2427 mpt_StopCckContTx(Adapter);
2428 else
2429 mpt_StopOfdmContTx(Adapter);
2430
2431 mpt_SetSingleTone_8814A(Adapter, FALSE, TRUE);
2432 }
2433 pMptCtx->HWTxmode = TEST_NONE;
2434 return status;
2435 }
2436
2437 pMptCtx->mpt_rate_index = PMacTxInfo.TX_RATE;
2438
2439 if (PMacTxInfo.Mode == CONTINUOUS_TX) {
2440 pMptCtx->HWTxmode = CONTINUOUS_TX;
2441 PMacTxInfo.PacketCount = 1;
2442
2443 hal_mpt_SetTxPower(Adapter);
2444
2445 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2446 mpt_StartCckContTx(Adapter);
2447 else
2448 mpt_StartOfdmContTx(Adapter);
2449 } else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
2450 /* Continuous TX -> HW TX -> RF Setting */
2451 pMptCtx->HWTxmode = OFDM_Single_Tone_TX;
2452 PMacTxInfo.PacketCount = 1;
2453
2454 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2455 mpt_StartCckContTx(Adapter);
2456 else
2457 mpt_StartOfdmContTx(Adapter);
2458 } else if (PMacTxInfo.Mode == PACKETS_TX) {
2459 pMptCtx->HWTxmode = PACKETS_TX;
2460 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0)
2461 PMacTxInfo.PacketCount = 0xffff;
2462 }
2463
2464 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2465 /* 0xb1c[0:15] TX packet count 0xb1C[31:16] SFD*/
2466 u4bTmp = PMacTxInfo.PacketCount | (PMacTxInfo.SFD << 16);
2467 phy_set_bb_reg(Adapter, 0xb1c, bMaskDWord, u4bTmp);
2468 /* 0xb40 7:0 SIGNAL 15:8 SERVICE 31:16 LENGTH*/
2469 u4bTmp = PMacTxInfo.SignalField | (PMacTxInfo.ServiceField << 8) | (PMacTxInfo.LENGTH << 16);
2470 phy_set_bb_reg(Adapter, 0xb40, bMaskDWord, u4bTmp);
2471 u4bTmp = PMacTxInfo.CRC16[0] | (PMacTxInfo.CRC16[1] << 8);
2472 phy_set_bb_reg(Adapter, 0xb44, bMaskLWord, u4bTmp);
2473
2474 if (PMacTxInfo.bSPreamble)
2475 phy_set_bb_reg(Adapter, 0xb0c, BIT27, 0);
2476 else
2477 phy_set_bb_reg(Adapter, 0xb0c, BIT27, 1);
2478 } else {
2479 phy_set_bb_reg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount);
2480
2481 u4bTmp = PMacTxInfo.LSIG[0] | ((PMacTxInfo.LSIG[1]) << 8) | ((PMacTxInfo.LSIG[2]) << 16) | ((PMacTxInfo.PacketPattern) << 24);
2482 phy_set_bb_reg(Adapter, 0xb08, bMaskDWord, u4bTmp); /* Set 0xb08[23:0] = LSIG, 0xb08[31:24] = Data init octet*/
2483
2484 if (PMacTxInfo.PacketPattern == 0x12)
2485 u4bTmp = 0x3000000;
2486 else
2487 u4bTmp = 0;
2488 }
2489
2490 if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) {
2491 u4bTmp |= PMacTxInfo.HT_SIG[0] | ((PMacTxInfo.HT_SIG[1]) << 8) | ((PMacTxInfo.HT_SIG[2]) << 16);
2492 phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2493 u4bTmp = PMacTxInfo.HT_SIG[3] | ((PMacTxInfo.HT_SIG[4]) << 8) | ((PMacTxInfo.HT_SIG[5]) << 16);
2494 phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
2495 } else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2496 u4bTmp |= PMacTxInfo.VHT_SIG_A[0] | ((PMacTxInfo.VHT_SIG_A[1]) << 8) | ((PMacTxInfo.VHT_SIG_A[2]) << 16);
2497 phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2498 u4bTmp = PMacTxInfo.VHT_SIG_A[3] | ((PMacTxInfo.VHT_SIG_A[4]) << 8) | ((PMacTxInfo.VHT_SIG_A[5]) << 16);
2499 phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
2500
2501 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_SIG_B, 4);
2502 phy_set_bb_reg(Adapter, 0xb14, bMaskDWord, u4bTmp);
2503 }
2504
2505 if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2506 u4bTmp = (PMacTxInfo.VHT_SIG_B_CRC << 24) | PMacTxInfo.PacketPeriod; /* for TX interval */
2507 phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, u4bTmp);
2508
2509 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_Delimiter, 4);
2510 phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, u4bTmp);
2511
2512 /* 0xb28 - 0xb34 24 byte Probe Request MAC Header*/
2513 /*& Duration & Frame control*/
2514 phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, 0x00000040);
2515
2516 /* Address1 [0:3]*/
2517 u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2518 phy_set_bb_reg(Adapter, 0xb2C, bMaskDWord, u4bTmp);
2519
2520 /* Address3 [3:0]*/
2521 phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2522
2523 /* Address2[0:1] & Address1 [5:4]*/
2524 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2525 phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2526
2527 /* Address2 [5:2]*/
2528 u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2529 phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2530
2531 /* Sequence Control & Address3 [5:4]*/
2532 /*u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8) ;*/
2533 /*phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/
2534 } else {
2535 phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod); /* for TX interval*/
2536 /* & Duration & Frame control */
2537 phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, 0x00000040);
2538
2539 /* 0xb24 - 0xb38 24 byte Probe Request MAC Header*/
2540 /* Address1 [0:3]*/
2541 u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2542 phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, u4bTmp);
2543
2544 /* Address3 [3:0]*/
2545 phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2546
2547 /* Address2[0:1] & Address1 [5:4]*/
2548 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2549 phy_set_bb_reg(Adapter, 0xb2c, bMaskDWord, u4bTmp);
2550
2551 /* Address2 [5:2] */
2552 u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2553 phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2554
2555 /* Sequence Control & Address3 [5:4]*/
2556 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8);
2557 phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2558 }
2559
2560 phy_set_bb_reg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX);
2561
2562 /* 0xb4c 3:0 TXSC 5:4 BW 7:6 m_STBC 8 NDP_Sound*/
2563 u4bTmp = (PMacTxInfo.TX_SC) | ((PMacTxInfo.BandWidth) << 4) | ((PMacTxInfo.m_STBC - 1) << 6) | ((PMacTxInfo.NDP_sound) << 8);
2564 phy_set_bb_reg(Adapter, 0xb4c, 0x1ff, u4bTmp);
2565
2566 if (IS_HARDWARE_TYPE_JAGUAR2(Adapter)) {
2567 u32 offset = 0xb44;
2568
2569 if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
2570 phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
2571 else if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
2572 phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
2573 else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
2574 phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
2575
2576 } else if(IS_HARDWARE_TYPE_JAGUAR(Adapter)) {
2577 u32 offset = 0xb4c;
2578
2579 if(IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
2580 phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
2581 else if(IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
2582 phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
2583 else if(IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
2584 phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
2585 }
2586
2587 phy_set_bb_reg(Adapter, 0xb00, BIT8, 1); /* Turn on PMAC*/
2588 /* phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); */ /* TX Stop */
2589 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2590 phy_set_bb_reg(Adapter, 0xb04, 0xf, 8); /*TX CCK ON*/
2591 phy_set_bb_reg(Adapter, 0xA84, BIT31, 0);
2592 } else
2593 phy_set_bb_reg(Adapter, 0xb04, 0xf, 4); /* TX Ofdm ON */
2594
2595 if (PMacTxInfo.Mode == OFDM_Single_Tone_TX)
2596 mpt_SetSingleTone_8814A(Adapter, TRUE, TRUE);
2597
2598 return status;
2599 }
2600
2601 #endif
2602
hal_mpt_SetContinuousTx(PADAPTER pAdapter,u8 bStart)2603 void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
2604 {
2605 u8 Rate;
2606
2607 RTW_INFO("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx);
2608 Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
2609 pAdapter->mppriv.mpt_ctx.is_start_cont_tx = bStart;
2610
2611 if (Rate <= MPT_RATE_11M) {
2612 if (bStart)
2613 mpt_StartCckContTx(pAdapter);
2614 else
2615 mpt_StopCckContTx(pAdapter);
2616
2617 } else if (Rate >= MPT_RATE_6M) {
2618 if (bStart)
2619 mpt_StartOfdmContTx(pAdapter);
2620 else
2621 mpt_StopOfdmContTx(pAdapter);
2622 }
2623 }
2624
mpt_trigger_tssi_tracking(PADAPTER pAdapter,u8 rf_path)2625 void mpt_trigger_tssi_tracking(PADAPTER pAdapter, u8 rf_path)
2626 {
2627 #ifdef CONFIG_RTL8814B
2628 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2629 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
2630
2631 halrf_do_tssi_8814b(pDM_Odm, rf_path);
2632 #endif
2633 }
2634
2635 #endif /* CONFIG_MP_INCLUDE*/
2636